KR0158797B1 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

Info

Publication number
KR0158797B1
KR0158797B1 KR1019980014673A KR19980014673A KR0158797B1 KR 0158797 B1 KR0158797 B1 KR 0158797B1 KR 1019980014673 A KR1019980014673 A KR 1019980014673A KR 19980014673 A KR19980014673 A KR 19980014673A KR 0158797 B1 KR0158797 B1 KR 0158797B1
Authority
KR
South Korea
Prior art keywords
integrated circuit
semiconductor integrated
semiconductor
circuit
integrated
Prior art date
Application number
KR1019980014673A
Other languages
Korean (ko)
Inventor
Yoshihiro Takemae
Masao Taguchi
Yukinori Kodama
Makoto Yanagisawa
Takaaki Suzuki
Junji Ogawa
Atsushi Hatakeyama
Hirohiko Mochizuki
Hideaki Kawai
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP02017394A external-priority patent/JP3319120B2/en
Priority claimed from JP6025808A external-priority patent/JPH07234264A/en
Priority claimed from JP03513194A external-priority patent/JP3361875B2/en
Priority claimed from JP04956994A external-priority patent/JP3443923B2/en
Priority claimed from JP6110638A external-priority patent/JPH07321571A/en
Priority claimed from KR1019950003010A external-priority patent/KR0158762B1/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of KR0158797B1 publication Critical patent/KR0158797B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
    • H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
KR1019980014673A 1994-02-17 1998-04-24 Semiconductor integrated circuit KR0158797B1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP02017394A JP3319120B2 (en) 1994-02-17 1994-02-17 Synchronous semiconductor memory device
JP6025808A JPH07234264A (en) 1994-02-24 1994-02-24 Semiconductor integrated circuit
JP03513194A JP3361875B2 (en) 1994-03-07 1994-03-07 Synchronous semiconductor memory device
JP04956994A JP3443923B2 (en) 1994-03-18 1994-03-18 Semiconductor device
JP6110638A JPH07321571A (en) 1994-05-25 1994-05-25 Amplifier circuit and semiconductor integrated circuit using the same
KR1019950003010A KR0158762B1 (en) 1994-02-17 1995-02-17 Semiconductor device

Publications (1)

Publication Number Publication Date
KR0158797B1 true KR0158797B1 (en) 1998-12-01

Family

ID=27548907

Family Applications (3)

Application Number Title Priority Date Filing Date
KR1019980014673A KR0158797B1 (en) 1994-02-17 1998-04-24 Semiconductor integrated circuit
KR1019980014674A KR0183416B1 (en) 1994-02-17 1998-04-24 Synchronous semiconductor memory device and semiconductor integrated circuit
KR1019980014672A KR0158798B1 (en) 1994-02-17 1998-04-24 Synchronous memory device

Family Applications After (2)

Application Number Title Priority Date Filing Date
KR1019980014674A KR0183416B1 (en) 1994-02-17 1998-04-24 Synchronous semiconductor memory device and semiconductor integrated circuit
KR1019980014672A KR0158798B1 (en) 1994-02-17 1998-04-24 Synchronous memory device

Country Status (1)

Country Link
KR (3) KR0158797B1 (en)

Also Published As

Publication number Publication date
KR0158798B1 (en) 1998-12-01
KR0183416B1 (en) 1999-04-01

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Legal Events

Date Code Title Description
A107 Divisional application of patent
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee