JPH0723403A - Video phase adjustment circuit for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To correct a registration error of a solid-state image pickup device in a horizontal direction with high precision. CONSTITUTION:A drive pulse oscillated from a crystal oscillator 21 is fed to a transfer drive generator 22, from which red, green and blue vertical transfer pulses, a horizontal transfer start position (HCLR) and a clock signal are generated. The HCLR and the clock signal of each color is fed to delay lines 23R, 23B, 23G and converted into the delayed HCLR and the delayed clock signal according to delay data from delay data input devices 25R, 25G, 25B and fed to horizontal transfer pulse generating circuits 26R, 26G, 26B, whether the pulses are converted into horizontal transfer pulses. The phase of the horizontal transfer pulse is adjusted based on the delay data to correct a registration error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase adjusting circuit for a video signal read from a solid-state image pickup device,
In particular, a video phase adjusting circuit of a solid-state image pickup device, which decomposes an optical image of a subject into three primary colors of red, green and blue, and receives the separated three primary color images by a solid-state image sensor to extract red, green and blue signals, respectively. It is about.

[0002]

2. Description of the Related Art In recent years, as a television camera for broadcasting, a three-panel television camera using a solid-state image pickup element has been increasingly adopted. FIG. 1 shows a schematic configuration diagram of a three-plate type television camera. In this configuration, the image of the subject 1 is formed by the lens 2, and this image is separated into three colors by the three-color separation prism 3 of red, green and blue. The separated object images of the respective colors are converted into electric signals by the solid-state image pickup devices 4R, G, and B, respectively, and the signals are sent to the signal processing devices 5R, 5G, and 5B, and necessary signal processing is performed as an output signal of the television camera. . The processed signal is sent to the synthesizing device 6 to mix the signals of the respective colors at a predetermined ratio determined by the broadcasting system and output the image signal from the camera, or
Alternatively, each color signal is independently output to the outside of the camera, and an external device synthesizes each of the red, green, and blue signals to display a color image.

Next, in order to explain the operating principle of the solid-state image pickup device, the most common solid-state image pickup device, interline, is used.
The CCD will be described with reference to FIG. It should be noted that other image pickup devices have almost the same operating principle in the present invention.
The interline CCD 11 has light receiving elements 12 that convert light into electric charges, which are arranged in a matrix in a vertical direction and a parallel direction. The subject image formed on the image pickup surface of the image pickup element is divided at each point of the light receiving element 12 and converted into electric charges. The charges are transferred to the vertical CCD 13 adjacent to the light receiving element 12 in each column. The vertical CCD 13 has vertical transfer pulses φV1, φV2,
φV3 and φV4 are applied, and the charges vertically transferred by these pulses are transferred to the horizontal CCD 14. Horizontal CC
Horizontal transfer pulses φH1 and φH2 are applied to D 14, which are horizontally transferred by these pulses, and finally amplified by the output amplifier 15 and output to the output terminal 16. Here, the intervals of the vertical transfer pulses φV1, φV2, φV3 and φV4 must be synchronized with the vertical synchronizing frequency in each television system. The horizontal transfer pulses .phi.H1 and .phi.H2 are generated by using a crystal oscillator or the like as the original oscillation and by directly or counting down the oscillation. The oscillation frequency of the crystal oscillator or the like must be synchronized with the horizontal synchronizing frequency of each television system. Therefore, the intervals of the vertical transfer pulse and the horizontal transfer pulse for each pixel are given at the same intervals.

The light receiving elements 12 are arranged at equal intervals in the vertical and horizontal directions, and transfer pulses are also provided at equal intervals in the vertical and horizontal directions.
The video signal output from 11 is a signal obtained by dividing the subject image formed on the imaging surface of the image sensor at equal intervals in the horizontal and vertical directions.

When an image of a subject is formed on the image pickup element through the lens, the chromatic aberration of magnification of the lens causes a shift in the image formation among red, green and blue. The chromatic aberration of magnification occurs because the imaging magnification varies depending on the wavelength, and appears as a registration error in the television camera. In addition, the image is distorted due to distortion (lens distortion). Since the driving speed of the image pickup device is constant, output image signals can be obtained from the light receiving devices arranged at equal intervals without any time change according to the image pickup positions. Therefore, the distortion of the subject image on the imaging plane of the image sensor caused by the aberration or distortion of the lens is output from the image sensor without correction, and the output image is output when the image is captured by the camera using the solid-state image sensor. A registration error due to such aberration and distortion will inevitably occur in the signal.

As a method for electrically performing such registration correction, there is a method in which a video signal is once taken into a digital memory and then the reading of the memory is controlled. -282984, JP-A-02-284591, etc., a method for changing the oscillation frequency of the voltage controlled oscillator for generating horizontal and vertical transfer signals is described in JP-A-01-251888, A method of adjusting the horizontal frequency of the horizontal transfer pulse is disclosed in Japanese Patent Laid-Open No. 58-59690.

[0007]

However, when the video signal is once processed in the digital memory and then the read operation of the memory is controlled, an operation such as A / D conversion is required in order to load the video signal into the digital memory, etc. There is a drawback that there is a system limit such as noise. Also, when changing the oscillation frequency of the voltage-controlled oscillator that generates the horizontal transfer pulse and the vertical transfer pulse, or when adjusting the frequency of the horizontal transfer pulse, the oscillation frequency tends to become unstable because the frequency is moved. It has the drawback of making it difficult. In particular, when the frequency is changed within a short period of time, the voltage-controlled oscillator cannot change the oscillation frequency quickly in response to it, and the registration error cannot be accurately corrected. When correcting the video signal, it is necessary to return the change in the oscillation frequency of the voltage controlled oscillator for the correction performed during the video period to the original frequency within the horizontal blanking period. The horizontal blanking period is very short compared to the video period, and it is difficult to make the response of the voltage controlled oscillator follow this.

The present invention solves the above-mentioned drawbacks of the conventional system and provides a video phase adjusting circuit of a solid-state image pickup device capable of highly accurately correcting the registration error of the solid-state image pickup device, particularly in the horizontal direction. It is intended to be provided. Another object of the present invention is to provide a video phase adjusting circuit for a solid-state image pickup device, which is capable of giving a special effect to the geometrical dimensions of the screen.

[0009]

A video phase adjusting circuit of a solid-state image pickup device according to the present invention includes means for generating a reference transfer pulse for each of the three primary colors of red, green and blue, and a means for correcting a registration error. , Variable digital delay means for changing the phase of the reference transfer pulse by inputting registration error information for each color. Further, the video phase adjusting circuit of the solid-state imaging device of the present invention, in order to obtain a special effect on the geometrical dimension of the screen, inputs the information corresponding to the special effect for each color to determine the phase of the reference horizontal transfer pulse. And a variable digital delay means for changing.

[0010]

In the image phase adjusting circuit of the solid-state image pickup device of the present invention, by inputting the registration error information for each color as delay data, the variable digital delay means can delay the input pulse by the delay data. Is provided. For example, if the input pulse is 8 bits and the delay time for each delay data is t, the delay data 00
When 000000 is input to the variable digital delay means, an output pulse delayed by 0 · t (a pulse that is not delayed) is output.
In the following description, the left end of the delay data is the least significant bit and the right end is the most significant bit. Also, the delay data 10
If you enter 000000 and 01000000 respectively, 1 ・ t, 2 ・
t Output delayed output pulses respectively. Similarly, when delay data 11111111 is input, an output pulse (maximum delay pulse) delayed by 255 • t is output. Therefore, an output pulse delayed by 0 · t to 255 · t according to the delay data is output (see FIG. 3).

For example, the delay data in the normal state is a state in which the cycle of the horizontal transfer pulse is not delayed or shortened.
Let's say it is 00. Here, the delay data is incremented by 1 for each transfer cycle pulse, that is, the delay data is incremented by 00001000, 10
By changing to 001000 and 01001000 (FIGS. 4a to 4d), the delay data for the sequential input pulse is changed, and the interval of the output pulse of the variable digital delay means becomes wider (FIG. 4).
e). Also, the delay data is decreased by one for each clock, that is, the delay data is 01110000, 10110000, 001100.
When it is changed to 00 (FIGS. 5a to 5d), the delay data for the successive input pulses is changed, and the intervals of the output pulses of the variable digital delay means are gradually narrowed (FIG. 5e). As described above, by changing the delay data for each minimum unit of the variable delay element, the interval of the output pulse can be changed for each minimum unit of the variable delay element, and the pulse frequency apparently changes. In the present invention, the frequency of the transfer pulse is not changed, but the phase thereof is changed.

By appropriately performing these operations in one line, it is possible to correct the registration error in the horizontal direction of the solid-state image pickup device. For example, as shown in FIG. 7, in one line in the right half of the screen. By increasing the transfer frequency of the solid-state image element for each minimum unit of the variable delay element, the image on the right half of the screen can be reduced for each minimum unit of the variable delay element. Therefore, the image phase adjusting circuit of the solid-state image pickup device of the present invention enables
Since the interval of the transfer pulse for each pixel, that is, the phase can be controlled, it is possible to accurately correct the registration error of the solid-state imaging device. Further, by setting the above-mentioned delay data so as to obtain a special effect on the geometrical size of the screen, a desired special effect can be easily and accurately realized.

[0013]

FIG. 7 is a block diagram showing the configuration of an embodiment of a video phase adjusting circuit of a solid-state image pickup device according to the present invention.
In this example, the clock pulse output from the horizontal transfer pulse generator and the horizontal transfer start position (H CLR) are delayed by the delay data. The drive pulse oscillated from the crystal oscillator 21 is supplied to the transfer drive pulse generator 22 and is converted into red, green and blue vertical transfer pulses, H CLR and a clock. These H CLR and clock are variable delay lines 23R and 23 for each color.
The vertical transfer pulse is supplied to the CCDs 24R, 24G and 24B for each color. Above H CL
R and the clock are the delay data input device 25 for each color.
The variable delay lines 23R, 23G and 23B are delayed by a predetermined time according to the delay data supplied to the R, 25G and 25B to generate a delay H CLR and a delay clock. These delays H CLR and delay clocks are applied to the horizontal transfer pulse generation circuits 26R, 26G and 26B for each color.
To a horizontal transfer pulse. CC these horizontal transfer pulses together with the above vertical transfer pulses for each color.
Supply to D 24R, 24G and 24B. These CCD
Images of respective colors obtained by separating the subject image by the three-color separation optical system are made incident on 24R, 24G, and 24B.

FIG. 8 shows a method of forming a horizontal transfer pulse. In this example, the variable delay lines 23R, 23G and 2
3B is configured to be able to delay the input pulse by the delay data by receiving the delay data from the delay data input devices 25R, 25G and 25B, respectively. Here, the delay time for each data is T
Consider the case. When the delay data is incremented by 1 for each transfer cycle pulse, that is, the delay time is changed to 0T, 1T -5T (Figs. 8a to 8f), the delay time of the sequential input pulse becomes continuously longer, and the variable delay line becomes longer. The output pulses of 23R, 23G, and 23B appear to have a slower frequency (see FIG. 8).
g). On the contrary, if the delay data is decreased by one for each transfer cycle pulse, the delay time of the successive input pulses is continuously shortened, and the output pulse of the variable delay line apparently has a faster frequency. Since the interval of the horizontal transfer pulse for each pixel can be changed by appropriately performing these operations in one line, it is possible to accurately correct the registration error in the horizontal direction of the solid-state imaging device.

In FIG. 9a, CCDs 24R, 24G and 24B are shown.
9b shows the horizontal transfer pulse and CCD output when delay data is not input, and FIG. 9c shows the horizontal transfer pulse and CCD output when delay data is input. In FIG. 9a, the charge accumulated in pixel A is
It is transferred to “4” of horizontal CCD 32 via CCD 31. The horizontal CCD 32 is driven by the horizontal transfer pulse, as shown in FIG. 9b.
If the delay data is not input as shown in, the CCD output is output at time t. On the other hand, as shown in FIG. 9c, when delay data is input, the CCD output is output at time t ',
The CCD output is delayed by t'-t.

FIG. 10 shows a method of correcting a subject image on the image plane of the image sensor. The subject image 4 on the imaging surface 41 of the image sensor
When 2 is imaged as shown by the distortion of the lens, it is output on the horizontal scanning line 43 at time t. Subject image 41
In order to obtain a subject image 44 which is not affected by the distortion of the lens, the interval of the horizontal transfer pulse is appropriately delayed as described above so that it is output on the horizontal scanning line 43 at time t '. In this way, if the horizontal transfer pulse is not delayed, the effect of lens distortion can be corrected by delaying the signal that should be output at time t until time t '. Similarly, in order to correct the distortion in the right half of the subject image 42, by appropriately shortening the interval of the horizontal transfer pulse, the time u on the horizontal scanning line 43 is reduced.
It is possible to implement the signal which is to be output at by changing the phase of the video signal until time u '.

11A, 11B, and 11C, in order to move the starting point of the scanning line, the horizontal movement start position (H CLR) is changed according to the figure. . By performing the above operations independently for each red, green, and blue image sensor, the registration error is corrected for the distortion of the object image on the image plane of the image sensor caused by lens aberration or distortion. For example, trapezoidal distortion (solid line in FIG. 11a), pincushion distortion (FIG. 1).
1b), linear distortion (solid line in FIG. 11c)
It can be corrected by giving a delay as shown by a dotted line.

FIG. 12 shows a part of the configuration of the embodiment of the present invention shown in FIG. 7, FIG. 13 shows a correction waveform generated by the mix amplifier of FIG. 12, and FIG. 14 shows the waveform of FIG. Each of the converted waveforms is shown, and an example of a method of determining delay data will be described below. 12, the delay data input device 50 corresponds to the delay data input devices 25R, G and B of FIG. 7, the variable delay lines 51 and 52 correspond to the variable delay lines 23R, G and B, respectively, and a horizontal transfer pulse generation circuit. 53 is a horizontal transfer pulse generation circuit 26
Corresponds to R, G and B respectively. In this example, the variable delay lines 51 and 52 are 8 bits.

The delay data input device 50 comprises a mix amplifier 54 as a correction waveform creating circuit, an A / D converter 55 and a latch 56. The horizontal transfer pulse creating circuit 53 has a 1/2 frequency divider 57. , AND gate 58 and EX-OR gates 59 and 60. The mix amplifier 54 is the same circuit as the registration correction circuit of the image pickup tube camera. The mix amplifier 54 has a horizontal sawtooth waveform (H SAW), a vertical sawtooth waveform (V SAW), a horizontal parabola waveform (H PARABORA), and a vertical parabola waveform (V PARAB).
(ORA) is input to form an analog correction waveform as shown in FIG. When such a correction waveform is supplied to the A / D converter 55 and 8-bit A / D conversion is performed, the delay data between the time 0 and the time A is shown in FIG. Is not delayed or shortened 11110000
Data which is constant at, and gradually increases from time A to time B to finally become the delay data 11111111 is obtained. Here, the delay data increases linearly from time A to time B, but the interval of the horizontal transfer pulse during this time is constant. Therefore, when the horizontal transfer pulse interval is gradually shortened as shown in FIG. 6 during this period, the delay data is not required to be increased at a constant rate, but is required to be rapidly decreased over time.

The 8-bit delay data thus formed is supplied to the latch 56 and latched by the output clock from the variable delay line 51, and then the variable delay line 5
Input the addresses 1 and 52 to determine the delay amount. The latching is performed in order to prevent the delay data from changing before the variable delay line 51 outputs a signal for one clock, and this operation is unnecessary if the delay data is latched inside the variable delay line 51.

From the variable delay line 51, the clock pulse interval does not change from time 0 to time A, but from time A to time B, a clock pulse having a slightly narrower interval is output. On the other hand, H CLR is also delayed by the same amount as the clock, which is to determine H CLR of the CCD output.

The output clock from the variable delay line 51 is divided by 1/2 by the 1/2 divider 57, ANDed with H CLR by the AND gate 58, and the phases are mutually inverted by the EX-OR gates 59 and 60. This is a pulse, but this is the horizontal transfer pulse of the CCD. When the input clock has the same frequency as the horizontal transfer pulse, the 1/2 frequency divider 57 is not necessary. Here, the output clock is divided by two, and this is AND gated with H CLR to create a CCD horizontal transfer pulse. This is the reset pulse and S / H required to drive the CCD.
This is because when making a pulse, it is easier to adjust the pulse phase by making a clock with a double frequency. If the circuit may be complicated, the input clock passed through the variable delay line 51 may be the same as the CCD horizontal transfer pulse,
In this case as well, the 1/2 divider 57 is not necessary.

As a result of the above operation, the horizontal transfer pulse of the CCD has a normal pulse width from time 0 to A and has a slightly narrower pulse width from time A to time B, and the output image of the CCD is from time 0 to time A. Normally, the time is shortened from time A to time B (see FIG. 7). The output of the mix amplifier 54 can be transformed into various waveforms by changing the mix ratio and the like. That is, the CCD video output can be temporally shortened or extended to various waveforms,
As a result, the registration error can be corrected. The waveform control of the mix amplifier 54 may be performed by a microcomputer or the like.
P corresponds to this. The 8-bit data may be reproduced by calculating the correction data for one screen. The method of creating the delay data is not limited to the method described above, and various methods are conceivable. For example, the delay data may be directly controlled by a microcomputer or the like.

Various types of variable delay lines can be used as the variable delay line used in the above-mentioned embodiment. For example, commercially available products such as NTSC, PAL-B (Shojo Densen), HDTV (Elmec Co., Ltd.), etc. Variable delay line can also be used. Furthermore, in the above-described embodiment, the phase of the horizontal transfer pulse is controlled so as to correct the registration error for each color, but the present invention is not limited to such correction of registration error. Alternatively, special effects on the geometrical dimensions of the screen can be obtained. For example, a circular object shown by a solid line in FIG. 10 can be projected as an ellipse shown by a broken line.

[0025]

As described above, according to the video phase adjusting circuit of the solid-state image pickup device of the present invention, by inputting the registration error information for each color, the input pulse can be delayed by the delay data. Since the variable digital delay means capable of controlling the phase of the horizontal transfer pulse of the solid-state image pickup element can be changed by the variable digital delay means according to the delay data, the interval of the horizontal transfer pulse for each pixel can be changed. This has an effect that a horizontal registration error of the apparatus can be corrected with high accuracy. Further, the desired special effect can be easily realized by setting the delay data according to the special effect on the geometrical dimension of the screen.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a three-panel television camera.

FIG. 2 is an explanatory diagram of an operation of an interline CCD.

FIG. 3 (a) shows an input pulse to a variable delay line,
(B)-(e) respectively show the delayed output pulse.

4A to 4D show how delay data is added, and FIG. 4E shows an output pulse obtained as a result.

5A to 5D show how delay data is reduced, and FIG. 5E shows an output pulse obtained as a result.

FIG. 6 shows a state in which a right half image of a screen obtained as a result of performing the registration correction in the horizontal direction is contracted.

FIG. 7 shows a configuration of an embodiment of a video phase adjusting circuit of a solid-state image pickup device according to the present invention.

8A to 8F show how delay data is added, and FIG. 8G shows an output pulse whose frequency is apparently delayed.

9A is a CCD operation, and FIG. 9B is a horizontal transfer pulse and CCD output when delay data is not input.
(C) shows a horizontal transfer pulse and CCD output when delay data is input.

FIG. 10 is a diagram showing how a registration error of a subject image is corrected in the present invention.

11A shows how trapezoidal distortion is corrected, FIG. 11B shows pincushion-shaped distortion, and FIG. 11C shows linear distortion.

12 shows a configuration of the delay data input device and horizontal transfer pulse generation circuit of FIG.

13 shows a correction waveform obtained by the mix amplifier of FIG.

FIG. 14 shows a waveform obtained by A / D converting the waveform of FIG.

[Explanation of symbols]

1 subject 2 lens 3 three-color separation prism 4R, 4G, 4B solid-state imaging device 5R, 5G, 5B signal processing device 6 synthesis device 11 interline CCD 12 light receiving device 13, 31 vertical CCD 14, 32 horizontal CCD 15 output amplifier 16 output Terminal 17 Camera output range 18 CCD pixel 21 Crystal oscillator 22 Transfer drive pulse generator 23R, 23G, 23B, 51, 52 Variable delay line 24R, 24G, 24B CCD 25R, 25G, 25B, 50 Delay data input device 26R, 26G, 26B, 53 horizontal transfer pulse generation circuit 41 imaging element imaging plane 42, 44 subject image 43 horizontal scanning line 50 delay data 54 mix amplifier 55 A / D converter 56 latch 57 1/2 frequency divider 58 AND gate 59, 60 EX- OR gate

Claims (2)

[Claims] 1. A means for generating a reference horizontal transfer pulse for each of the three primary colors of red, green and blue, and the reference by inputting registration error information for each color in order to correct the registration error. A video phase adjusting circuit for a solid-state image pickup device, comprising: a variable digital delay means for changing the phase of a horizontal transfer pulse. 2. A means for generating a reference horizontal transfer pulse for each of the three primary colors of red, green and blue, and information for each color in order to obtain a special effect on the geometrical dimensions of the screen. A video phase adjusting circuit for a solid-state image pickup device, comprising: a variable digital delay means for changing the phase of the reference horizontal transfer pulse by inputting.