JPH0723295A - Image pickup device - Google Patents

Abstract

PURPOSE:To improve the vertical resolution of the video signal obtained by performing an image pickup by using a normal standard television and a CCD imager of a special specification by distributing and supplying the optical information on a subject obtained by a spectroscopic means to each image pickup means. CONSTITUTION:The image of one-frame taken by a same timing by using CCD imagers 3 and 4 is fetched by the same timing. By transferring the photo diode image picking-up the odd-numbered fields of the CCD imager 3 as it is, discharging the signal electric charge of the even-numbered fields and stopping the images from the photo diode corresponding to the odd-number by the one picture element shifting of a CCD imager 4 by one field, the information composed of all the picture elements for the portion of one-frame is made to be the video signal corresponding to a standard television signal. Thus, because the picture element information of a photographed subject is read by all the picture elements for the portion of one-frame in this video signal, vertical resolution can be improved, and moving resolution can be also maintained by outputting the signal at every field.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device for photographing incident light incident through an optical lens, and more particularly to an image pickup device capable of improving both dynamic resolution and vertical resolution.

[0002]

2. Description of the Related Art In a solid-state image pickup device such as a CCD (Charge Coupled Device) imager, an image pickup section is a photodiode corresponding to a light receiving section for photoelectrically converting incident light to obtain a signal charge and reading of the signal charge. And a signal reading section corresponding to the section. One of CCD imagers is an interline type.

In general, the interline CCD imager also constitutes a signal reading section provided at one end side of each photodiode of the light receiving section, and via a transfer gate for actually passing the signal charge obtained by the photodiode. The signal charges are transferred to the vertical transfer register and sequentially moved downward to take out the signal from the horizontal line reading unit.

The interline CCD imager has a field storage mode, a frame storage mode and the like. In addition to the above-described modes, the CCD imager can adopt an electronic shutter mode in which the photoelectric conversion time can be set to be short. The characteristics of these modes are as shown in Table 1.

[0005]

[Table 1]

In the field read mode, the signal charges accumulated in a plurality of photodiodes in this CCD imager are corresponding to the read pulse supplied to the vertical transfer registers corresponding to the odd lines and the vertical transfer registers corresponding to the even lines, respectively. And are supplied via a transfer gate. In this reading method, the signal charges from the vertical transfer registers are added and mixed with the signal charges for two lines in the order of, for example, an odd line and an even line in accordance with a read pulse supplied for each field in this reading method, and pixel information of an odd field is obtained. 2 in the order of the even line and the next odd line
Signal charges of lines are added and mixed, and as signals of even fields, signals of all pixels in both fields are output every vertical blanking period.

As described above, the CC in the field read mode
The D imager adds and mixes the signals simultaneously read out for two lines to generate image information of one field signal, and performs line-interlaced scanning of this image information for each field. By using information as each field signal and simultaneously reading out for each field, it is possible to complete half the sampling time required for the frame read mode (see the sampling time in Table 1). The field signal is a mode in which the charge accumulation time for each field is short, so that the correlation with time is good, and the dynamic resolution indicating the time resolution of a moving image can be excellently obtained.

The frame read mode is CC
The signal charges accumulated in the plurality of photodiodes in the D imager are transferred to the vertical transfer registers corresponding to the odd lines and the vertical transfer registers corresponding to the even lines in accordance with the read pulse supplied for each field. Supplied through. The signal charges from these vertical transfer registers are read independently without being mixed with the signal charges of the pixels on the odd line and the even line as described above in response to the supply of the vertical transfer pulse. In the frame read mode, the signal charges on the odd lines and the signal charges on the even lines are interlaced and scanned for each line and read in the odd field period and the even field period, respectively. That is, the signal charges in the odd field and the even field are read out for each frame.

Therefore, in the frame-reading type CCD imager, for example, when the picked-up image is a still image, the number of vertical transfer channels corresponding to the pixels expressing the image is larger than that in the field-reading type CCD imager. Many. For example, a normal NTSC CCD
Since the imager has about 250 lines, the vertical limit resolution of the output video signal is determined. This CCD
The imager can also obtain images with low flicker (see Table 1).

When a still image is viewed without using the electronic shutter as described above, different frames are displayed as shown in areas A and B of FIG. 15B with respect to, for example, the vertical synchronization timing shown in FIG. 15A. Even if the sampling timing of the information is different over the entire area, the two fields that are different from each other in the frame accumulation mode are interlaced to be scanned and read, so that the vertical resolution of the image of the area A and the image of the area B shown in FIG. Can be over 250 TV lines.

The electronic shutter mode is a field storage mode. A typical interline CCD imager has a vertical overflow drain structure CCD.
The electronic shutter operation is performed by sweeping unnecessary charges to the silicon substrate by using. Since this configuration does not require a memory area, it is easy to downsize.

The frame interline CCD imager has the same structure as the image pickup section of a normal interline CCD imager, but a memory area for accumulating image information for one field is provided below the image pickup section. I have it. The frame interline CCD imager can use this memory area to perform a variable electronic shutter operation. In this operation, a sweep charge read pulse is supplied at time T ₁ of a certain horizontal retrace period to temporarily read the charge accumulated in the photodiode into the vertical transfer register, and the signal of the photodiode is set to an empty state to restart photoelectric conversion. Start conversion. The signal charges read to the vertical transfer register are transferred downward by normal vertical transfer.

At time T ₂ in the vertical blanking period, the vertical transfer register sweeps out all the remaining charges as unnecessary charges to the outside by applying a high-speed sweep pulse. Next, the frame interline CCD imager supplies a signal charge read pulse at time T ₃ within this vertical blanking period to read the signal charge accumulated in the photodiode after time T ₁ into the vertical transfer register. The signal charges are transferred at high speed and read out and used as normal signal charges. Therefore, the time for the photodiode to perform photoelectric conversion is from time T ₁ to time T ₃ , and this exposure period can be set shorter than the normal one field or one frame period. 1/60 in NTSC system as shown
Shutter speeds from seconds to 1/10000 seconds are possible.

By using the electronic shutter in the field storage mode as described above, image sampling is performed in field units, so that the dynamic resolution, which is a feature of the field storage mode, can be increased. In this case, the information to be obtained is the image captured in the time regions C and D shown in FIG. 16 as is apparent from the above. At this time, by reading an image captured in an arbitrary fixed time, that is, the time region C or D in the field accumulation mode, the CCD
The imager readable pixel array comprises half of all pixels.

As described above, the photoelectric conversion time can be set shorter than the normal field period or the frame period, but as shown in Table 1, the signal reading is performed in the normal frame,
Alternatively, it is widely used because it is possible to easily improve the dynamic resolution by performing interlace scanning for one line in each field and simultaneously reading out two lines.

[0016]

By the way, in the above-mentioned field storage mode, the number of pixels is reduced because the pixels of two lines are added and mixed, and the vertical resolution is about 70% of that in the frame storage mode. Will fall to. Further, in the frame accumulation mode, since the accumulation time is longer than that in the field accumulation mode, there is a time lag between the location where photoelectric conversion is performed and the location of the signal actually read out for a rapidly moving subject, and a frame afterimage is generated. Will be generated. Therefore, in the frame accumulation mode, it is not always possible to obtain a high dynamic resolution for a moving image.

Therefore, in the conventional CCD imager, depending on the application to be used, either the field storage mode giving priority to the dynamic resolution or the frame storage mode giving priority to the vertical resolution is used.
It was necessary to change the reading method of the signal charge accumulated in the CD and select it to obtain necessary image information. As described above, since each mode has the above-mentioned drawbacks, it is inevitable that one of the dynamic resolution and the vertical resolution is lowered as long as these CCD imagers are used.

In recent years, the horizontal resolution of CCD imagers has generally become 500 TV lines or more along with the improvement in the number of pixels, and the resolution of peripheral devices has dramatically improved. There is a strong demand for improvement in the resolution of the entire image pickup apparatus.

In order to meet such a demand, at present, the number of elements in the horizontal and vertical directions apart from the CCD imager used in the high definition system having 2000 pixels in the horizontal direction and 1000 pixels in the vertical direction and the standard television system is provided. Special CCD imagers and the like having 1000 pixels are being provided. If these CCD imagers are used, these CCD imagers can obtain a resolution of about 500 TV lines even if half of the pixels in the vertical direction are used.

However, the CCD imager described above is very expensive and generally difficult to use. In particular, since the CCD imager in the electronic shutter mode performs image sampling of the video signal on a field-by-field basis, deterioration of the vertical resolution that occurs in the field accumulation mode described above remains.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and a normal standard television,
An object of the present invention is to provide an image pickup apparatus capable of significantly improving the vertical resolution of a video signal obtained by picking up an image using a CCD imager with high definition and special specifications.

[0022]

An image pickup apparatus according to the present invention is configured such that a spectroscopic unit that disperses incident light that is incident through an optical lens and each optical information about an object that is spectroscopically dispersed by the spectroscopic unit is electrically. A first and a second imaging means for simultaneously imaging and outputting using the exposure means, and a synthesizing means for synthesizing the output signals output from the first and second imaging means,
The above-mentioned problems are solved by the optical information about the subject obtained by the spectroscopic means being distributed and supplied to the respective imaging means to the first and second imaging means.

Here, the first and second image pickup means are
The optical information respectively supplied are simultaneously exposed and imaged by using an electrical exposure means, and one of the first and second imaging means reads out one of the imaging means. A configuration is provided in which a control unit that stops the field period and reads the imaging output is provided.

[0024]

In the image pickup apparatus according to the present invention, each light information obtained by splitting the incident light on the subject by the spectroscopic means is distributed and supplied to the first and second image pickup means through the electric exposure means, and simultaneously imaged. The images are combined by the combining means and output.

Further, in the image pickup apparatus, the control means controls the output of one of the image pickup outputs of the first and second image pickup means to be stopped for one field period so as to read out the field accumulation mode to obtain the dynamic resolution. While ensuring the above, the simultaneously captured images are output as a video signal with high vertical resolution obtained in the frame accumulation mode.

[0026]

Embodiments of the image pickup apparatus according to the present invention will be described below with reference to the drawings. Here, a case where an interline CCD imager is used for the image pickup unit will be exemplified.

FIG. 1 shows a schematic configuration of the first embodiment of the image pickup apparatus. The imaging apparatus shown in FIG. 1 is a prism 2 that is a spectroscopic unit that disperses incident light that enters through the optical lens 1, and each optical information about the subject that has been spectrally dispersed by the prism 2 is an electrical exposure unit. CCD imagers 3 and 4 that are first and second image pickup means that are simultaneously imaged and output using an electronic shutter, and a signal processing device as a synthesizing means that synthesizes output signals output from the CCD imagers 3 and 4. 5 and.

The signal processing device 5 comprises a preprocessor section 5A, a signal processing section 5B and an amplifier 5C. The preprocessor unit 5A is supplied when a different signal of the same signal is double-sampled from the signal generation unit 51 that generates a clock as a reference signal, the timing generation unit 52 that generates a timing signal, and the CCD imagers 3 and 4. It has a correlated double sampling unit (hereinafter, simply referred to as CDS) 53 that performs correlation of output signals and absorbs offset error.

As shown in FIG. 2A, a screen of a normally picked up image is composed of odd lines (O) of odd fields and even lines (E) of even fields. Here, the CCD imagers 3 and 4 shown in FIG. 1 capture the same image shown in FIG. 2 at the same timing (see FIG. 3).
(See (c) and (f)). At this time, the imaging device receives the read pulse shown in FIG.
By supplying the transfer pulse shown in FIG.
Only the line signals of the odd fields are output from the D imager 3 (see the line signal shown by the solid line in FIG. 2B). The even field line signal shown in FIG. 2C is discarded.

Further, in this image pickup device, the read pulse shown in FIG. 3D is supplied in a cycle twice as long as the read pulse shown in FIG. 3A, and then the even field line supplied to the vertical transfer register. The transfer pulse shown in FIG. 3 (e) in which the signal is matched with the timing of outputting the even line (E) in FIG. 3 (c) is supplied for a certain period. In response to the supply of this transfer pulse, the CCD imager 4 is moved to the position shown in FIG. 3 (g) after the vertical transfer is stopped for one field period, that is, the position corresponding to the even field in FIG. 3 (c). Only even fields are output (see FIG. 2C).

A CCD in which the same image is divided into two in this way
For example, the field signals supplied from the imagers 3 and 4 are switched for each field and subjected to signal processing corresponding to the standard television system to be combined to obtain a frame signal captured at the same timing (see FIG. See)).

Further, a more specific structure of the above-described image pickup device will be described with reference to the circuit structures of FIGS. 4 to 6, and the operation of the image pickup device will be described with reference to a timing chart of FIG. Further, FIG. 1 is also referred to when necessary.
Here, the downward negative pulse in FIG. 7A indicates that the operation of the image pickup apparatus is performed at the rising edge so as to be enlarged and shown.

Optical information incident through the optical lens 1 shown in FIG. 1 is split into two equal parts by the prism 2. After this, the CCDs to which the separated light information respectively correspond
It is incident on the imagers 3 and 4. Further, the CCD drive pulse for driving the CCD imagers 3 and 4 is a signal generator 51 and a timing generator 52 shown in FIGS.
And is supplied to the CCD imagers 3 and 4.

As shown in the schematic block circuit diagram of FIG. 4, the signal generating section 51 uses various synchronizing signals such as a horizontal synchronizing signal HD, a vertical synchronizing signal VD, and the above horizontal synchronizing signal as driving pulses for the CCD imager. The timing signals for the CCD imagers 3 and 4 are generated based on the frequency doubled signal 2FH having the frequency of 2 and the field index signal FLD indicating the periods of the odd field and the even field. CC for generating this timing signal
A timing signal corresponding to the D imager 3 is generated by the timing generation circuit 521a. Further, the timing signal corresponding to the CCD imager 4 is the timing generation circuit 5
21b.

Here, the timing generation circuit 521a.
Generates a pulse at a normal CCD driving timing. On the other hand, in the timing generation circuit 521b, the vertical synchronization signal VD 'which is the output signal from the timing control unit 522 is half the cycle of the horizontal synchronization signal with respect to the phase of the vertical synchronization signal VD supplied from the signal generation unit 51. ,
That is, it is supplied as a signal delayed by 1 / 2H. Therefore, the CCD imagers 3 and 4 have a relationship that the signal charges of the even field are always read in the odd field period and the signal charges of the odd field are read in the even field period as the read timing. This operation will be described in detail later.

Further, the timing controller 522 is
A control signal C shown in FIG. 7 based on the vertical synchronizing signal VD, the double frequency signal 2FH, and the field index signal FLD.
The ONT is created and supplied to the pulse control unit 523 and the changeover switch SW. The control signal CONT is the CCD
After the read pulse from the imager, the horizontal sync signal is 2H
It is a signal that changes at the timing when minutes have passed (FIG. 7).
(See (i)). When the control signal CONT is supplied, the CCD imager 4 temporarily suspends the output due to the transfer of the signal charges from the CCD imager 4 side for one field even when the read pulse is actually supplied.

Timing generation circuits 521a and 521b
Are supplied with the reference clock of each timing signal from the oscillator 526. The oscillator 526 supplies a signal having a frequency of 28 MHz, for example, as a reference clock. The timing generation circuit 521a supplies the horizontal register transfer clocks H1 and H2 and the precharge gate clock PG to the CCD imager 3, and vertically supplies the vertical register transfer clock timing signals XV1 to XV4 and the read pulse sensor gate clocks XSG1 and XSG2. The driver 525a is supplied.

Similarly, the timing generation circuit 521b supplies the horizontal register transfer clocks H1 and H2 and the precharge gate clock PG to the CCD imager 4, and the vertical register transfer clock timing signals XV1 to XV4 and the read pulse sensor gate clock XSG1. , XS
The vertical driver 525 for G2 via the pulse control unit 523
b. Regarding the pulse control unit 523, the circuit configuration and the like will be described later.

The vertical drivers 525a and 525b are
The vertical register transfer clocks V1 to V4 for driving the CCD and the charge sweep pulse SUB for sweeping the signal charge from the supplied timing signal to the overflow drain are supplied to the CCD imager 3 and 4 from the electronic shutter controller 524. The output is supplied according to the control signal XSUB for the sweep-out pulse. The electronic shutter control unit 524 generates the control signal XSUB for the electric charge sweeping pulse from the horizontal synchronizing signal HD and the field index signal FLD supplied from the signal generating circuit 51,
For example, 1/30 to 1/10 by shutter control of H unit
000 seconds or 1 / 25-1 / 10 according to CCIR standard
The shutter speed is controlled for 000 seconds.

The CCD imagers 3 and 4 output the output signals of one field obtained by picking up the same image at the same timing, that is, an odd field and an even field, respectively.
It is supplied to the CDS circuit 53a and the CDS circuit 53b of the DS section 53. The CDS circuit 53a and the CDS circuit 53b perform the correlated double integration processing on the supplied image pickup signal and output it to the terminals a and b of the changeover switch SW, respectively. The changeover switch SW outputs a terminal to the changeover signal processing section 5B for each field in accordance with the control signal CONT supplied from the timing control section 522. The signal processing unit 5B performs gain adjustment to correct the sensitivity difference between the outputs of the two CCD imagers 3 and 4, and further performs normal process processing. The signal processing unit 5B outputs a video signal obtained by converting a video signal captured at one frame simultaneous timing into a normal standard television system through an amplifier 5C and an output terminal 6.

A schematic circuit configuration of the timing control section 522 is shown in FIG. Timing control unit 522
Is mainly a counter circuit 16, a mono-multi circuit 19, D
-It is composed of flip-flops 17, 18 and 20.
In the timing controller 522, the field index signal is sent to the D-flip-flop 18 via the input terminal 11.
Is supplied to the input side of. Further, the power supply voltage of +5 V is supplied from the input terminal 12 to the power supply terminal V _DD of each circuit described above. The input terminal 13 is connected to the GND of each circuit. In addition, the vertical synchronizing signal VD from the input terminal 14 is D
-Supplied to the data input terminal D of the flip-flop 20.

Further, in the timing control section 522, the double frequency signal 2FH is supplied to the input terminal B of the monomulti circuit 19 and the clock input terminal CL of the counter 16 via the input terminal 15. Mono-multi circuit 19
Controls the pulse width of the frequency doubled signal 2FH with a capacitor C1 and a resistor R5 connected to the mono-multi circuit 19. The mono-multi circuit 19 has the GN input terminal A.
By connecting to the line D, the input signal of the input terminal B is inverted and output. Mono-multi circuit 19
Is inverted by passing through the input terminal B the pulse of the positive frequency doubled frequency signal 2FH, and is supplied from the output terminal Q to the clock terminal of the D-flip-flop 20 as a negative pulse. The D-flip-flop 20 inputs the vertical synchronizing signal VD to the data input terminal D as described above, but the vertical synchronizing signal VD shown in FIG. The vertical synchronizing signal VD ′ delayed by H / 2 of the horizontal synchronizing signal with respect to the vertical synchronizing signal VD by hitting and outputting with the output terminal 2
Output via 2.

The timing control unit 522 uses the counter circuit 1
6 inputs this vertical synchronizing signal VD 'as a load pulse. The counter circuit 16 uses the double frequency signal 2FH.
The clock is set to the up-count mode in which the step is incremented by one. This counter circuit 16
An initial value for starting counting is set by presetting the levels of the data input terminals A, B, C, and D.
This initial value is set by setting the data input terminals A, B, C and D to the levels "H", "L", "H" and "H", respectively, as is apparent from the connection relationship of FIG. . These 4 bits represent "1101" in binary notation. The counter circuit 16 presets the initial value at the load pulse level “L” and the rising edge of the clock, and starts counting up at the rising edge of the clock supplied thereafter. The counter circuit 16 is shown in FIG.
As shown in FIG. 5, the ripple carry signal RC is set to the D-flip-flop 17 when the double frequency signal 2FH counts 3 times.
It is supplied to the clock input terminal as the clock.

The D-flip-flop 17 is reset in the period of the level "L" by the supply of the vertical synchronizing signal VD 'output from the D-flip-flop 20. After that, the D-flip-flop 17 is operated by the counter circuit 1
At the rising edge from 6, the output signal of level "H" is output from the input terminal D, which is caught at +5 V, to the clock terminal of the D-flip-flop 18. The D-flip-flop 18 latches the field index signal FLD (FIG. 7 (g)) supplied to the input terminal D and outputs the control signal CONT from the inverting output terminal side via the output terminal 21 (FIG. 7 ( See i)).

The control signal CONT output from the timing controller 522 is supplied to the pulse controller 523. The pulse control unit 523 includes an inverter 32,
It is composed of AND gates 33 and 34 and OR gates 35 to 38. A control signal CONT supplied via the input terminal 25 is supplied to one end sides of the AND gates 33 and 34, respectively. Further, the control signal CONT is supplied to one end side of each of the OR gates 35 to 38 through the inverter 32. In the pulse control unit 523, the timing signals XV1 to XV4 for the vertical register transfer clock are input via the input terminals 26 to 31, respectively (FIG. 7).
(J), (m), (o) and (q)) and the sensor gate clocks XSG1 and XSG2 for the read pulse supplied for each field are AND gates 33, 34 and O.
It is supplied to the other ends of the R gates 35 to 38.

The AND gate 33 outputs a vertical register transfer clock timing signal XV1 'via the output terminal 39 as a logical product of the control signal CONT and the vertical register transfer clock timing signal XV1 (FIG. 7).
(See (k)). Similarly, the AND gate 34 also outputs the vertical register transfer clock timing signal XV2 ′ via the output terminal 40 as the logical product of the control signal CONT and the vertical register transfer clock timing signal XV2 (see FIG. 7 (k)). ). Further, the OR gates 35 and 36
7 and (n) and (p) of FIG. 7 from the output terminals 42 and 43 by ORing the control signal CONT and the timing signal XV3 for the vertical register transfer clock and the control signal CONT and the timing signal XV4 for the vertical register transfer clock, respectively.
The vertical register transfer clock timing signals XV3 'and XV4' are output as the logical sum output shown in FIG. The OR gates 37 and 38 are also the sensor gate clock XSG for the read pulse as the logical sum of the control signal CONT and the sensor gate clock XSG1 for the read pulse and the control signal CONT and the sensor gate clock XSG2 for the read pulse.
1 ′ and XSG2 ′ are output from the output terminals 43 and 44, respectively.

The vertical driver 525a shown in FIG. 4 uses the supplied timing signal X for the vertical register transfer clock.
Vertical register transfer clocks V1 to V4 generated based on V1 to XV4 are supplied to the CCD imager 3. Further, the electronic shutter control unit 524 supplies the control signal XSUB for the charge sweep-away pulse shown in FIG. 7 (r) to the vertical drivers 525a and 525b. Vertical driver 52
5a and 525b output SUB signals, respectively.

The CCD imager 3 in this case is shown in FIG.
The odd field signal imaged at the exposure time Ex shown in (r) is transferred to the CDS circuit 53a and output. Also CCD
As shown in FIG. 7 (s), the imager 4 outputs an even field signal imaged at the exposure time Ex at the same exposure time as shown in FIG. 7 (r) with a delay of one field.

As described above, the CCD imagers 3 and 4 simultaneously read from the photodiode PD to each register of the vertical transfer channel, but the CCD imager 3 reads the CCD output as it is, and the CCD imager 4 vertically in one field period. After the transfer is stopped, reading is performed, and the imaging device outputs a video signal obtained by capturing one frame at the same timing in a format according to a normal standard television signal.

Next, a pixel signal is shifted in the vertical direction by one pixel pitch with respect to the subject image incident through the optical lens, and a video signal obtained by capturing one frame at the same timing is converted into a format conforming to a normal standard television signal. A method for obtaining the above will be described with reference to the schematic diagram of FIG. Figure 8
Both (a) and (b) show the relationship between the photodiode and the vertical transfer channel. Here, the photodiodes forming the odd field lines are PD _O, and the photodiodes forming the even field lines are PD _E.
It is expressed as. Further, the vertical transfer register is constituted by a set of vertical transfer channels V1 to V4.

FIG. 8A shows the relationship between the photodiodes of the CCD imagers 3 and 4 used in the first embodiment and the vertical transfer channels. In this case, CCD
The correspondence between the photodiodes of the imagers 3 and 4 and the vertical transfer channels V1 to V4 is as follows: the photodiode PD _O and the vertical transfer channel V1, and the photodiode PD _E and the vertical transfer channel V, as indicated by the dotted arrows.
3 and 1 are in a one-to-one relationship.

A second embodiment of the image pickup apparatus according to the present invention will be described with reference to FIG. As shown in FIG. 8B, the relationship between the photodiodes of the CCD imagers 3 and 4 and the vertical transfer channels in the second embodiment is as follows. The photodiodes of the CCD imager are vertically displaced by one pixel. In fact, in the example shown in FIG. 8B, the pixels of the CCD imager 4 are vertically displaced from the CCD imager 3 by one pixel as indicated by the dashed line arrow. Along with the shift of the pixel (photodiode) in the vertical direction, the vertical transfer registers are also shifted by two in the vertical direction.

CC having the configuration arrangement shown in FIG.
The relationship between the images obtained by reading the images at the same timing using the D imagers 3 and 4 will be described with reference to the timing of FIG. The CCD imager 3 outputs the signal charges obtained by photoelectric conversion by the photodiode to the vertical transfer channel via the transfer gate according to the input of the read pulse shown in FIG. 9A. The vertical transfer channel is shown in Fig. 9 (b).
By the supply of the vertical transfer pulse, the CCD imager 3 alternately outputs the odd field (O) and the even field (E) shown in FIG. 9C.

The CCD imager 4 also takes images at the same timing as the CCD imager 3. The CCD imager 4 is supplied with a read pulse once per frame at the same timing as the read pulse of the CCD imager 3 shown in FIG. 9D. Here, the photodiode PD _O of the odd field of the CCD imager 4 of FIG.
By shifting the position of 1 pixel in the vertical direction,
It corresponds to the position of the photodiode PD _{E in} the even field of the CCD imager 3. Therefore, since the signal charge (see FIG. 9F) photoelectrically converted by the photodiode PD _O of the CCD imager 4 is taken out as an even field signal, the vertical transfer pulse of the CCD imager 4 is delayed by about 1 field. Point of time, ie CC
It is supplied to the even field of the D imager 3. As a result, the CCD imager 4 has a C
C at the position corresponding to the even field of the CD imager 3.
The field image picked up by the photodiode PD _O of the CD imager 4 is output.

In this way, the CCD imagers 3 and 4 both output the signal charge from the photodiode PD _O. By switching the output signals from the CCD imagers 3 and 4 in synchronism with the switching of the field signals, a video signal in which one frame shown in FIG. 9 (h) is captured at the same timing is in a format conforming to a normal standard television signal. Is output as a signal.

FIG. 10 shows a more specific block circuit configuration for realizing this operation. In FIG. 10, the same parts as those in FIG. 4 used in the first embodiment are designated by the same reference numerals and the description thereof is omitted. As described above, the block circuit shown in FIG. 10 reads the subject image at the same timing and operates, so that the timing generation circuit 52 can be operated if the drive capability of the output pulse can be sufficiently secured.
It has the feature that 1 is integrated into one.

The timing generation circuit 521 supplies the vertical register transfer clock timing signals XV1 to XV4 and the sensor pulse clocks XSG1 and XSG2 for the read pulse supplied for each field to the vertical driver 525a and the pulse controller 523A, respectively. There is. The timing generation circuit 521 uses the horizontal register transfer clock H.
1, H2 and precharge gate clock PG are supplied to the CCD imagers 3 and 4, respectively.

Here, the pulse control unit 523A supplies the result of the logical sum or the logical product with the control signal CONT from the timing control unit 522 to the vertical register transfer clock timing signals XV1 'to XV4' and for each field. Sensor gate clock XSG for read pulse
1 ', XSG2' are output to the vertical driver 525b. The vertical driver 525b supplies the vertical register transfer clocks V1 to V4 to the CCD imager 4 from the vertical register transfer clock timing signals XV1 'to XV4'.

As described above, the CCD imagers 3 and 4 transfer the signal charges for one frame captured at the same timing and output them to the CDS section 53 according to the timing of the signals supplied. In the CDS unit 53, offset error absorption processing is performed by correlating output signals supplied when different portions of the same signal are double-sampled, and output to the terminals a and b of the changeover switch SW, respectively. The changeover switch SW switches between the terminal a and the terminal b according to the control signal CONT. Changeover switch SW
Is output to the signal processing unit 5B (see FIG. 9 (h)). The signal processing unit 5B has a changeover switch S.
The output signal from W is processed into a video signal of the standard television system and output from the output terminal 6 via the amplifier 5C.

With this configuration, the CCD
An image of one frame captured by the imager 3 and the CCD imager 4 at the same timing is captured at the same timing, and the photodiode PD _O for picking up the odd field of the CCD imager 3 is transferred as it is and the signal charge of the even field is discarded. , By stopping the image from the photodiode PD _O corresponding to an odd number by shifting one pixel of the CCD imager 4 for only one field, information consisting of all pixels for one frame is converted into a video signal corresponding to a standard television signal. . This video signal can improve the vertical resolution because the pixel information of the photographed subject is read out by all the pixels for one frame, and the dynamic resolution can be maintained by outputting for each field.

The third aspect of the image pickup apparatus according to the present invention
FIG. 11 shows a case of using a circuit such as a field memory as an example of the above. This third embodiment also uses the same circuit configuration as in FIG. Here, the same parts as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.
However, configurations different from those in FIG. 4 will be briefly described below.

The timing generation circuit 521c shown in FIG.
The same vertical register transfer clock timing signals XV1 to XV as the timing generation circuit 521a have the same circuit configuration.
V4, sensor gate clock XSG for read pulse
1 and XSG2 are supplied to the vertical driver 525b.
The vertical driver 525b supplies vertical transfer clocks V1 to V4 from the vertical register transfer clock timing signals XV1 to XV4 and the read pulse sensor gate clocks XSG1 and XSG2, and drives the CCD imager 4 based on the vertical transfer clocks. ing. The CCD imager 4 outputs the output from the CDS circuit 53b via the memory unit 527 provided in the timing generation unit 52.

The memory section 527 is used for the A / D converter 52.
7a, field memory 527b, D / A converter 527
It is composed of c. The memory unit 527 has a CDS circuit 53.
The analog signal output from b is converted into an A / D converter 527.
a is converted into a digital signal and the field memory 527
supply to b. The field memory 527b stores a digital signal as data according to the control signal CONT supplied from the timing control unit 522. Further, the field memory 527b supplies the data in the memory to the D / A converter 527c according to the control signal CONT supplied from the timing control unit 522. D / A converter 527
c converts the digital signal read and supplied from the field memory 527b into an analog signal and outputs the analog signal to the terminal b side of the changeover switch SW.

The changeover switch SW is changed over to the terminal a side while storing it as data in the memory section 527 and sends the odd field signal from the CDS circuit 53a to the signal processing section 5B. In addition, the changeover switch S
Since W outputs an even field signal, W is switched to the terminal b side at a timing synchronized with the field signal. The signal processing unit 5B processes the supplied signal into a video signal compatible with the standard television system, and outputs the processed signal via the amplifier 5C and the output terminal 6.

As described above, by switching the signal charges obtained by the CCD imagers 3 and 4 at the same timing and photoelectrically converted for each field, and outputting them, it is possible to obtain a video signal having good vertical resolution and dynamic resolution.

Next, a fourth embodiment of the image pickup apparatus according to the present invention will be described with reference to FIG. Here, the same parts as those of the circuit configuration shown in FIG. The image pickup apparatus according to the fourth embodiment uses a spectroscope 2S that is a spectroscopic unit that disperses the incident light that is incident through the optical lens 1, and an electronic shutter that outputs optical information about a subject that has been spectrally separated by the spectroscope 2S. Two camera devices 3C and 4C as first and second interline type image capturing means for simultaneously capturing and outputting the same, and a signal as a synthesizing means for synthesizing output signals output from the two camera devices. The processing device 5 is used.

FIG. 13 is a block circuit diagram for explaining the block circuit configuration of the camera devices 3C and 4C and the signal processing device 5 in the image pickup device and the connection relationship between them. The signal processing device 5 includes a signal generation unit 51, a changeover switch SW, a SYNC addition processing unit 5D, and an amplifier 5C.

The two camera devices 3C and 4C have CCD imagers 3 and 4 respectively built therein, and further, the timing generation circuit 521, the electronic shutter controller 524, the vertical driver 525, and the oscillator used in the above-described embodiments. 5
26, the CDS circuits 53a and 53b, and the signal processing unit 5B are configured with exactly the same circuit configuration, and each camera device 3C,
4C includes a signal generation circuit 51S and a low-pass filter 5 for operating in synchronization with a reference signal supplied from the outside.
I also have 28.

Further, the camera device 4C is configured by adding the timing control unit 522 and the pulse control unit 523 for stopping the vertical transfer output for one field to the above-mentioned configuration. The timing control section 522 and the pulse control section 523 have exactly the same configuration as the detailed circuit configuration described in the first embodiment.

As described above, the timing generator 52 described above is used.
By incorporating the camera into the camera devices 3C and 4C,
The signal processing device 5 includes a signal generator 51 and a changeover switch S.
W, SYNC addition section 5D as a signal processing section, amplifier 5
It is possible to simplify the structure with C.

In this case, the signal generating unit 51 in the signal processing device 5 functions as an externally provided reference signal transmitting unit to the signal generating units 51S and 51S 'of the camera devices 3C and 4C, respectively. The sync signal EXVD is supplied, and the signal generator 51 supplies the electronic shutter controller 524 with the field index signal FLD and the external horizontal sync signal EXHD.

The signal generator 51S of the camera device 3C
Is a horizontal synchronization signal H based on a signal supplied from the outside.
The D and vertical synchronization signals VD are output to the timing generation circuit 521. In addition, the signal generator 51 of the camera device 4C
S ′ outputs the horizontal synchronization signal HD to the timing generation circuit 521 and the vertical synchronization signal VD to the timing control unit 522 based on the signal supplied from the outside. The signal generators 51S and 51S ′ supply the output signal H-COM from each camera device to the oscillator 526 via the low-pass filter 528. The oscillator 526 outputs a signal having a frequency of 28 MHz, for example, to the timing generation circuit 52.
1 is supplied as a reference clock.

The timing controller 522 inputs the signal 2FH having a frequency doubled from the vertical synchronizing signal VD, the field index signal FLD and the horizontal synchronizing signal. Based on these input signals, the timing control unit 52
2 generates a vertical synchronizing signal VD ′ and a control signal CONT whose timings are shifted compared with the vertical synchronizing signal VD and supplies them to the timing generation circuit 521 and the pulse control unit 523, respectively. These timing generation circuits 521, 52
1 supplies vertical register transfer clock timing signals timing signals XV1 to XV4 and read pulse sensor gate clocks XSG1 and XSG2 to the vertical driver 525a and the pulse control unit 523, respectively. Pulse control unit 523 built in the CCD imager 4
Are vertical register transfer clock timing signals XV1 to XV4, read pulse sensor gate clocks XSG1 and XSG2 to vertical transfer clock timing signals XV1 'to XV4', and read pulse sensor gate clocks XSG1 'and XSG2, respectively. 'Is generated and supplied to the vertical driver 525b.

The CCD imager 3 includes a vertical driver 52.
5a outputs the vertical transfer clocks V1 to V4 and the electric charge sweeping pulse SUB to supply an odd field signal to C
Output to the DS circuit 53a. Also, CCD imager 4
Supplies the vertical transfer clocks V1 to V4 and the charge sweeping-off pulse SUB output from the vertical driver 525b and outputs an even field signal to the CDS circuit 53b.

The CDS circuits 53a and 53b perform the correlated double integration processing to perform the signal processing section 5 of the camera devices 3C and 4C.
Changeover switch SW in the signal processing device 5 via B and 5B
Are supplied to terminals a and b, respectively. This changeover switch SW controls the control signal CON generated by the camera device 4C.
Switching control is performed according to T. The output signal output via the changeover switch SW is supplied to the SYNC addition circuit 5D. The signal generator 51 outputs the synchronization signal SYNC to the SY
It is supplied to the NC addition circuit 5D. SYNC addition circuit 5
The D outputs an output signal obtained by adding the synchronization signal SYNC to the supplied video signal via the amplifier 5C and the output terminal 6.

Even with such a configuration, by switching the signal charges that are picked up at the same timing and photoelectrically converted for each field and output, an image with good vertical resolution and dynamic resolution output from the camera devices 3C and 4C is obtained. You can get a signal.

Further, as a fifth embodiment of the image pickup apparatus according to the present invention, a case where the circuit configuration of the present invention is applied to a three-plate camera apparatus as a monochrome frame shutter camera will be described with reference to FIG. The image pickup apparatus according to the fifth embodiment includes a spectroscope 2S that is a spectroscopic unit that disperses the incident light that is incident through the optical lens 1, and the spectroscope 2S.
Three CCD imagers 3 for detecting respective color signals R, G, B as interline type first and second image pickup means for simultaneously photographing and outputting the optical information about the subject separated by S using an electronic shutter. 4, 7 and the three Cs
The signal processing device 5 is configured as a synthesizing unit that synthesizes output signals output from two CCD imagers of the CD imagers 3, 4, and 7.

As shown in FIG. 14, the spectroscope 2S has a 2
A CCD imager 3 for RGB for incident light by combining two color separation prisms, for example, a dichroic prism.
The light rays that are split into 4 and 7 are supplied. The signal processing device 5 includes a preprocessor 5A, a signal processing unit 5B, a changeover switch SW1 and an amplifier 5C.

The preprocessor 5A is the first processor described above.
The signal generating section 51, the timing generating section 52, and the CDS section 53 shown in FIG. Also,
The signal processing unit 5B includes a main signal processing unit 5Bm and a sub signal processing unit 5Bs.

The preprocessor 5A captures an image of one frame generated by photoelectric conversion at the same timing, divides the image into, for example, an odd field signal and an even field signal, and outputs the signals for each field. At this time, the preprocessor unit 5A outputs a monochrome video signal by combining two color signals of the three output signals corresponding to RGB. There are three possible combinations of color signals, G / R, G / B, and R / B. Using one of these combinations, two color signals corresponding to the standard television system described in the first embodiment are supplied to the sub signal processing unit 5Bs. Sub signal processing unit 5Bs
, A black and white image is formed by the supplied two color signals. This black-and-white image has a very high resolution because it is output by capturing the vertical resolution at the same timing. The sub-signal processing unit 5Bs performs signal processing corresponding to this black-and-white image so as not to reduce the resolution, and outputs the signal to the terminal b side of the changeover switch SW1.

The preprocessor 5A is a three-plate type R
The color signals R, G, B output from the GB compatible CCD imagers 3, 4, 7 are supplied to the main signal processing section 5Bm. Therefore, the main signal processing unit 5Bm outputs a normal color video signal to the terminal a side of the changeover switch SW1 using the output signals from the normal three-plate CCD imagers 3, 4, and 7.

The change-over switch SW1 is switched depending on whether a color image signal is desired to be obtained or a monochrome high-resolution image signal is desired to be obtained. By switching the changeover switch SW1, one of the video signals desired by the user is output via the amplifier 5C and the output terminal 6.

With such a configuration, it is possible to easily output one of a color video signal and a black and white high resolution video signal.

With the above arrangement, the above-mentioned high-resolution video signal can increase the vertical resolution of the picked-up image by reading out the signal charges at the same timing, and can be divided for each field. The dynamic resolution can be kept high by outputting the signal as image information for each of the odd field and the even field. As described above, the image pickup apparatus of the present invention can improve both the vertical resolution and the dynamic resolution of mutually contradictory images in which one is deteriorated and the other is deteriorated. In particular, the vertical resolution of the video signal will be greatly improved.

Further, even if a CCD imager is used, it is an NTSC system which is an ordinary standard television system, or P
The electronic shutter can be adapted to the slow shutter in 1/30 seconds to 1/60 seconds, or 1/25 seconds to 1/50 seconds in correspondence with the AL system, and the above-mentioned improvement of the video signal can be realized. You can

[0086]

According to the image pickup device of the present invention, each light information obtained by splitting incident light on a subject by the splitting means is distributed and supplied to the first and second image pickup means via the electrical exposure means. The control means performs control to stop the output of one of the read-out image pickup outputs of the first and second image pickup means for one field period by synthesizing and outputting the images captured at the same time by the synthesizing means. By outputting a video signal having a priority characteristic in the frame accumulation mode while reading, the signal charge can be read at the same timing to improve the vertical resolution of the captured image, and the signal divided for each field Is output as image information for each of the odd and even fields, the dynamic resolution can be kept high. That. As described above, the image pickup apparatus of the present invention can improve both the vertical resolution and the dynamic resolution of mutually contradictory images in which one is deteriorated and the other is deteriorated. In particular, the vertical resolution of the video signal can be greatly improved.

Further, in the above-mentioned reading method, even if a normal interline type CCD imager is used, the electronic shutter is 1/30 sec. To correspond to the normal standard television system NTSC system or PAL system. 1/6
The above-mentioned improvement of the video signal can be realized in 0 seconds, or in 1/25 seconds to 1/50 seconds.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of an image pickup apparatus in this embodiment.

2A is a diagram schematically showing a state in which an image for one frame is being scanned in the image pickup apparatus shown in FIG.
(B) is a schematic diagram showing scanning of odd fields, and (c) is a schematic diagram showing scanning of even fields.

3 is a timing chart for explaining an operation relationship when the same image is captured at the same timing in the image capturing apparatus shown in FIG.

FIG. 4 is a block circuit diagram showing a schematic configuration of a signal processing device used in the imaging device shown in FIG.

5 is a circuit diagram showing a specific circuit configuration of a timing control unit of the signal processing device in the imaging device shown in FIG.

6 is a circuit diagram showing a specific configuration of a pulse control unit provided in the signal processing device shown in FIG.

7 is a timing chart for explaining a circuit operation in the signal processing device shown in FIG.

FIG. 8A is a schematic diagram showing the relationship between a photodiode and a vertical transfer channel of the CCD imager used in the first embodiment, and FIG. 8B is a diagram showing C in the second embodiment.
It is a schematic diagram which showed the relationship of the photodiode of a CD imager, and a vertical transfer channel.

FIG. 9 is a timing chart for explaining in principle the operation when the CCD imager in the second embodiment shown in FIG. 8 is driven.

FIG. 10 is a block circuit diagram showing a specific configuration of a second embodiment of the image pickup device according to the present invention.

FIG. 11 is a block circuit diagram showing a specific configuration of a third embodiment of the image pickup device according to the present invention.

FIG. 12 is a block diagram showing a schematic configuration of a fourth embodiment of the image pickup apparatus according to the present invention.

13 is a block circuit diagram for explaining a circuit configuration and a connection relationship between each camera device and a signal processing device in the imaging device shown in FIG.

FIG. 14 is a block diagram showing a schematic configuration of a fifth embodiment of the image pickup apparatus according to the present invention.

FIG. 15 is a timing chart for explaining the operation in the frame accumulation mode in the conventional CCD imager.

FIG. 16 is a timing chart for explaining the operation when the electronic shutter mode is used in the conventional CCD imager.

[Explanation of symbols]

1 ... Optical lens 2 ... Prism 3, 4, 7 ... CCD imager 5 ... Signal Processor 6 ... Output terminal 5A ... Preprocessor 51 ... Signal generator 52 ... Timing generation unit 53 ... CDS unit 5B ... Signal processing unit 5C ... Amplifiers 521, 521a, 521b ... Timing generation circuit 522 ・ ・ ・ ・ ・ ・ ・ ・ Timing control unit 523 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Pulse control unit 524 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・・ ・ ・ Electronic shutter controller 525a, 525b ・ ・ ・ Vertical driver 526 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Oscillator 5 7 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Memory part 528 ・ ・ ・ ・ ・ ・ ・ ・ ・ LPF 5Bm ・ ・ ・ ・ ・ ・ ・ ・ ・ Main signal Processing unit 5Bs ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Sub signal processing unit SW, SW1 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Changeover switch

Claims (2)

[Claims] 1. A spectroscopic means for spectroscopically dividing incident light incident through an optical lens, and each optical information of a subject dispersed by the spectroscopic means is simultaneously imaged and output using an electrical exposure means. And a second image pickup means, and a synthesizing means for synthesizing the output signals output from the first and second image pickup means, wherein the first and second image pickup means are obtained by the spectroscopic means. An image pickup apparatus, wherein optical information about a subject to be captured is distributed and supplied to respective image pickup means. 2. The first and second image pickup means simultaneously expose and image the supplied optical information using an electrical exposure means, and one of the first and second image pickup means. 2. The image pickup apparatus according to claim 1, further comprising control means for reading the image pickup output by stopping the reading of the other image pickup means for one field period with respect to the reading of the image pickup means.