JPH07231046A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To increase the surface area of a capacitor electrode so as to increase the capacity of the capacitor and improve the memory characteristics by providing ruggedness on the top and side surfaces of the bottom electrode of the capacitor and providing ruggedness also on the top electrode plane that faces the bottom electrode of the capacitor. CONSTITUTION:Ruggedness is provided on the top and the side surfaces of the bottom electrode 16A of a capacitor, and the plane of a top electrode 19 that faces the bottom electrode 16A of the capacitor is also provided with ruggedness. Namely, after forming the pattern of the capacitor bottom electrode 16, many fine shielding particles, for example, high-polymer material 22 such as latex particles, are adhered to the whole surfaces of the capacitor bottom electrode 16. Then, the capacitor bottom electrode 16 is etched by using many fine shielding particles 22 adhered to the whole surface as a mask, and fine ruggedness is formed on the whole surface. A capacitor dielectric material 18 formed of silicon nitride film is formed on the bottom electrode 16A and a capacitor top electrode 19 is formed on the capacitor dielectric material 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (D having a memory cell structure of one transistor and one capacitor).
RAM) and its manufacturing method.

[0002]

2. Description of the Related Art The structure of a conventional semiconductor memory device will be described with reference to FIG. FIG. 26 is a partial cross-sectional view showing a 2-bit memory cell structure of a conventional semiconductor memory device.

In FIG. 26, 5 is a silicon oxide film for element isolation, 7 is a gate electrode of a MOS transistor, and 8 is a source / drain. Further, 9 is a silicon oxide film which is an insulating film, 10 is a silicon oxide film which is also an insulating film, 12 is a doped polysilicon film, 13 is a silicon tungsten (WSi) film, and 14 is a silicon oxide film which is an insulating film. Is. The doped polysilicon film 12 and the silicon tungsten film 13 form a bit line.

Further, 16 is a capacitor lower electrode composed of a doped silicon oxide film, 18 is a silicon nitride film or a capacitor dielectric composed of a silicon nitride film and a silicon oxide film, and 19 is a doped silicon oxide film. Is the upper electrode of the formed capacitor. A capacitor electrode 21 is composed of the capacitor lower electrode 16, the capacitor dielectric 18, and the capacitor upper electrode 19, and one capacitor electrode 21 is a charge (electron) equivalent to 1 bit.
Store. Further, 20 is a silicon oxide film which is an insulating film.

Next, a method of manufacturing the above-mentioned conventional semiconductor memory device will be described with reference to FIGS. 12 to 26. 12 to 25 are partial cross-sectional views showing a structure (2-bit memory cell) in each manufacturing process of a conventional semiconductor memory device.

First, an oxide film for element isolation is formed by the LOCOS method. That is, a silicon oxide film 2 is formed on an entire surface of a silicon substrate 1 in an oxidation furnace, a polysilicon film 3 and a nitride film 4 are deposited by a low pressure CVD method or the like, and then a photoresist is applied to a desired pattern by a photolithography method. To form. Then, as shown in FIG. 12, the polysilicon film 3 and the nitride film 4 are etched by dry etching to remove the resist.

Next, the above-mentioned substrate is put into the oxidation furnace again, and as shown in FIG.
As shown in FIG. 3, a silicon oxide film 5 for element isolation is formed. In the following figures, the silicon oxide film 2 on the silicon substrate 1 is not shown. Further, as shown in FIG. 14, a doped polysilicon film 6 is deposited on the entire surface of the substrate by a low pressure CVD method or the like. Then, as shown in FIG. 15, after the gate electrode 7 of the MOS transistor is formed on the substrate by photolithography and etching, phosphorus is implanted on the entire surface to form the source / drain 8. next,
As shown in FIG. 16, LDD (lightly Doped Drain)
For formation, the silicon oxide film 9 is formed on the side wall of the gate electrode 7 by the low pressure CVD method, anisotropic etching or the like.
After that, phosphorus is further injected into the source / drain 8.

Next, as shown in FIG. 17, a silicon oxide film 10 as an insulating film is deposited on the entire surface of the substrate by a low pressure CVD method or the like, and then a contact hole 11 is formed by a photolithography method.
To form. Thereafter, as shown in FIG. 18, a doped polysilicon film 12 and a silicon tungsten (WSi) film 13 are deposited on the entire surface of the substrate by a low pressure CVD method or the like, and then a bit line is formed by a photolithography method and etching.

Further, as shown in FIG. 19, after a silicon oxide film 14 which is an insulating film is deposited by a low pressure CVD method or the like, a contact hole 1 for a lower electrode of a capacitor electrode is formed.
5 is formed.

Next, as shown in FIG. 20, phosphorus-doped polysilicon 16 which is a material for the lower electrode of the capacitor electrode is deposited on the entire surface of the substrate by a low pressure CVD method or the like. At this time, irregularities are formed on the surface of the phosphorus-doped polysilicon film 16 by changing the conditions of the low pressure CVD method, for example, by lowering the temperature from a normal deposition temperature. In addition, the unevenness on the drawing is schematically shown.

Further, as shown in FIG. 21, a photoresist 17 is applied to the entire surface of the substrate,
As shown in FIG. 2, a desired pattern 17 is formed by photolithography.

Then, as shown in FIG. 23, the phosphorus-doped polysilicon film 16 is etched by using the resist pattern 17 as a mask, and after removing the resist, a capacitor lower electrode 16 is formed as shown in FIG. .

Subsequently, as shown in FIG. 25, a capacitor dielectric 18 composed of a silicon nitride film or a silicon nitride film and a silicon oxide film is deposited by a low pressure CVD method or the like, and a doped silicon oxide film is further formed on the entire surface. Capacitor upper electrode 19 is deposited by a low pressure CVD method or the like.

Then, as shown in FIG. 26, an insulating film 2 such as a silicon oxide film for insulating from other metal wiring.
0 is deposited by a low pressure CVD method or the like.

In this type of memory cell in the conventional example,
As shown in FIG. 26, the unevenness formed on the upper and lower parts of the capacitor lower electrode 16 and the capacitor upper electrode 19 was utilized to increase the capacitor capacity. That is, the electric charge (electrons) stored in the capacitor electrode 21 disappears with the passage of time, so the larger the capacitor capacity, the better,
The surface area was increased by utilizing the irregularities.

[0016]

In order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the capacitor electrode as described above. To increase the surface area while keeping the projected area of one capacitor electrode viewed from the upper surface of the substrate constant or small, increase the thickness of the capacitor electrode and increase its side area. , There is a way to increase the surface area. However, if the thickness of the capacitor electrode is increased by that method, the step difference between the peripheral circuit portion and the memory cell portion becomes too large, and there is a drawback that photolithography of aluminum (Al) wiring or the like cannot be performed at once. . Therefore, in the above-described conventional semiconductor memory device, unevenness is provided on the upper surface of the lower electrode 16 of the capacitor electrode 21 in order to increase the surface area without increasing the thickness of the capacitor electrode. It is possible to increase by about 1.2 to 1.3 times compared with the above.) In manufacturing, since the side surface of the capacitor lower electrode 16 is not provided with irregularities, its surface area cannot be increased sufficiently and the capacitor capacitance cannot be increased sufficiently. There was a problem.

The present invention has been made to solve the above-mentioned problems, and by increasing the surface area of the capacitor electrode, the capacity of the capacitor can be sufficiently increased, and the memory characteristics can be improved. And its manufacturing method.

[0018]

A semiconductor memory device according to claim 1 of the present invention is a semiconductor memory device having a memory cell of one transistor and one capacitor, and an unevenness is formed on the upper and side surfaces of the lower electrode of the capacitor. And the unevenness is also provided on the facing surface of the upper electrode facing the lower electrode of the capacitor.

A method of manufacturing a semiconductor memory device according to a second aspect of the present invention includes the following steps. [1] A first step of depositing a large number of fine shields on the entire surface of the capacitor lower electrode after forming the pattern of the capacitor lower electrode. [2] A second step of etching the capacitor lower electrode by using a large number of fine shields attached to the entire surface as a mask to form a large number of fine recesses on the entire surface. [3] A third step of forming a capacitor dielectric on the capacitor lower electrode on which the large number of fine recesses are formed, and forming a capacitor upper electrode thereon.

[0020]

In the semiconductor memory device according to the first aspect of the present invention, the side surface of the lower electrode of the capacitor is provided with irregularities, and the opposing surface of the side surface of the upper electrode of the capacitor is also provided with irregularities. As a result, the surface area of the capacitor electrode can be increased more than ever, and the capacitance of the capacitor can be increased.

In the method of manufacturing a semiconductor memory device according to claim 2 of the present invention, after the patterning of the capacitor lower electrode is performed by the first step, a large number of fine shields are attached to the entire surface of the capacitor lower electrode. To be made. Also, in the second step, the capacitor lower electrode is etched by using the large number of fine shields attached to the entire surface as a mask to form a large number of fine recesses on the entire surface. Further, in the third step, the capacitor dielectric is formed on the capacitor lower electrode in which the large number of fine recesses are formed, and the capacitor upper electrode is formed thereon.

[0022]

【Example】

Example 1. The structure of the first embodiment of the present invention will be described with reference to FIG. FIG. 10 shows the first embodiment of the present invention.
2 is a partial cross-sectional view showing the memory cell structure (2 bits) of FIG. 1 and is the same as that of the conventional device described above except for the capacitor electrode 21A. In each figure, the same reference numerals indicate the same or corresponding parts.

In FIG. 10, the capacitor electrode 21A
Is a capacitor lower electrode 16A composed of a doped silicon oxide film, and a capacitor dielectric 18 composed of a silicon nitride film or a silicon nitride film and a silicon oxide film.
And a capacitor upper electrode 19 composed of a doped silicon oxide film. Note that one capacitor electrode 21A stores a charge (electron) corresponding to 1 bit.

Next, a method of manufacturing the semiconductor memory device according to the first embodiment described above will be described with reference to FIGS. 1 to 9 are partial sectional views showing the structure (2-bit memory cell) in each manufacturing process of the semiconductor memory device according to the first embodiment of the present invention. Note that FIG.
Up to the steps shown in FIG. 12 are the same as those in the conventional example shown in FIGS.

As shown in FIG. 1, phosphorus-doped polysilicon 16 which is a material for the lower electrode of the capacitor electrode is deposited on the entire surface of the substrate by the low pressure CVD method.

Next, as shown in FIG. 2, a photoresist 17 is applied on the entire surface of the substrate, and then, as shown in FIG.
A desired pattern 17 is formed by photolithography as shown in FIG.

Subsequently, as shown in FIG. 4, the phosphorus-doped polysilicon film 1 is formed by using the pattern 17 as a mask.
6 is etched to form the capacitor lower electrode 16.

Next, as shown in FIG. 5, the diameter is 0.1 μm.
A spherical polymer material 22 having a diameter of m or less and a substantially uniform diameter is attached to the substrate. The projected area of the capacitor lower electrode 16 when viewed from above is, for example, about 0.8 μm in length and about 0.5 μm in width, and therefore the size of the polymer material 22 is 0.1 μm in diameter.
It was selected to be less than μm. The specific attachment method is as follows.
The polymer material 22 such as 1 μm latex (Latex) particles (rubber) is soaked and passed through a liquid such as suspended water so that the polymer material 22 is attached to the entire surface of the substrate. Note that FIG. 5 is a schematic diagram, and in reality, the polymer material 22 is randomly attached to the entire surface of the substrate. The latex particles are sticky and adhere to the sidewall of the capacitor lower electrode 16.

Further, as shown in FIG. 6, the capacitor lower electrode 16 is dry-etched by using, for example, a mixed gas of chlorine and oxygen or a mixed gas of chlorine and SF _{6 with} the polymer material 22 as a shield. Then the capacitor lower electrode 1
A depression (recess) is formed on the entire surface of 6. The surface of the silicon oxide film 14 is not affected by the dry etching.

Then, as shown in FIG.
2 is removed by applying ultrasonic waves in water or a mixed solution of aqueous ammonia and aqueous hydrogen peroxide. As a result, for example,
When the polymer material 22 having a diameter of 0.05 μm is adhered at a rate of about 100 pieces / μm ² to the capacitor lower electrode 16A having a projected area of 0.8 μm in the vertical direction and 0.5 μm in the horizontal direction, the capacitor lower electrode 16A The surface area of can be increased by about 1.5 to 2 times that of the one without irregularities.

Subsequently, as shown in FIG. 8, a capacitor dielectric 18 composed of a silicon nitride film or a silicon nitride film and a silicon oxide film is formed to have a uniform film thickness by a low pressure CVD method or the like. As shown, the capacitor upper electrodes 19 made of a doped silicon oxide film are opposed to each other.
Is deposited by a low pressure CVD method or the like. Although not shown in FIG. 9, a slight dent may occur on the surface of the capacitor upper electrode 19 corresponding to the depression of the capacitor lower electrode 16A.

Finally, as shown in FIG. 10, an insulating film 2 such as a silicon oxide film for insulating from other metal wiring.
0 is deposited.

As described above, the capacitor lower electrode 16
The fine hemispherical depressions (recesses) provided on the entire surface of A significantly increase the surface area as compared with the conventional example, and thus increase the capacitance of the capacitor. Therefore, according to the first embodiment, the electric charge (electrons) stored in the capacitor electrode 21A can be increased, and thus the memory characteristic of the semiconductor memory device can be improved. In particular, even when the semiconductor memory device is miniaturized, one capacitor electrode 21 is provided as described above.
There is an effect that the surface area of A can be widened.

Example 2. Although the polymer material 22 of FIG. 5 was used as the shield in the above-mentioned Example 1, in this Example 2, instead of the polymer material 22, a spherical shape having a diameter of 0.1 μm or less was used. The silicon oxide film is used.

After the capacitor lower electrode 16 of FIG. 4 is formed, the whole is inserted into a CVD apparatus in a vacuum, and what was normally treated as a foreign substance is positively discharged under the condition that the foreign substance is easily discharged. A minute silicon oxide film having a diameter of 0.1 μm or less is deposited on the entire surface of the substrate at a deposition temperature lower than the temperature by, for example, about 10 ° C. like the polymer material 22 shown in FIG. By doing so, it is possible to form a shield similar to that in the first embodiment, and etching is performed using the shield as a mask to form a large number of recesses as in FIG.
After that, the fine silicon oxide film, which is a shield, is dipped in a hydrofluoric acid solution, melted, and removed.

Example 3. Further, in the above-mentioned Example 1, the case where the polymer material 22 shown in FIG. 5 was used as the shield was shown, but in this Example 3, instead of the polymer material 22, as shown in FIG. A photoresist 23 having a diameter of 0.1 μm or less and used in the photoengraving method is used.

The phosphorus-doped polysilicon film 16 shown in FIG. 4 is etched using the pattern 17 as a mask,
After the capacitor lower electrode 16 is formed, a photoresist is applied on the entire surface, and then the photoresist is plasma-treated by a resist removing (asher) device using an oxidation plasma, so that the photoresist has a diameter of 0.1 μm.
It utilizes the phenomenon that remains in the conical shape of
As shown in FIG. 11, a minute photoresist 23 having a diameter of 0.1 μm or less is attached to the entire surface of the substrate. By doing so, a shield similar to that of the first embodiment can be formed, and the capacitor lower electrode (doped polysilicon) 16 is etched using this shield as a mask to form a large number of recesses as in FIG. Then, the photoresist 23, which is a shield, is washed with a mixed solution of sulfuric acid and hydrogen peroxide to remove the photoresist 23.

Incidentally, FIG. 11 shows a state immediately before the photoresist 23 is completely removed by the asher device. Even under the present circumstances, the photoresist 23 is completely removed by the asher device
Is difficult to remove, and a large number of photoresists having a diameter of 0.1 μm (for example, 1000 to 2000 pieces / 6 inch φ wafer) remain. Therefore, it is possible to create the state shown in the figure without adjusting the time and performing overashing.

[0039]

As described above, the semiconductor memory device according to claim 1 of the present invention is a semiconductor memory device having memory cells of one transistor and one capacitor, and is formed on the upper and side surfaces of the lower electrode of the capacitor. Since the unevenness is provided and the facing surface of the upper electrode facing the lower electrode of the capacitor is also provided with the unevenness, the surface area of the capacitor electrode can be increased, so that the capacitance of the capacitor electrode can be increased, which in turn improves the memory characteristics. There is an effect that can be done. In particular, even when the device is miniaturized, the surface area of each capacitor electrode can be increased.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising:
A first step of depositing a large number of fine shields on the entire surface of the capacitor lower electrode; and a step of etching the capacitor lower electrode using the fine shields attached to the entire surface as a mask And a third step of forming a capacitor dielectric on the capacitor lower electrode on which the large number of minute recesses are formed, and forming a capacitor upper electrode thereon. Therefore, the manufactured semiconductor memory device has an effect that the surface area of the capacitor electrode can be increased, so that the capacitance of the capacitor electrode can be increased, and the memory characteristic can be improved. In particular, even when the device is miniaturized, the surface area of each capacitor electrode can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a partial cross section in a step of a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a partial cross section in a step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a partial cross section in a step of the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a partial cross section in a step of the method of manufacturing the semiconductor memory device according to Embodiment 1 of the present invention.

FIG. 5 is a diagram showing a partial cross section in a step of the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a partial cross section in a step of the method of manufacturing the semiconductor memory device according to Embodiment 1 of the present invention.

FIG. 7 is a diagram showing a partial cross section in a step of the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a partial cross section in a step of the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a partial cross section in a step of the method of manufacturing the semiconductor memory device according to Embodiment 1 of the present invention.

FIG. 10 is a diagram showing a partial cross section of the memory cell structure of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 11 is a diagram showing a partial cross section in a step of the method of manufacturing the semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 12 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 13 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 14 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 15 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 16 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 17 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 18 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 19 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 20 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 21 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 22 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 23 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 24 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 25 is a diagram showing a partial cross section in a step of the method for manufacturing the conventional semiconductor memory device.

FIG. 26 is a diagram showing a partial cross section of a memory cell structure of a conventional semiconductor memory device.

[Explanation of symbols]

 1 Silicon substrate 2 Silicon oxide film 3 Polysilicon film 4 Nitride film 5 Silicon oxide film for element isolation 6 Doped polysilicon film 7 Gate electrode 9 Silicon oxide film 10 Silicon oxide film 12 Doped polysilicon 13 WSi film 14 Silicon film 16 Phosphorus-Doped Polysilicon Film 16A Capacitor Lower Electrode 18 Capacitor Dielectric 19 Capacitor Upper Electrode 20 Insulating Film 21A Capacitor Electrode 22 Polymer Material 23 Photoresist

Claims (2)

[Claims] 1. A semiconductor memory device having a memory cell of one transistor and one capacitor, wherein unevenness is provided on the upper and side surfaces of the lower electrode of the capacitor, and the upper electrode facing the lower electrode of the capacitor is opposed. A semiconductor memory device having unevenness on its surface. 2. After patterning the lower electrode of the capacitor,
The first step of depositing a large number of fine shields on the entire surface of the capacitor lower electrode, etching the capacitor lower electrode using the fine shields attached to the entire surface as a mask, A second step of forming fine recesses, and a third step of forming a capacitor dielectric on the capacitor lower electrode on which the large number of fine recesses are formed and forming a capacitor upper electrode thereon. A method of manufacturing a semiconductor memory device, comprising: