JPH07230952A - Recrystallizing method - Google Patents
Recrystallizing methodInfo
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- JPH07230952A JPH07230952A JP4202194A JP4202194A JPH07230952A JP H07230952 A JPH07230952 A JP H07230952A JP 4202194 A JP4202194 A JP 4202194A JP 4202194 A JP4202194 A JP 4202194A JP H07230952 A JPH07230952 A JP H07230952A
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- Prior art keywords
- thin film
- film
- substrate
- semiconductor layer
- semiconductor
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、大電流デバイス,高耐
圧デバイス,耐放射線デバイス,3次元デバイスなどに
利用され、絶縁性基板上の半導体薄膜を再結晶化する再
結晶化方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recrystallization method for recrystallizing a semiconductor thin film on an insulating substrate, which is used for large current devices, high breakdown voltage devices, radiation resistant devices, three-dimensional devices and the like.
【0002】[0002]
【従来の技術】絶縁性基板上に単結晶半導体薄膜を形成
する技術(SOI技術)は、SOI構造が、その構造上
の特徴から、寄生容量の低減,素子の完全分離,3次元
構造への対応が可能であり、デバイスの高速化,高集積
化,多機能化が期待されることから、近年盛んに研究さ
れている。2. Description of the Related Art In the technology for forming a single crystal semiconductor thin film on an insulating substrate (SOI technology), the SOI structure is characterized by its structural features such as reduction of parasitic capacitance, complete isolation of elements, and three-dimensional structure. It has been actively researched in recent years because it is possible to deal with it, and it is expected that the device will have higher speed, higher integration, and higher functionality.
【0003】絶縁性基板上に単結晶半導体薄膜を形成す
る方法としては、図14に示すように、絶縁性基板10
1上に多結晶あるいは非晶質の半導体薄膜102を形成
した後、種々の加熱法(レーザー加熱,カーボンストリ
ップヒーター加熱,ハロゲンランプ加熱,電子ビーム加
熱,カーボンサセプタを用いた高周波加熱等)を用い、
加熱源あるいは基板101を走査して、半導体薄膜10
2を連続的に溶融,再結晶化して単結晶化する手法が用
いられている。As a method of forming a single crystal semiconductor thin film on an insulating substrate, as shown in FIG.
After a polycrystalline or amorphous semiconductor thin film 102 is formed on 1, various heating methods (laser heating, carbon strip heater heating, halogen lamp heating, electron beam heating, high frequency heating using a carbon susceptor, etc.) are used. ,
The semiconductor thin film 10 is scanned by scanning the heating source or the substrate 101.
A method of continuously melting and recrystallizing 2 to form a single crystal is used.
【0004】この際、安定した溶融,再結晶化を行なう
ために、一般には、半導体薄膜102上にさらに表面保
護膜103が形成される。また、処理能力を向上するた
めに、半導体薄膜102の溶融領域を広くとることが考
えられる。しかしながら、広い溶融領域の上を、表面保
護膜103が覆っただけの状態では、融液のゆらぎを十
分には抑えきれず、図15に示すように、得られた単結
晶半導体薄膜(再結晶化膜)102’の表面形状に不規
則な凹凸が生じ、溶融領域がはじけて半導体薄膜10
2’に穴があくビードアップ現象が生ずることがある。
この場合には、得られた単結晶半導体薄膜102’上に
デバイス等を作成するとき、デバイス等の特性にばらつ
きが生じたり、歩留りが低下したりするなどの問題が生
じる。At this time, in order to perform stable melting and recrystallization, a surface protective film 103 is generally formed on the semiconductor thin film 102. In addition, it is conceivable to widen the melting region of the semiconductor thin film 102 in order to improve the processing capacity. However, in the state where the surface protection film 103 only covers the wide melting region, the fluctuation of the melt cannot be sufficiently suppressed, and as shown in FIG. 15, the obtained single crystal semiconductor thin film (recrystallized Irregular surface irregularities are formed on the surface of the oxide film) 102 ', and the melted region pops off, resulting in the semiconductor thin film 10'.
There may be a bead-up phenomenon in which 2'has a hole.
In this case, when a device or the like is formed on the obtained single crystal semiconductor thin film 102 ′, there arise problems such as variations in the characteristics of the device or the like and a decrease in yield.
【0005】このような問題を回避するため、例えば特
開昭59−229815号に示されているように、絶縁
性基板上の複数の領域にSiの半導体層(半導体薄膜)
をアイランド状に形成し、アイランド状に形成された半
導体層(半導体薄膜)を連結して、溶融再結晶させるこ
とが考えられる。図16は絶縁性基板101上に半導体
層(半導体薄膜)202をストライプ状のパターンに、
あるいは上記文献のように連結したアイランド状のパタ
ーンに形成した場合を示す図であり、このように、半導
体層(半導体薄膜)をパターニングすることによって、
溶融領域が規則的に細かく分割されると同時に、表面保
護膜も溶融領域ごとに分割され、融液の変動を効果的に
抑えることができるので、不規則な表面形状の乱れやビ
ードアップを防止することができる。In order to avoid such a problem, for example, as disclosed in JP-A-59-229815, a semiconductor layer (semiconductor thin film) of Si is formed in a plurality of regions on an insulating substrate.
It is conceivable that the semiconductor layers (semiconductor thin films) formed in the shape of islands are connected to each other and melted and recrystallized. FIG. 16 shows a semiconductor layer (semiconductor thin film) 202 on an insulating substrate 101 in a stripe pattern,
Alternatively, it is a diagram showing a case of forming a connected island-shaped pattern as in the above document, and by patterning the semiconductor layer (semiconductor thin film) in this way,
The melted area is regularly divided into smaller parts, and the surface protection film is also divided into melted areas so that fluctuations in the melt can be effectively suppressed, preventing irregular surface shape irregularities and bead-ups. can do.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、図16
に示すように半導体層(半導体薄膜)をパターニングす
るときには、半導体層(半導体薄膜)のパターンに応じ
て内部応力が発生するという問題が新たに生じる。すな
わち、半導体層(半導体薄膜)が何らかの形状でパター
ニングされていると、パターン側面の表面保護膜と半導
体層(半導体薄膜)との境界において、半導体薄膜の再
結晶化時(固化時)の体積変化に伴う応力が境界面に垂
直方向に発生し、ストライプ状あるいは連結したアイラ
ンド状などのように連結したパターンでは、パターンの
側面に沿って連続的に一定方向の応力が加わることにな
り、双晶等の欠陥が発生し易くなるという問題が生じ
る。However, as shown in FIG.
When patterning the semiconductor layer (semiconductor thin film) as shown in (3), a new problem arises that internal stress is generated according to the pattern of the semiconductor layer (semiconductor thin film). That is, when the semiconductor layer (semiconductor thin film) is patterned in some shape, the volume change during recrystallization (solidification) of the semiconductor thin film at the boundary between the surface protective film on the pattern side and the semiconductor layer (semiconductor thin film). Is generated in the direction perpendicular to the boundary surface, and in a pattern that is connected in a stripe shape or a connected island shape, stress in a fixed direction is continuously applied along the side surface of the pattern. There arises a problem that defects such as the above are likely to occur.
【0007】本発明は、絶縁性基板上に半導体層(半導
体薄膜)を形成し、該半導体層(半導体薄膜)を溶融し
て再結晶化する際、半導体層(半導体薄膜)の安定した
溶融領域を実現することができるとともに、再結晶化後
の半導体層(半導体薄膜)に欠陥が発生するのを有効に
防止することの可能な再結晶化方法を提供することを目
的としている。According to the present invention, when a semiconductor layer (semiconductor thin film) is formed on an insulating substrate and the semiconductor layer (semiconductor thin film) is melted and recrystallized, a stable molten region of the semiconductor layer (semiconductor thin film) is obtained. It is an object of the present invention to provide a recrystallization method capable of realizing the above and effectively preventing the occurrence of defects in the semiconductor layer (semiconductor thin film) after recrystallization.
【0008】[0008]
【課題を解決するための手段および作用】本発明の再結
晶化方法では、先ず、図1に示すような層構成の半導体
材料基板を形成する。すなわち、図1の例では、支持体
である絶縁性基板1上に、単結晶化されるべき多結晶あ
るいは非晶質の半導体層(半導体薄膜)2を形成し、こ
の半導体層(半導体薄膜)2上に表面保護膜3を形成す
る。ここで、絶縁性基板1としては、石英ガラス,セラ
ミック等の耐熱性を有する絶縁性基板の他に、金属ある
いは半導体の表面にSiO2,Si3N4等の絶縁性材料
を形成したものをも用いることができる。なお、絶縁性
基板1の厚さは通常0.3〜3.0mm程度である。In the recrystallization method of the present invention, first, a semiconductor material substrate having a layer structure as shown in FIG. 1 is formed. That is, in the example of FIG. 1, a polycrystalline or amorphous semiconductor layer (semiconductor thin film) 2 to be single-crystallized is formed on an insulating substrate 1 which is a support, and this semiconductor layer (semiconductor thin film) is formed. The surface protection film 3 is formed on the surface 2. Here, as the insulating substrate 1, in addition to an insulating substrate having heat resistance such as quartz glass or ceramic, a substrate on which an insulating material such as SiO 2 or Si 3 N 4 is formed on the surface of metal or semiconductor is used. Can also be used. The insulating substrate 1 usually has a thickness of about 0.3 to 3.0 mm.
【0009】また、単結晶化されるべき多結晶あるいは
非晶質の半導体層(半導体薄膜)2は、例えば、Si,
Ge等の半導体材料を各種CVD法,真空蒸着法,スパ
ッタ法等の成膜法により、0.1〜3.0μm程度の厚
さに成膜して形成される。The polycrystalline or amorphous semiconductor layer (semiconductor thin film) 2 to be single-crystallized is, for example, Si,
It is formed by forming a semiconductor material such as Ge into a film having a thickness of about 0.1 to 3.0 μm by a film forming method such as various CVD methods, a vacuum evaporation method, and a sputtering method.
【0010】この際、本発明においては、図2により詳
細に示すように、この半導体層(半導体薄膜)2に複数
の穴状の微細欠損部分(以下ピットと呼ぶ)4を形成す
る。なお、図2は、図1の半導体層(半導体薄膜)2の
B−B線における横断面図である。このようなピット4
は、通常のフォトリソグラフィ工程を用いて形成するこ
とができ、ピット4の間隔については、半導体層(半導
体薄膜)2の溶融,再結晶化の過程時(加熱時)に半導
体層(半導体薄膜)2に形成される溶融領域6内にピッ
ト4が少なくとも1つ以上含まれるような間隔で(より
具体的には、加熱時に形成される溶融領域6内において
ピット4が約500μm程度以内の間隔で)、隣接して
存在するように形成されるのが良い。At this time, in the present invention, as shown in more detail in FIG. 2, a plurality of hole-shaped fine defect portions (hereinafter referred to as pits) 4 are formed in the semiconductor layer (semiconductor thin film) 2. Note that FIG. 2 is a cross-sectional view of the semiconductor layer (semiconductor thin film) 2 of FIG. 1 taken along the line BB. Such a pit 4
Can be formed by using a normal photolithography process. Regarding the interval between the pits 4, the semiconductor layer (semiconductor thin film) is formed in the process of melting and recrystallization of the semiconductor layer (semiconductor thin film) 2 (during heating). At intervals such that at least one pit 4 is included in the molten region 6 formed in 2 (more specifically, at an interval of about 500 μm or less in the molten region 6 formed during heating). ), Preferably formed so that they are adjacent.
【0011】また、表面保護膜3は、例えば、上記のよ
うにして形成された半導体層(半導体薄膜)2上に、S
iO2,SiN等の絶縁性薄膜を各種CVD法,真空蒸
着法,スパッタ法等の成膜法により5000Å〜3mm
程度の厚さで成膜して形成される。The surface protective film 3 is formed on the semiconductor layer (semiconductor thin film) 2 formed as described above, for example, by S.
Insulating thin films such as iO 2 and SiN are formed by various CVD methods, vacuum deposition methods, sputtering methods, etc.
It is formed by forming a film with a certain thickness.
【0012】図3は複数のピット4が存在する半導体層
(半導体薄膜)2上に表面保護膜3を形成したときの拡
大図(図1の部分拡大図)である。図3からわかるよう
に、半導体層(半導体薄膜)2には、ピット4が存在す
るため、その部分では表面保護膜3が直接、絶縁性基板
1の表面に形成されることになる。これにより、表面保
護膜3は、約500μm程度以内の間隔で、絶縁性基板
1の表面に固定されるような構造となる。FIG. 3 is an enlarged view (partially enlarged view of FIG. 1) when the surface protective film 3 is formed on the semiconductor layer (semiconductor thin film) 2 having a plurality of pits 4. As can be seen from FIG. 3, since the semiconductor layer (semiconductor thin film) 2 has the pits 4, the surface protective film 3 is directly formed on the surface of the insulating substrate 1 at that portion. As a result, the surface protective film 3 has a structure in which it is fixed to the surface of the insulating substrate 1 at intervals of about 500 μm or less.
【0013】しかる後、このように形成した半導体材料
基板をレーザー加熱,カーボンストリップヒーター加
熱,ハロゲンランプ加熱,高周波加熱等により加熱し、
半導体層(半導体薄膜)2を溶融しながら、加熱源ある
いは基板1を相対的に0.1mm/秒〜10mm/秒程
度の走査速度で走査する。この場合、上記のような構造
とすることによって、加熱時には、半導体層(半導体薄
膜)2の溶融領域6上の表面保護膜3が基板1に固定さ
れ、半導体層(半導体薄膜)2の融液は、表面保護膜3
により変動(ゆらぎ)が抑えられ、表面に不規則な凹凸
が発生したりビードアップが生ずるのを著しく低減でき
て、安定した溶融領域を実現できる。Thereafter, the semiconductor material substrate thus formed is heated by laser heating, carbon strip heater heating, halogen lamp heating, high frequency heating, etc.,
While heating the semiconductor layer (semiconductor thin film) 2, the heating source or the substrate 1 is relatively scanned at a scanning speed of about 0.1 mm / sec to 10 mm / sec. In this case, with the structure as described above, the surface protection film 3 on the molten region 6 of the semiconductor layer (semiconductor thin film) 2 is fixed to the substrate 1 during heating, and the melt of the semiconductor layer (semiconductor thin film) 2 is melted. Is the surface protective film 3
As a result, fluctuations (fluctuations) can be suppressed, irregular irregularities on the surface and bead up can be significantly reduced, and a stable melting region can be realized.
【0014】また、半導体層(半導体薄膜)が何らかの
形状でパターニングされていると、前述のように、パタ
ーン側面の表面保護膜と半導体層(半導体薄膜)の境界
において、再結晶化時(固化時)の体積変化に伴う応力
が境界面に垂直方向に発生し、ストライプ状,あるいは
連結したアイランド状等のように連続したパターンで
は、前述のように、パターンの側面に沿って連続的に一
定方向の応力が加わることになり、双晶等の欠陥が発生
し易くなる。これに対し、本発明では、半導体層(半導
体薄膜)2中に微細なピット4が散在するようなパター
ンとなっており、このようなパターンでは、パターン側
面の表面保護膜3と半導体層(半導体薄膜)2との境界
が、微小であり、かつ、連続していないため、連続的に
一定方向の応力が加わることがない。これによって、双
晶等の欠陥の発生を抑えることができる。When the semiconductor layer (semiconductor thin film) is patterned in some shape, as described above, at the boundary between the surface protective film on the side surface of the pattern and the semiconductor layer (semiconductor thin film), recrystallization (solidification) occurs. ) The stress due to the volume change is generated in the direction perpendicular to the boundary surface, and in a continuous pattern such as a stripe shape or a connected island shape, as described above, a constant direction is continuously applied along the side surface of the pattern. Stress is applied, and defects such as twins are likely to occur. On the other hand, in the present invention, the pattern is such that the fine pits 4 are scattered in the semiconductor layer (semiconductor thin film) 2. In such a pattern, the surface protective film 3 on the side surface of the pattern and the semiconductor layer (semiconductor layer) Since the boundary with the thin film 2 is minute and not continuous, stress in a fixed direction is not continuously applied. This makes it possible to suppress the occurrence of defects such as twins.
【0015】このように、本発明では、半導体層(半導
体薄膜)2を連続的に再結晶化するときに、表面凹凸お
よびビートアップが少なく、さらに、欠陥の発生も少な
い単結晶半導体層(単結晶半導体薄膜)を得ることがで
きる。As described above, according to the present invention, when the semiconductor layer (semiconductor thin film) 2 is continuously recrystallized, the surface roughness and the beat-up are small, and further, the number of defects is small. A crystalline semiconductor thin film) can be obtained.
【0016】なお、本明細書において、「半導体層」と
「半導体薄膜」とは同じ意味の語,すなわち同義語とし
て用いている。In this specification, the terms "semiconductor layer" and "semiconductor thin film" are used as the same meaning, that is, synonyms.
【0017】[0017]
【実施例】以下、本発明の実施例を説明する。 (実施例1)図4は実施例1で用いた基板の層構成を示
す図である。実施例1では、支持体である絶縁性基板1
として、厚さ500μmの石英基板を用い、この基板1
上に、半導体層(半導体薄膜)2として、多結晶Si膜
2をLP−CVD法により3300Åの膜厚に形成し
た。しかる後、通常のフォトリソグラフィ工程により、
図5により詳細に示すように、多結晶Si膜2に一辺が
10μmの正方形のピット4aを、加熱時に形成される
溶融領域6内において300μm以内の間隔で隣接する
ように形成した。なお、図5は図4のC−C線における
横断面図である。次に、このようにパターニングされた
多結晶Si膜2上に表面保護膜3として、SiO2膜を
LP−CVD法により1.3μmの厚さに形成した。EXAMPLES Examples of the present invention will be described below. (Embodiment 1) FIG. 4 is a view showing the layer structure of the substrate used in Embodiment 1. In Example 1, the insulating substrate 1 which is a support
As the substrate 1, a quartz substrate having a thickness of 500 μm is used.
As the semiconductor layer (semiconductor thin film) 2, a polycrystalline Si film 2 was formed thereon by LP-CVD to a film thickness of 3300Å. After that, by a normal photolithography process,
As shown in more detail in FIG. 5, square pits 4a each having a side of 10 μm were formed in the polycrystalline Si film 2 so as to be adjacent to each other within a distance of 300 μm in the melting region 6 formed during heating. Note that FIG. 5 is a cross-sectional view taken along the line CC of FIG. Next, as the surface protection film 3, a SiO 2 film having a thickness of 1.3 μm was formed as a surface protection film 3 on the thus patterned polycrystalline Si film 2.
【0018】また、このように作成した半導体材料基板
と比較するために、半導体層(半導体薄膜)2として、
図6(a),(b)に示すように、材料,成膜法,膜厚
等は同じであるが、パターニングのなされていない多結
晶Si膜22を用いた基板(図6(a))と、幅xが1
00μm、間隔yが10μmのストライプ状のパターン
30にパターニングした多結晶Si膜32を用いた基板
(図6(b))とを用意した。Further, as a semiconductor layer (semiconductor thin film) 2, for comparison with the semiconductor material substrate thus prepared,
As shown in FIGS. 6A and 6B, a substrate using a polycrystalline Si film 22 having the same material, film forming method, film thickness, etc., but not patterned (FIG. 6A) And the width x is 1
A substrate (FIG. 6B) using a polycrystalline Si film 32 patterned into a stripe-shaped pattern 30 of 00 μm and an interval y of 10 μm was prepared.
【0019】上記のようにして形成した実施例1の基板
(多結晶Si膜2にピット4が形成されている基板)に
対して、図7に示すようなレーザー加熱装置でレーザー
加熱法を用いて多結晶Si膜2の溶融再結晶化を行なっ
た。なお、この際、このレーザー加熱装置のレーザー6
01には、ビーム径1.5mm,出力10WのArレー
ザーを用い、レーザー601からのレーザービームを一
軸テーブル607上に置かれた基板605に垂直入射す
るようにミラー602で反射させ、ビームエキスパンダ
ー603によってビーム径を10倍に拡大し、さらに、
シリンドリカルレンズ604によって、ビームを長軸1
5mm,短軸4mmのだ円形に絞り込み、基板605に
照射した。基板605全体をセラミックヒーター606
上で500℃にバイアス加熱し、一軸テーブル607を
走査速度0.1mm/秒で、レーザービーム短軸方向に
移動することによって、基板605を走査した。A laser heating method is applied to the substrate of Example 1 (the substrate having the pits 4 formed in the polycrystalline Si film 2) formed as described above by a laser heating apparatus as shown in FIG. Then, the polycrystalline Si film 2 was melted and recrystallized. At this time, the laser 6 of this laser heating device
As 01, an Ar laser having a beam diameter of 1.5 mm and an output of 10 W is used. A laser beam from the laser 601 is reflected by a mirror 602 so as to be vertically incident on a substrate 605 placed on a uniaxial table 607, and a beam expander 603 is provided. The beam diameter is expanded 10 times by the
With the cylindrical lens 604, the beam has a long axis 1
The substrate 605 was irradiated with the light by narrowing it down to an ellipse having a length of 5 mm and a minor axis of 4 mm. The whole substrate 605 is a ceramic heater 606.
The substrate 605 was scanned by bias heating to 500 ° C. above and moving the uniaxial table 607 at a scanning speed of 0.1 mm / sec in the short axis direction of the laser beam.
【0020】この結果、実施例1の多結晶Si膜2は、
図8に示すように、長軸10mm,短軸0.7mmのだ
円形に近い形状702で溶融し、走査に従って幅10m
mの再結晶化Si膜2’が連続的に得られた。As a result, the polycrystalline Si film 2 of Example 1 was
As shown in FIG. 8, the major axis 10 mm and the minor axis 0.7 mm are melted in a shape close to an ellipse 702, and a width of 10 m is obtained by scanning.
The recrystallized Si film 2'of m was continuously obtained.
【0021】パターニングしていない多結晶Si膜22
を用いた基板(図6(a))と、ストライプ状にパター
ニングした多結晶Si膜32を用いた基板(図6
(b))とについても、同様の方法で再結晶化を行なっ
た。なお、ストライプ状にパターニングした多結晶Si
膜32を用いた基板では、レーザービーム長軸方向が、
ストライプの長手方向Zと直交するようにレーザービー
ムを照射し、ストライプの長手方向Zに沿って基板を走
査した。Unpatterned polycrystalline Si film 22
And a substrate using a polycrystalline Si film 32 patterned in a stripe shape (FIG. 6A).
Also for (b)), recrystallization was performed by the same method. In addition, polycrystalline Si patterned in a stripe shape
In the substrate using the film 32, the major axis direction of the laser beam is
A laser beam was irradiated so as to be orthogonal to the longitudinal direction Z of the stripe, and the substrate was scanned along the longitudinal direction Z of the stripe.
【0022】次表(表1)は、それぞれの再結晶化膜
2,22,32について、膜の表面形状,ビードアップ
の有無,欠陥の形態を比較したものである。The following table (Table 1) compares the recrystallized films 2, 22, 32 with respect to the surface shape of the film, the presence or absence of bead-up, and the morphology of defects.
【0023】[0023]
【表1】 [Table 1]
【0024】なお、表1において、表面形状について
は、表面保護膜(SiO2膜)3をフッ酸系エッチング
液で除去した後、触針式の表面形状測定装置を用いて再
結晶化膜の凹凸を測定し、その最大値と最小値との差
の、再結晶化前の多結晶膜Siの膜厚に対する割合が示
されている。その結果、パターニングなしの多結晶Si
膜22を用いた基板では、最大で8%の凹凸が再結晶化
膜全体に不規則に形成されたのに対し、実施例1のピッ
トパターンをもつ多結晶Si膜2を用いた基板では、凹
凸は最大でも3%と小さくなった。また、ストライプパ
ターンの多結晶Si膜32をもつ基板では、凹凸の形状
はストライプごとにほぼ同じであり、いずれもストライ
プの中央部で高くなっていたが、その差は約12%と大
きく、パターニングなしの多結晶Si膜22を用いた基
板、あるいはピットパターンをもつ多結晶膜2を用いた
基板での再結晶化膜よりも、凹凸が大きいことがわかっ
た。In Table 1, regarding the surface shape, after removing the surface protective film (SiO 2 film) 3 with a hydrofluoric acid-based etching solution, the surface of the recrystallized film was measured using a stylus type surface shape measuring device. The unevenness is measured, and the ratio of the difference between the maximum value and the minimum value to the film thickness of the polycrystalline film Si before recrystallization is shown. As a result, polycrystalline Si without patterning
In the substrate using the film 22, irregularities of up to 8% were irregularly formed over the entire recrystallized film, whereas in the substrate using the polycrystalline Si film 2 having the pit pattern of Example 1, The maximum unevenness was as small as 3%. Further, in the substrate having the stripe-patterned polycrystalline Si film 32, the shape of the unevenness was almost the same for each stripe, and the height was higher in the central portion of each stripe, but the difference was as large as about 12%. It was found that the unevenness was larger than that of the recrystallized film on the substrate using the uncoated polycrystalline Si film 22 or the substrate using the polycrystalline film 2 having the pit pattern.
【0025】また、ストライプパターンの多結晶Si膜
32を用いた基板の場合、上記12%の凹凸は、100
μm幅1本のストライプにおける値であるのに対し、パ
ターニングなしでの8%の凹凸は、溶融幅10mmにお
ける値であり、従って、このことから、凹凸の勾配もス
トライプパターンの多結晶Si膜32を用いた基板の方
が大きいことがわかった。Further, in the case of a substrate using the polycrystalline Si film 32 having a stripe pattern, the 12% unevenness is 100%.
While the value is for a stripe having a width of μm, the unevenness of 8% without patterning is the value for a melting width of 10 mm. Therefore, from this, the gradient of the unevenness is also the stripe pattern of the polycrystalline Si film 32. It was found that the substrate using was larger.
【0026】膜厚にむらがあるときには、デバイスを形
成する場所によって、その電気特性にばらつきが生じて
しまう。そこで、ラッピングあるいはエッチバック等の
表面平坦化プロセスを行うことが必要となってくる。こ
のような表面平坦化プロセスを行う場合、平坦度が悪い
ものほど、その時間や回数が増え、さらに、Si膜も設
定値からのずれが大きくなってくることから、再結晶化
後の膜の表面凹凸は、極力小さい方が望ましく、この点
で、実施例1のピットパターンをもつ多結晶Si膜2を
用いた基板が最も良いことがわかった。When the film thickness is uneven, the electrical characteristics of the device vary depending on the place where the device is formed. Therefore, it becomes necessary to perform a surface flattening process such as lapping or etch back. When such a surface flattening process is performed, the poorer the flatness, the more the time and the number of times increase, and the Si film also deviates from the set value. It is desirable that the surface irregularities be as small as possible. From this point, it was found that the substrate using the polycrystalline Si film 2 having the pit pattern of Example 1 is the best.
【0027】また、図9(a),(b)はそれぞれ、パ
ターニングしていない図6(a)の多結晶Si薄膜22
を用いた基板,実施例1のピットパターンが形成された
多結晶Si薄膜2を用いた基板のそれぞれ中央部の領域
(幅wが約10mm,長さlが100mmの領域)Aに
再結晶化Si薄膜22’,2’が形成されている状態を
模式的に示す図である。図9(a),(b)からわかる
ように、Si薄膜がパターニングされていない場合,ピ
ットパターンが形成されている場合のいずれも、ビード
アップ53,13が発生しているが、その様子は両者で
異なっている。9 (a) and 9 (b) are the unpatterned polycrystalline Si thin film 22 of FIG. 6 (a), respectively.
Recrystallized into a central region (region having a width w of about 10 mm and a length l of 100 mm) A of the substrate using the substrate and the substrate using the polycrystalline Si thin film 2 in which the pit pattern of Example 1 was formed. It is a figure which shows typically the state in which Si thin film 22 ', 2'is formed. As can be seen from FIGS. 9 (a) and 9 (b), the bead-ups 53 and 13 occur when the Si thin film is not patterned or when the pit pattern is formed. Both are different.
【0028】すなわち、Si薄膜がパターニングされて
いない基板(図9(a))では、再結晶化領域A中で3
箇所にビードアップ53が発生しており、それぞれのビ
ードアップ53は、発生場所において、溶融領域Aのほ
ぼ全体の幅wにわたってSiがはじけて、抜けてしまっ
ている。これに対し、Si薄膜にピットを形成した基板
(図9(b))では、同領域A中でビードアップ13の
発生箇所は2箇所であり、いずれのビードアップ13
も、ピットを境界としてそれ以上まで拡大しておらず、
溶融領域全体の幅wにわたって、抜けてしまうことはな
い。このように、ピットを形成した基板の方がビードア
ップの発生数が少なく、かつ、その大きさが小さい。That is, in the substrate in which the Si thin film is not patterned (FIG. 9A), 3 in the recrystallization region A is used.
The bead-ups 53 are generated at the locations, and in each of the bead-ups 53, Si is popped off over the substantially entire width w of the melted region A at the location where the bead-ups 53 occur. On the other hand, in the substrate in which the pits are formed on the Si thin film (FIG. 9B), there are two bead-ups 13 in the same area A.
However, it has not expanded further beyond the pit,
It does not fall out over the width w of the entire melting region. As described above, the number of bead-up occurrences is smaller and the size thereof is smaller in the substrate in which the pits are formed.
【0029】ビードアップの発生は、熱源の変動や、膜
中のダスト等の異物による融液の急激な変動に起因する
ことが大きく、ピットのところで表面保護膜3が基板に
固定されることによる強度向上は、これを抑えるのに有
効であることがわかった。さらにピットの存在は、ビー
ドアップが発生しても、その拡大を防止する効果もある
ことをこれらの結果は示している。なお、Si薄膜をス
トライプ状にパターニングした図6(b)のSi薄膜で
は、ビードアップの発生は全くなかった。The occurrence of bead-up is largely due to the fluctuation of the heat source and the rapid fluctuation of the melt due to foreign matter such as dust in the film, and the surface protective film 3 is fixed to the substrate at the pit. It has been found that increasing the strength is effective in suppressing this. Furthermore, these results show that the presence of pits also has the effect of preventing the bead-up from expanding even if it occurs. No bead up occurred in the Si thin film of FIG. 6 (b) in which the Si thin film was patterned in a stripe shape.
【0030】また、結晶欠陥の形態を顕微鏡観察により
比較したところ、実施例1のピットパターンが形成され
た多結晶Si膜2を用いた基板,図6(a),(b)の
多結晶Si膜22,32を用いた基板のいずれの基板に
も、図10に示すようなサブグレインバンダリー901
が、平均間隔約10μmで再結晶化Si膜全域で見られ
た他、多結晶Siとの境界付近には、グレインバンダリ
ーも見られた。Further, when the morphology of crystal defects was compared by microscope observation, it was found that the substrate using the polycrystalline Si film 2 having the pit pattern of Example 1 and the polycrystalline Si of FIGS. 6 (a) and 6 (b). Any of the substrates using the films 22 and 32 has a sub-grain bandary 901 as shown in FIG.
However, in addition to being observed throughout the recrystallized Si film with an average interval of about 10 μm, grain boundary was also observed near the boundary with the polycrystalline Si film.
【0031】また、実施例1のピットパターンが形成さ
れたSi薄膜2を用いた基板では、Si薄膜中に正方形
のピット4aの角から数μmの長さでクラック903の
発生が見られた。これは、SiとSiO2の熱膨張係数
差からくるSi薄膜の内部応力が、ピットの角に集中し
たためと考えられるが、局所的であり、長さも短いもの
であることから、その部分を避けて再結晶化膜を利用す
れば特に問題はない。In the substrate using the Si thin film 2 having the pit pattern of Example 1, cracks 903 were observed in the Si thin film at a length of several μm from the corner of the square pit 4a. It is considered that this is because the internal stress of the Si thin film due to the difference in thermal expansion coefficient between Si and SiO 2 was concentrated at the corner of the pit, but it is local and the length is short, so avoid that part. If a recrystallized film is used, there is no particular problem.
【0032】これに対し、図6(b)のようにストライ
プ状にパターニングされた多結晶Si膜32を用いた基
板では、図11に示すようにストライプパターン30に
ほぼ平行に直線状の欠陥905が多数形成されており、
透過型電子顕微鏡によって観察したところ、この欠陥9
05は双晶であることがわかった。双晶の形成は、Si
薄膜をストライプ状にパターニングすると、パターン側
面のSiO2とSiの境界において、固化時の9%とい
う大きな体積膨張に伴う圧縮応力が、パターン側面に沿
って連続的に一定方向から加わることによると考えられ
る。双晶が形成された部分は、サブグレインバンダリー
が形成された部分とは膜の電気特性が異なり、デバイス
特性のばらつきの原因となるため、その発生を極力抑え
る必要がある。図6(a)のパターニングをしていない
多結晶Si膜22を用いた基板と実施例1のピットパタ
ーンを形成した多結晶Si膜2を用いた基板では、この
ように連続的にある一定方向から応力が加わることがな
いため、双晶の発生は見られなかった。On the other hand, in the substrate using the polycrystalline Si film 32 patterned in the stripe shape as shown in FIG. 6B, the linear defect 905 is almost parallel to the stripe pattern 30 as shown in FIG. Are formed,
This defect 9 was observed by a transmission electron microscope.
It was found that 05 was twinned. Twin formation is Si
It is considered that when the thin film is patterned in a stripe shape, a compressive stress due to a large volume expansion of 9% at the time of solidification is continuously applied from a fixed direction along the pattern side surface at the boundary between SiO 2 and Si on the pattern side surface. To be The portion where the twin crystal is formed has a different electric property of the film from the portion where the sub-grain boundary is formed, which causes variations in device characteristics. Therefore, it is necessary to suppress the occurrence thereof as much as possible. In the substrate using the unpatterned polycrystalline Si film 22 of FIG. 6A and the substrate using the pit-patterned polycrystalline Si film 2 of the first embodiment, a continuous pattern is formed in a certain direction. Since no stress was applied from the surface, twinning was not observed.
【0033】以上、再結晶化膜の膜質(表面凹凸,ビー
ドアップ,欠陥)を、Si薄膜をパターニングしない基
板、ストライプ状にパターニングした基板、ピットを形
成した多結晶Si膜を用いた基板について総合的に評価
すると、表1からわかるように、ピットを形成した実施
例1の基板は、表面凹凸が最も小さく、応力に起因した
双晶の形成も見られず、ビードアップについても、2箇
所に微小なものがあるだけで、これについては、ピット
の大きさ、間隔を最適化することによりなくすこともで
きると考えられることから、デバイス形成のための半導
体基板としては、最も有利なものである。As described above, the quality of the recrystallized film (surface irregularities, bead-ups, defects) is summarized for the substrate not patterned with the Si thin film, the substrate patterned with stripes, and the substrate using the polycrystalline Si film with pits formed. As can be seen from Table 1, the substrate of Example 1 in which the pits were formed had the smallest surface irregularities, no twin formation due to stress was observed, and the bead-up also occurred at two locations. It is the most advantageous semiconductor substrate for device formation because it is possible to eliminate it by only optimizing the size and spacing of pits, since there are only minute ones. .
【0034】(実施例2)実施例2では、実施例1と同
様にして、厚さ500μmの石英基板上にLP−PVD
法により多結晶Si薄膜2を3300Åの厚さで形成し
た後、通常のフォトリソグラフィ工程により、この多結
晶Si薄膜2に一辺が10μmの正方形のピット4a
を、その間隔が最大でも溶融領域内で600μmとなる
ようにランダムに形成した。そして、その上に表面保護
膜3として,SiO2 膜をLP−CVD法により1.3
μmの厚さに形成した。この半導体材料基板を、実施例
1と同様にして、レーザービームにより溶融再結晶化し
たところ、表面凹凸については、約8%となり、ピット
パターンなしの場合と比較して大きな改善が見られなか
った。そこで、ピットパターンの間隔について、100
μmから1mmまで、100μmずつ変化させたものに
つき、同様の再結晶化を行なったところ、次表(表2)
に示すように、間隔が約500μm程度以下のときに、
表面の凹凸が大きく改善されることがわかった。Example 2 In Example 2, as in Example 1, LP-PVD was formed on a quartz substrate having a thickness of 500 μm.
After forming the polycrystalline Si thin film 2 with a thickness of 3300Å by the method, a square pit 4a having a side of 10 μm is formed on the polycrystalline Si thin film 2 by a normal photolithography process.
Were randomly formed such that the distance between them was 600 μm in the melting region even at the maximum. Then, a SiO 2 film as a surface protection film 3 is formed thereon by LP-CVD to 1.3
It was formed to a thickness of μm. When this semiconductor material substrate was melted and recrystallized by a laser beam in the same manner as in Example 1, the surface unevenness was about 8%, and no significant improvement was observed as compared with the case without a pit pattern. . Therefore, the pit pattern interval is 100
The same recrystallization was carried out for the materials which were changed by 100 μm from μm to 1 mm. The following table (Table 2)
As shown in, when the distance is about 500 μm or less,
It was found that the surface irregularities were greatly improved.
【0035】[0035]
【表2】 [Table 2]
【0036】(実施例3)実施例3においても、実施例
1,実施例2と同様に、図1に示す層構成の基板を用い
たが、実施例3では、正方形ではなく円形のピットパタ
ーンを多結晶Si膜2に形成した。すなわち、先ず、実
施例1,実施例2と同様に、基板1として、厚さ500
μmの石英基板を用い、この基板1上にLP−CVD法
により、多結晶Si薄膜を3300Åの厚さに形成し
た。しかる後、通常のフォトリソグラフィ工程により、
図12に示すように、多結晶Si薄膜2に直径10μm
の円形のピット4bを、間隔が最大でも溶融領域内で約
500μm程度以下となるようにランダムに形成した。(Embodiment 3) In Embodiment 3, as in Embodiments 1 and 2, the substrate having the layer structure shown in FIG. 1 was used. However, in Embodiment 3, a circular pit pattern is used instead of a square. Was formed on the polycrystalline Si film 2. That is, first, as in the first and second embodiments, the substrate 1 having a thickness of 500 is formed.
A polycrystalline Si thin film having a thickness of 3300 Å was formed on the substrate 1 by a LP-CVD method using a quartz substrate of μm. After that, by a normal photolithography process,
As shown in FIG. 12, the polycrystalline Si thin film 2 has a diameter of 10 μm.
The circular pits 4b were randomly formed so that the distance between them was about 500 μm or less in the melting region even at the maximum distance.
【0037】次にこのようにしてピット4bが形成され
た多結晶Si薄膜2上に、表面保護膜3としてSiO2
膜をLP−CVD法により1.3μmの厚さに形成し
た。次いで、このようにして形成した半導体材料基板上
に、実施例1,実施例2と同様な方法でレーザービーム
を照射し、基板を相対的に走査することにより多結晶S
i薄膜2を溶融,再結晶化した。Next, on the polycrystalline Si thin film 2 having the pits 4b formed in this manner, SiO 2 as a surface protective film 3 is formed.
The film was formed to a thickness of 1.3 μm by the LP-CVD method. Next, the semiconductor material substrate thus formed is irradiated with a laser beam in the same manner as in Examples 1 and 2, and the substrate is relatively scanned to cause polycrystalline S
The i thin film 2 was melted and recrystallized.
【0038】このようにして得られたSi溶融再結晶化
膜について、膜の表面凹凸,ビードアップの有無,欠陥
の形態を評価したところ、Si薄膜に正方形のピットを
形成した実施例1,実施例2における基板とほぼ同等の
評価結果が得られ、さらに、ピットが正方形の場合にピ
ットの角で見られた微小なクラックの発生もなかった。With respect to the Si melt recrystallized film thus obtained, the surface irregularities of the film, the presence or absence of bead-up, and the morphology of defects were evaluated. The evaluation results almost equal to those of the substrate in Example 2 were obtained, and in the case where the pits were square, no minute cracks were found at the corners of the pits.
【0039】(実施例4)実施例3と同様に、石英基板
1上に多結晶Si薄膜2を形成し、この多結晶Si薄膜
2に円形のピット4bを形成した後、表面にSiO2 膜
3を形成したが、実施例4では、円形のピット4bを直
径100μmのものとし、ピット4b間の間隔を溶融領
域内で500μm〜300μm程度のものとした。この
基板における多結晶Si薄膜を実施例1と同様にして溶
融,再結晶化した。(Embodiment 4) Similar to Embodiment 3, a polycrystalline Si thin film 2 is formed on a quartz substrate 1, circular pits 4b are formed in this polycrystalline Si thin film 2, and then a SiO 2 film is formed on the surface. In Example 4, the circular pits 4b had a diameter of 100 μm, and the intervals between the pits 4b were about 500 μm to 300 μm in the melting region. The polycrystalline Si thin film on this substrate was melted and recrystallized in the same manner as in Example 1.
【0040】ここで得られた再結晶化膜の膜質につい
て、実施例1と同様の観点で評価したところ、各ピット
周辺に表面形状の乱れが見られ、表面凹凸は、10%と
大きくなった。ピットの大きさとピットの間隔について
調べたところ、次表(表3)に示すように、ピットの大
きさ(直径)が最小隣接ピット間距離(すなわち、最も
近接した穴状の微細欠損部分間距離;表3の例では30
0μmとなっている)の10分の1程度以下であれば、
ピット周辺の表面形状の乱れがほとんどないことがわか
った。The film quality of the recrystallized film obtained here was evaluated from the same viewpoint as in Example 1. As a result, the surface shape was disturbed around each pit, and the surface unevenness was as large as 10%. . When the pit size and the pit interval were examined, as shown in the following table (Table 3), the pit size (diameter) was the minimum distance between adjacent pits (that is, the distance between the closest hole-like fine defect portions). 30 in the example of Table 3
Is about 1/10 or less of (0 μm)
It was found that there was almost no disturbance in the surface shape around the pit.
【0041】[0041]
【表3】 [Table 3]
【0042】ピット周辺の表面形状の乱れは、基板走査
に伴う溶融領域の移動の際、ピットがSi融液の障害物
となるため、ピット径が大きいと、ピットのところで、
融液が乱れるために生ずるものと考えられ、ピットの大
きさを、最小隣接ピット間距離の10分の1程度を直径
とする円よりも小さいものにすることで、ピットが融液
の移動の際に大きな障害とならず、従って、融液が乱れ
ずに、得られる単結晶半導体薄膜の表面凹凸のピット周
辺での乱れを小さくすることができる。The irregularities in the surface shape around the pits cause the pits to become obstacles to the Si melt during the movement of the melted area due to the substrate scanning. Therefore, if the pit diameter is large,
It is considered that this occurs because the melt is disturbed, and by making the size of the pit smaller than a circle whose diameter is about one-tenth of the distance between the minimum adjacent pits, the pit does not move In this case, it does not become a major obstacle, and therefore, the disorder of the surface unevenness of the obtained single crystal semiconductor thin film around the pit can be reduced without disturbing the melt.
【0043】(実施例5)実施例5では、実施例1と同
様に、石英基板1上に多結晶Si薄膜2を形成し、正方
形ピット4aを形成した後、表面にSiO2 膜3を形成
したが、実施例5においては、ピット4aの並び方をラ
ンダムではなく、図13に示すように、一辺500μm
の格子位置に配列した。(Embodiment 5) In Embodiment 5, as in Embodiment 1, a polycrystalline Si thin film 2 is formed on a quartz substrate 1, square pits 4a are formed, and then a SiO 2 film 3 is formed on the surface. However, in Example 5, the arrangement of the pits 4a was not random, but was 500 μm on each side as shown in FIG.
Are arranged at the lattice positions of.
【0044】このようにして形成した半導体材料基板の
多結晶Si薄膜を実施例1と同様にして溶融、再結晶化
して得られたSi溶融再結晶化膜は、ピットの位置が一
定方向に規則的に定まっているので、Si溶融再結晶化
膜領域も一定方向に連続しており、デバイス設計上有利
である。In the Si melt recrystallized film obtained by melting and recrystallizing the polycrystalline Si thin film of the semiconductor material substrate thus formed in the same manner as in Example 1, the pit positions are regular in a certain direction. Since the Si melt recrystallized film region is continuous in a certain direction, it is advantageous in device design.
【0045】(実施例6)実施例1と同様な半導体薄膜
材料基板をレーザー導入窓のついた真空チャンバー中に
設置し、2×10-4Torrの減圧雰囲気中で同様の溶
融再結晶化を行ったところ、得られたSi再結晶化膜の
表面の凹凸は2%となり、大気雰囲気中で行ったものよ
りも小さかった。これは、大気中で溶融再結晶化を行う
場合、基板表面は、対流による激しい熱の損失をうけ、
この不安定な熱循環は、Si融液の大きな変動をひきお
こすためSiの表面形状が乱れるが、対流による熱損失
の影響がないような減圧雰囲気にすることにより、安定
した溶融状態が実現されるためと考えられる。Example 6 The same semiconductor thin film material substrate as in Example 1 was placed in a vacuum chamber having a laser introduction window, and the same melt recrystallization was performed in a reduced pressure atmosphere of 2 × 10 −4 Torr. As a result, the surface roughness of the obtained Si recrystallized film was 2%, which was smaller than that in the air atmosphere. This is because the substrate surface suffers severe heat loss due to convection when melt recrystallization is performed in the atmosphere.
This unstable heat circulation causes a large fluctuation of the Si melt, so the surface shape of Si is disturbed, but a stable molten state is realized by creating a depressurized atmosphere that is not affected by heat loss due to convection. It is thought to be because.
【0046】[0046]
【発明の効果】以上に説明したように、請求項1記載の
発明によれば、絶縁性基板上に半導体薄膜と表面保護膜
とが順次に形成されている半導体材料基板を加熱走査
し、半導体薄膜を溶融,再結晶化する際に、半導体薄膜
には、複数の穴状の微細欠損部分が、加熱時の溶融領域
内において所定の間隔で設けられており、溶融領域内に
表面保護膜を基板に固定している部分が一箇所以上存在
し、表面保護膜を構造的に補強しているので、融液の変
動を効果的に抑制することができ、得られる単結晶半導
体薄膜の表面の凹凸を小さくし、ビードアップを防止す
ることができる。さらに、微細欠損部分が散在するよう
なパターンでは、半導体薄膜をストライプ状あるいは連
結したアイランド状等の連続したパターンの場合のよう
に固化時の堆積変化に起因するパターン側面に沿った連
続的な一定方向の応力が加わることがないため、双晶等
の欠陥の発生を抑えることができる。As described above, according to the first aspect of the present invention, the semiconductor material substrate in which the semiconductor thin film and the surface protective film are sequentially formed on the insulating substrate is heated and scanned to obtain the semiconductor. When the thin film is melted and recrystallized, the semiconductor thin film is provided with a plurality of hole-shaped fine defect portions at predetermined intervals in the melting region at the time of heating, and the surface protective film is formed in the melting region. Since there is one or more portions fixed to the substrate and structurally reinforces the surface protective film, it is possible to effectively suppress the fluctuation of the melt, and to obtain the surface of the obtained single crystal semiconductor thin film. It is possible to reduce unevenness and prevent bead-up. Further, in a pattern in which fine defect portions are scattered, a continuous constant pattern along the side surface of the pattern due to a change in deposition during solidification, as in the case of a continuous pattern in which a semiconductor thin film is stripe-shaped or island-shaped, is connected. Since no directional stress is applied, the occurrence of defects such as twins can be suppressed.
【0047】また、請求項2記載の発明によれば、微細
欠損部分の形状が円形となっているので、微細欠損部分
に応力が集中する角が存在せず、従って、クラックの発
生を防止できる。Further, according to the second aspect of the present invention, since the shape of the fine defect portion is circular, there is no corner where stress concentrates in the fine defect portion, and therefore the occurrence of cracks can be prevented. .
【0048】また、請求項3記載の発明によれば、微細
欠損部分の大きさが、最も近接した穴状の微細欠損部分
間距離の10分の1程度を直径とする円よりも小さいも
のとなっているので、微細欠損部分が融液の移動の際に
大きな障害とならず、従って、融液が乱れずに、得られ
る単結晶半導体薄膜の表面凹凸の微細欠損部分周辺での
乱れを小さくすることができる。According to the third aspect of the present invention, the size of the fine defect portion is smaller than a circle having a diameter of about 1/10 of the distance between the closest hole-like fine defect portions. As a result, the fine defect portion does not become a major obstacle during the movement of the melt, and therefore the melt is not disturbed, and the disturbance of the surface irregularities of the obtained single crystal semiconductor thin film around the fine defect portion is small. can do.
【0049】また、請求項4記載の発明では、複数の穴
状の微細欠損部分が格子位置に配列されているので、単
結晶半導体薄膜を一定方向に連続して得ることができ、
そこにデバイスを形成しようとした場合、設計上有利で
ある。In the invention according to claim 4, since the plurality of hole-shaped fine defect portions are arranged at the lattice positions, the single crystal semiconductor thin film can be continuously obtained in a certain direction.
If a device is to be formed there, it is advantageous in design.
【0050】また、請求項5記載の発明では、溶融,再
結晶化工程を減圧雰囲気中で行なうようになっているの
で、基板表面付近で対流による熱の乱れがなく、これに
より、融液が安定化し、得られる単結晶半導体薄膜の表
面の凹凸をより小さくすることができる。Further, in the invention described in claim 5, since the melting and recrystallization steps are carried out in a reduced pressure atmosphere, there is no heat disturbance due to convection near the surface of the substrate, and thus the melt is formed. It is possible to stabilize and further reduce the unevenness of the surface of the obtained single crystal semiconductor thin film.
【図1】本発明の半導体材料基板の縦断面図である。FIG. 1 is a vertical sectional view of a semiconductor material substrate of the present invention.
【図2】図1の半導体材料基板のB−B線における横断
面図である。2 is a cross-sectional view of the semiconductor material substrate of FIG. 1 taken along the line BB.
【図3】図1の半導体材料基板の部分拡大図である。3 is a partially enlarged view of the semiconductor material substrate of FIG.
【図4】実施例1で用いた半導体材料基板の縦断面図で
ある。4 is a vertical sectional view of a semiconductor material substrate used in Example 1. FIG.
【図5】図4の半導体材料基板のC−C線における横断
面図である。5 is a cross-sectional view taken along line CC of the semiconductor material substrate of FIG.
【図6】本発明の半導体材料基板と比較するために用い
る半導体材料基板の半導体層の構成図である。FIG. 6 is a configuration diagram of a semiconductor layer of a semiconductor material substrate used for comparison with the semiconductor material substrate of the present invention.
【図7】レーザー加熱装置の構成例を示す図である。FIG. 7 is a diagram showing a configuration example of a laser heating device.
【図8】本発明による溶融,再結晶化の様子を説明する
ための図である。FIG. 8 is a diagram for explaining the state of melting and recrystallization according to the present invention.
【図9】ビードアップの発生結果を示す図である。FIG. 9 is a diagram showing a result of occurrence of bead up.
【図10】サブグレインバンダリーの発生結果を示す図
である。FIG. 10 is a diagram showing a result of occurrence of subgrain boundary.
【図11】ストライプ状にパターニングされた多結晶S
i膜において発生した直線状の欠陥を示す図である。FIG. 11: Polycrystalline S patterned in stripes
It is a figure which shows the linear defect which arose in the i film.
【図12】実施例3で用いた半導体材料基板の半導体層
の横断面図である。FIG. 12 is a cross-sectional view of a semiconductor layer of a semiconductor material substrate used in Example 3.
【図13】ピットを格子位置に配列した状態を示す図で
ある。FIG. 13 is a diagram showing a state in which pits are arranged at lattice positions.
【図14】従来の半導体材料基板の一構成例を示す図で
ある。FIG. 14 is a diagram showing a configuration example of a conventional semiconductor material substrate.
【図15】図14の半導体材料基板の半導体層を溶融,
再結晶化した状態を示す図である。FIG. 15 is a view of melting the semiconductor layer of the semiconductor material substrate of FIG.
It is a figure which shows the state recrystallized.
【図16】再結晶化されるべき従来の半導体材料基板の
他の構成例を示す図である。FIG. 16 is a diagram showing another configuration example of the conventional semiconductor material substrate to be recrystallized.
1 絶縁性基板 2 半導体層(半導体薄膜) 3 表面保護膜 4 微細欠損部分(ピット) 6 溶融領域 1 Insulating Substrate 2 Semiconductor Layer (Semiconductor Thin Film) 3 Surface Protection Film 4 Fine Defects (Pits) 6 Melting Area
Claims (5)
とが順次に形成されている半導体材料基板を加熱走査
し、前記半導体薄膜を溶融再結晶化する再結晶化方法に
おいて、前記半導体薄膜には、複数の穴状の微細欠損部
分が、加熱走査時に溶融領域内において所定の間隔で設
けられていることを特徴とする再結晶化方法。1. A recrystallization method of melting and recrystallizing the semiconductor thin film by heating and scanning a semiconductor material substrate in which a semiconductor thin film and a surface protective film are sequentially formed on an insulating substrate. In the recrystallization method, a plurality of hole-shaped fine defect portions are provided at a predetermined interval in the melting region during heating scanning.
前記微細欠損部分の各々は、円形形状となっていること
を特徴とする再結晶化方法。2. The recrystallization method according to claim 1, wherein
The recrystallization method is characterized in that each of the fine defect portions has a circular shape.
前記微細欠損部分の各々の大きさは、最も近接した穴状
の微細欠損部分間距離の10分の1程度を直径とする円
よりも小さいものとなっていることを特徴とする再結晶
化方法。3. The recrystallization method according to claim 1, wherein
The size of each of the fine defect portions is smaller than a circle having a diameter of about 1/10 of the distance between the closest hole-like fine defect portions. .
前記微細欠損部分の各々は、格子位置に配列されている
ことを特徴とする再結晶化方法。4. The recrystallization method according to claim 1, wherein
The recrystallization method, wherein each of the fine defect portions is arranged at a lattice position.
前記溶融,再結晶化は、減圧雰囲気中でなされるように
なっていることを特徴とする再結晶化方法。5. The recrystallization method according to claim 1, wherein
A recrystallization method characterized in that the melting and recrystallization are performed in a reduced pressure atmosphere.
Priority Applications (1)
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JP4202194A JPH07230952A (en) | 1994-02-16 | 1994-02-16 | Recrystallizing method |
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Application Number | Priority Date | Filing Date | Title |
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JP4202194A JPH07230952A (en) | 1994-02-16 | 1994-02-16 | Recrystallizing method |
Publications (1)
Publication Number | Publication Date |
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JPH07230952A true JPH07230952A (en) | 1995-08-29 |
Family
ID=12624521
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