JPH0722887A - Power controller - Google Patents

Abstract

PURPOSE:To perform low voltage driving by performing power control by selecting the voltage of a power source connected to the source/drain area of each field effect transistor(FET) and the voltage of first and second control power sources, and switching an attenuator circuit. CONSTITUTION:The source or drain area of the FET 21 is connected to the input terminals T1 and T2 of the attenuator circuit 1 in parallel, and the source or drain area of the FET 22 to the ground side of the circuit 1, and furthermore, a capacitor 24 to the circuit in series. In addition to that, the power source 10 is connected between the FET 22 on the ground side and the capacitor 24, and between the input/output terminals T1, T2. Also, the first control power source 11 is connected to the gate of the FET 21 on the input/output side, and the second control power source 12 to the gate of the FET 22. The first control power source 11 with voltage lower than that of the power source 10 is connected to the second power source 12 with voltage higher than that, and the FET 22 is turned on, and the FET 21 is turned off, then, the attenuator circuit 1 is turned on. Also, the circuit 1 can be turned off by applying a backward voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power control circuit, and more particularly to a power control device having an attenuator circuit, for example.

[0002]

2. Description of the Related Art At present, in the field of land mobile communications such as car telephones and mobile telephones, the number of subscribers has increased and the number of radio waves in the current frequency band has become insufficient. Therefore, the launch of several new services is being decided one after another. All of these services are digital communications, and the quasi-microwave band (0.8 GHz to 2 GHz) is used.

Mobile communication terminals are required to be miniaturized because importance is attached to portability, and it is an important issue to make ICs for electronic parts used here. However, the development of microwave ICs (MMIC: monolithic microwave IC) that can be used in this frequency band has been delayed,
Promotion of development is desired.

The terminals used in these systems are
Since it is assumed to be driven by a battery, it is a condition that the component needs to operate with battery output. However, since the output voltage of a battery is generally low, there is a demand for the development of a power control device that exhibits good attenuation characteristics while being driven at a low voltage.

As a conventional technique, for example, "Finbarr
J. McGrath, Russ G. Pratt, “DC-12GHz 4-bit GaAs Monoli
thic Digital Attenuator "APPLIED MICROWAVE Winter
There is a power control circuit as shown in 91/92 pp60-67 ". The conventional semiconductor attenuator circuit is GaA.
An s-MESFET (metal-semiconductor field effect transistor) is used, and the control voltage applied to its gate is 0V.
And about -5V. This is a GaAs-MESFET
This is because the pinch-off voltage V _p is set to −3 V or less in order to reduce the resistance value of the on-state.

In such a conventional semiconductor attenuator circuit, the pinch-off voltage V _p is set to a deep negative voltage in order to realize a small resistance value of the on-state of the FET in order to obtain a good attenuation characteristic. That is, F
The resistance value of the on-state of ET is controlled by the pinch-off voltage V _p .

Therefore, the gate control voltage necessary to turn off the FET becomes a negative voltage deeper than V _p .
Here, in order to realize a smaller insertion loss, V _p must be deeply set, which means that the performance is secured when the power supply voltage is assumed to be 3 V as in the case of use in a mobile phone terminal, for example. There is a danger that doing so will be a fatal drawback.

[0008]

SUMMARY OF THE INVENTION The present invention provides a power control device suitable for use in a mobile communication terminal such as a mobile phone as described above.

[0009]

According to the present invention, as shown in the basic circuit configuration of FIG. 1, field effect transistors (hereinafter referred to as FETs) are connected in parallel to signal input / output terminals T ₁ and T ₂ of an attenuator circuit 1. ) 21 is connected to the source region or the drain region and the FET is connected to the ground side of the attenuator circuit 1.
A source or drain region 22 and a capacitor 24 are connected in series with the source or drain region 22.

Further, the power source 10 is connected between the field effect transistor 22 on the ground side and the capacitor 24, and the power source 10 is connected to the input / output terminals T ₁ and T ₂ of the attenuator circuit. Further, the first control power supply 11 is connected to the F on the input / output terminal side.
FET2 on the ground side while connected to the gate of ET21
The second control power supply 12 is connected to the second gate.

Further, the present invention provides each FE in the above configuration.
The built-in voltage V _b and the pinch-off voltage V _p of T21 and 22, configured as a _{1V ≦ V b -1V ≦ V p} <0V.

Further, according to the present invention, at least one of the FETs 21 and 22 in each of the above-mentioned configurations is configured as a junction type FET (JFET).

[0013]

With the circuit configuration described above, each FET
The voltage of the power supply 10 connected to the source / drain region of
By appropriately selecting the power sources of the first and second control power sources 11 and 12, the attenuator circuit 1 can be switched, that is, turned on / off, to perform power control.

That is, for example, by connecting the first control power supply 11 having a voltage lower than the voltage of the power supply 10 and the second control power supply 12 having a high voltage to the FETs 21 and 22, for example, on the ground side. The FET 22 is turned on and the FET 21 on the input / output terminal side is turned off, whereby the attenuator circuit 1 can be turned on. The attenuator circuit 1 can be turned off by turning off the ground side FET 22 and turning on the input / output terminal side FET 21 by applying reverse voltages.

At this time, the FET 2 is connected via the capacitor 24.
Since the configuration is such that 2 is grounded, the applied voltage is applied to each power source 1
This second FET 22 is controlled by controlling 0 to 12.
The potential difference between the source or drain electrode and the gate can be set to a desired value.

Further, as described above, by setting the built-in voltage V _b of each FET 21 and 22 to 1 V or more and the pinch-off voltage V _p to -1 V to less than 0 V, low voltage driving becomes possible.

A junction type FET (JFE) is used as the FET.
T) is used to set a pinch-off voltage V _p of an appropriate value with respect to a desired power supply voltage, and the FET is turned on by the difference between the control voltage applied to the gate and the voltage applied to the drain and the source. It is possible to control the impedance value in the off state and obtain good attenuator characteristics.

Therefore, even when it is used in a mobile communication terminal such as a mobile phone terminal, that is, even when the power supply voltage is assumed to be 3 V, it is extremely easy to ensure its performance by selecting the value of the applied voltage. .

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the basic structure of the present invention. 1 is an attenuator circuit, both input / output terminals T ₁ ,
The FET 21 is connected in parallel to T ₂ , that is, the source region or the drain region is connected thereto. Also, this attenuator circuit 1
The source or drain region of another FET 22 is connected to the ground side of, and the capacitor 24 is connected to the ground side in series with this.

Further, the power supply 10 is connected between the FET on the ground side and the capacitor 24, and is also connected to the input / output terminals T ₁ and T ₂ of the attenuator circuit 1 to connect the first control power supply 11 to the input / output terminal side. The second control power supply 12 is connected to the gate of the FET and is connected to the gate of the ground side FET.

In such a configuration, a more detailed circuit configuration diagram is shown in FIG. 2, particularly when the attenuator circuit 1 described above has a T-type configuration. That is, in order to achieve desired attenuation while matching, for example, a T-type resistor R
₁ , R ₂ and R ₃ are connected. The resistor R _1, to both outer sides of R ₂ for example G that the input and output terminals T ₁ and T ₂
The source terminal and the drain terminal of the FET 21 composed of aAs-JFET are connected in parallel. Further, the power source 10 is connected to the source and drain terminals of the FET 21 via high impedance elements L ₁ and L ₂ , respectively.

_On the ground side of the resistor R ₃ , GaAs-JF is used.
For example, the drain terminal of the FET 22 formed of ET or the like and the source terminal thereof are connected to the capacitor 24 and are grounded.
The power supply 10 is connected between the source terminal of the ET 22 and the capacitor 24 via the high impedance element L ₃ . Furthermore, the first control power supply 11 is connected to the gate terminal of the FET 21 on the input / output terminal side.
And the second control power supply 12 is connected to the gate terminal of the ground side FET 22.

With respect to the operation in such a configuration, a case where the 3V operation is performed will be described as an example. Also, in this case, the pinch-off voltage V _p of the GaAs-JFET is -1 V.
It is set to −1 V, which is equal to or more than 0 V and less than 0 V.

At this time, the voltage of the power source 10 is set to 2V, and the voltage of the first and second control power sources 11 and 12 is set to 0V or 3V. When each FET, that is, GaAs-JFET is turned on, if the control voltage applied to its gate is 3V, the voltage applied to the drain and source is 2V.
Therefore, the gate voltage for the drain and source is +
This is 1V higher, which is close to the built-in voltage (about 1.2V) of GaAs-JFET.
T turns on.

The GaAs--on-stated in this way
An extremely small resistance value between the drain and source of the JFET is realized.

When the GaAs-JFET is turned off, the voltage applied to its gate is set to 0V. Since the voltage applied to the drain and the source is 2V, the gate voltage to the drain and the source is -2V lower.
Since the pinch-off voltage V _p of the GaAs-JFET is -1V, it means that the GaAs-JFET is completely off.

By utilizing the ON / OFF of the FET, the attenuator circuit 1 can be turned on / off by the following operation. First, when the attenuator circuit is turned on, the voltage of the power supply 10 is 2V, the gate of the FET 21 on the input / output terminal side is the first control power supply 11 to 0V, and the gate of the FET 22 on the ground side is the second control power supply 12 to 3V.
Apply V. Since the voltage applied to the source / drain region is 2V, the gate voltage of the FET 22 on the ground side is +
This is 1 V higher, and the device is on. On the other hand, the gate voltage of the FET 21 on the input / output side is lower than that of the drain and source regions by 2V. Since the pinch-off voltage is set to -1V as described above, the FET 21 is turned off.

Since the drain-source resistance of the GaAs-JFET is extremely small, the circuit of FIG. 2 is approximated by turning off the FET 21 on the input / output side and turning on the FET 22 on the ground side in this way. Resistance to R ₁ , R
It can be regarded as a T-type attenuator circuit composed of only ₂ and R _3, and exhibits very good attenuation characteristics.

When the off operation is shown as the attenuator, the connection of the above-mentioned first and second control power supplies is exchanged, or the connection is left as it is, for example, the FET 2 on the input / output side.
3V is applied from the first control power supply 11 to the gate of No. 1 to turn on the FET 21, and the second FET 22 is connected to the ground side FET 22.
The FET 22 is turned off by setting the voltage of the control power source 12 to 0V.

In such a state, the input / output side FET 21
FET22 with extremely low resistance in the ON state and on the ground side
Is completely off, the circuit of FIG. 2 can be regarded as a short between the input and output terminals T ₁ and T ₂ , and the attenuator circuit is turned off. In this case, the off-ground side FET
Since the signal leaking from 22 to the ground is very small, the insertion loss of the entire circuit can be suppressed to be very small.

As described above, according to the present invention, the built-in voltage V _b and the pinch-off voltage V _p of the first and second FETs 21 and 22 in the above-described structure are set as 1 V ≦ V _b −1 V ≦ V _p <0 V. Enable low voltage driving, and by making each FET a JFET, the power supply voltage is 3 when applied to a mobile communication terminal such as a mobile phone.
Even with V, the on / off operation of the attenuator circuit can be easily performed.

As the attenuator circuit, a so-called π type configuration can be adopted as shown in the circuit configuration diagram of FIG. In this case, the FET 21 such as GaAs-JFET is connected in parallel with the resistor R ₁ on the input / output terminal side.
On the other hand, the drain terminals of FETs 22 and 23 such as GaAs-JFET are connected in series to the resistors R ₂ and R ₃ on the ground side, respectively. Then, the source side thereof is grounded via the capacitors 24 and 25, respectively.

The power source 10 is connected to the source and drain terminals of the FET 21 on the input / output side and to the source terminals of the FETs 22 and 23 on the ground side. The first control power source 1
1 is connected to the gate of the FET 21 on the input / output side, and the second control power supply 12 is connected to the gates of the FETs 22 and 23 on the ground side. In FIG. 3, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and duplicate description will be omitted.

With such a configuration, the attenuator circuit 1 can be turned on / off by applying a voltage from each of the power sources 10 to 12 as in the case of using the attenuator circuit 1 having the T-type configuration described above. .

Also in this case, good attenuator characteristics can be obtained by driving at a low voltage of 3 V as in the above example. Therefore, when applied to a mobile communication terminal such as a mobile phone, it becomes extremely easy to ensure its performance.

The present invention is not limited to the above-described embodiment, and the present invention is not limited to the above-mentioned embodiment, and its circuit configuration is such that a high impedance element is connected between the power source 10 and the source / drain terminal in the example of FIG. It goes without saying that various modifications and changes can be made without departing from the scope of the invention.

[0038]

As described above, according to the present invention, it is possible to reliably operate the attenuator circuit and switch it on / off by driving at a low voltage. Therefore, when applied to a mobile communication terminal such as a mobile phone, it becomes extremely easy to ensure its performance.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a basic configuration of the present invention.

FIG. 2 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of another embodiment of the present invention.

[Explanation of symbols]

 1 Attenuator Circuit 10 Power Supply 11 First Control Power Supply 12 Second Control Power Supply 21 Field Effect Transistor (FET) 22 Field Effect Transistor (FET) 23 Field Effect Transistor (FET) 24 Capacitance 25 Capacitance

Claims (3)

[Claims] 1. A source region or a drain region of a field effect transistor is connected to a signal input / output terminal of an attenuator circuit, and a source and a drain region of another field effect transistor are connected in series with a capacitance on the ground side of the attenuator circuit. A power source is connected between the ground side field effect transistor and the capacitor, and the power source is connected to an input / output terminal of the attenuator circuit, and a first control power source is the ground side field effect transistor. And a second control power supply connected to the gate of the field effect transistor on the input / output terminal side. 2. The power according to claim 1, wherein the built-in voltage V _b and the pinch-off voltage V _{p of} each field effect transistor are set to 1 V ≦ V _b −1 V ≦ V _p <0 V. Control device. 3. The power control apparatus according to claim 1, wherein at least one of the field effect transistors is a junction type.