JPH07226686A - Serial input/output circuit and mobile communication equipment - Google Patents

Abstract

PURPOSE:To perform serial transmissions/receptions by a designated number of bits and to improve processing efficiency by using a transmission side circuit and a reception side circuit which have prescribed constitutions for the data of the designated number of bits. CONSTITUTION:The number of bits to be transmitted from a transmission control circuit 3 is set to a register 6 and the number of bits to be received from a reception control circuit 9 is set to a register 12. In a matching detection circuit 7, the output signals of the register 6 and a transmission data count counter 5 are inputted. A signal inhibiting the output of a clock and a signal permitting the output of the clock are transmitted to a clock control circuit 8 when these two signals are matched and when the signals are not matched, respectively. In an initial state, the circuit 7 sets the signal inhibiting the output of the clock and a matching detection circuit 13 sets the signal permitting the output of the clock. The circuit 8 outputs the clock only when the two signals are permitted. When the WR signal that the circuit 3 outputs when the circuit 3 writes parallel data in a parallel/serial conversion circuit 4 is inputted in the circuit 7, the inhibition of the clock is switched to the permission of the clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit for serially inputting / outputting data used in a communication device or the like, and in particular, parallel data is once converted into serial data and sent out to detect an error in serial data. The present invention relates to a circuit for converting serial data, which has been subjected to error correction, scramble, or the like, or has been transmitted as it is, into parallel data.

[0002]

2. Description of the Related Art A serial input / output circuit has a shift register for parallel-serial conversion on the data transmission side,
It is known that a shift register for serial / parallel conversion is used on the receiving side. In this serial input / output circuit, when the clock is input to the shift register, the shift operation is performed and a specific number of data cannot be processed.

To solve this problem, Japanese Patent Laid-Open No. 3-97055 discloses a serial input / output circuit capable of transmitting / receiving a specific byte.

FIG. 6 shows the configuration of the serial input / output circuit described in Japanese Patent Laid-Open No. 3-97055.
In FIG. 6, 21 is a shift register that shifts data in synchronization with the clock signal CK, and 22 is a shift register 2.
In 1, a clock counter (first counter) that counts the clock signal CK to notify that the data has been shifted a specific number of times, and 23 counts a clock count signal that is output when the clock counter 2 counts a specific number of times. A byte counter (second counter) 24 is a clock control circuit for controlling the shift operation by the clock signal CK of the shift register 1 when the count value of the byte counter 3 reaches a specific value.
An end signal control circuit 25 controls a transmission / reception end signal indicating that the transmission / reception of serial input / output has ended. Figure 6
In the clock counter 22, the shift register 21
Is set to the same value as the number of stages, and an overflow signal is output each time the clock signal CK is counted by the set number. The byte counter 23 counts this overflow signal and outputs a control signal to the clock control circuit 24 and the end signal control circuit 25 so that serial transmission / reception can be performed while the count value is a predetermined value. Here, the byte counter is, for example, a down counter, and its content is 0.
The control signal is output only during the period. Here, when the number of bytes of the clock signal CK which is not transmitted is written in the byte counter 23, the clock counter 22
The byte counter 23 counts down in response to the overflow signal from No., serial transmission / reception is not performed until the content becomes 0, and transmission / reception is performed only when it becomes 0.
After that, the byte counter 23 further counts down, so that transmission / reception is not performed with the clock signal CK.

[0005]

However, in the serial input / output circuit according to the conventional technique, the output of the byte counter is used for the control signal as described above, so that it is possible to perform transmission / reception in byte units. There was a problem that serial transmission / reception with a bit number could not be performed. Further, the prior art does not describe the processing of transmitted serial data and the configuration of the receiving side that receives serial data and converts it into parallel data. Further, in the conventional technique, there is a problem in that it is not possible to specify reception only by specifying the number of bytes to be sent.

An object of the present invention is to solve such problems and to provide a serial input / output circuit capable of performing serial transmission / reception by a designated number of bits. Another object of the present invention is to provide a serial input / output circuit that can perform processing such as scrambling, error detection, and error correction on the transmitted serial data.

[0007]

SUMMARY OF THE INVENTION A serial input / output device of the present invention is a circuit for controlling a clock and a register for counting a bit to be transmitted, a register for designating a bit to be transmitted, in order to transmit and receive data of a designated number of bits. And a shifter circuit configured to convert parallel data to serial data, a register that specifies the received bit, a counter that counts the received bit, a circuit that controls the clock, and a shift register that converts the serial data to parallel data. And a sending side circuit configured by.

[0008]

Since the length of serial data to be sent and the length of serial data to be received can be freely changed, there is no need to perform unnecessary serial transmission / reception, and serial data can be efficiently transferred. The process is simplified because it is not necessary to control the data input timing to the shift register and the output timing from the shift register.

From the above, for example, a microcomputer that controls serial input / output can perform other processing, so that the processing efficiency can be improved. If this device is used for scrambling, error detection, error correction, etc., the processing speed can be increased efficiently.

[0010]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a serial data input / output circuit according to the first embodiment of the present invention. In FIG. 1, 1 is a transmission circuit for converting parallel data into serial data and transmitting, 2 is a reception circuit for receiving serial data and converting it into parallel data, 3 is a transmission control circuit for setting transmission data or a value in a register, 9 Is a reception control circuit for setting a value in transmission data or a register.

Next, the operation will be described. First, the number of bits to be transmitted from the transmission control circuit is set in the register 6, and the number of bits to be received from the reception control circuit is set in the register 12. The output signals of the register 6 and the transmission data counting counter 5 are input to the coincidence detection circuit 7, and when the two signals coincide, the clock output is prohibited, and when they do not coincide, the clock control circuit 8 outputs a signal that permits the clock output.
Output to. The operation of the coincidence detection circuit 13 is similar. In the initial state, the coincidence detection circuit 7 is prohibited from outputting the clock, the coincidence detection circuit 13 is preset to output a signal permitting the clock output, and the clock control circuit 8 permits both of these two signals. Output clock only when. Further, the coincidence detection circuit 7 switches from the clock output prohibition signal to the clock output permission signal when the WR signal output when the transmission control circuit 3 writes parallel data to the parallel-serial conversion circuit 4 is input. The match detection circuit 13 is switched in the same manner as when the RD signal output when the reception control circuit 9 reads parallel data from the serial-parallel conversion circuit 10 is input.

Here, suppose that register 6 is 10 and register 1 is
A case where 2 is set to 8 and transmission / reception is performed will be described. When 10-bit parallel data is written from the transmission control circuit 3 to the parallel-serial conversion circuit 4, the match detection circuit 7 receives W.
Output the R signal. When the WR signal is input, the coincidence detection circuit 7 outputs the clock output enable signal to the clock control circuit 8 as described above. The clock control circuit 8 outputs a clock according to this signal, and the parallel-serial conversion circuit 4 starts serial transmission. Further, the transmission data counting counter 5 and the counter 6 start counting transmission bits and reception bits, respectively. After that, transmission / reception is performed until the count value of the reception data counting counter 11 reaches 8. When the count value of the reception data count counter 11 reaches 8, the match detection circuit 13 detects that the output of the register 12 and the count value of the reception data count counter 11 match and outputs a clock output prohibition signal to the clock control circuit 8. To do.
The clock control circuit 8 stops the output of the clock by this signal, and the transmission / reception is stopped. Here, when the reception control circuit 9 reads the data received from the serial-parallel conversion circuit 10, the RD signal is output to the coincidence detection circuit 13, and the coincidence detection circuit 13 outputs the clock output enable signal and simultaneously resets the counter 6. Thereby, the transmission / reception is restarted again, and when 2 bits are transmitted, the count value of the transmission data count transmission data count counter 5 becomes 10 and the coincidence detection circuit 7 outputs the clock output prohibition signal and the transmission / reception is stopped. Here, when the next transmission data is written from the transmission control circuit 3 to the parallel-serial conversion circuit 4, a WR signal is output and the transmission data counting counter 5 is reset by the clock output permission signal from the coincidence detection circuit 7 and the transmission and reception are restarted. . Serial transmission / reception is performed by repeating this operation.

As described above, the parallel-serial conversion circuit,
Serial transmission / reception can be performed regardless of the number of bits of the serial / parallel conversion circuit and the number of bits of writing / reading of the transmission control circuit and the reception control circuit. Further, since the operation and stop of the entire circuit are controlled by using the RD signal and the WR signal, unnecessary transmission / reception is not performed.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a diagram showing the configuration of a serial input / output circuit according to the second embodiment of the present invention.

In the second embodiment, the serial input / output circuit has a TD.
A case where the present invention is applied to a device that performs high-speed data processing such as MA communication will be described. A case where transmission control and reception control are performed by one microcomputer and after performing processing such as error correction on transmitted serial data, The reception is different from that of the first embodiment.

In FIG. 2, 1 and 2 are the transmitting circuit and the receiving circuit shown in FIG. 1, 14 is a BCH circuit, 15 is a CRC circuit,
Reference numeral 16 is a scrambler circuit, and 17 is a microcomputer for controlling transmission / reception. TDMA like a mobile phone
In a communication system, it is necessary to perform scrambling, error detection, and error correction processing on a transmitted or received data string at high speed.

Next, the operation will be described.

When the microcomputer 17 writes parallel data to be processed in the transmission circuit 1, the transmission circuit 1 starts sending serial data. The microcomputer 17 writes the initial values in the BCH circuit 14, the CRC circuit 15, and the scramble circuit 16 in advance.
Here, FIG. 3 is a diagram showing an example of the configuration of the CRC circuit 15 that performs error detection, FIG. 4 is a diagram of the configuration of the BCH circuit 14 that adds an error correction code, and FIG. 5 is a diagram showing an example of the configuration of the scramble circuit 16 that generates a random code. The serial data sent from the transmission circuit is input to the BCH circuit 14 and the CRC circuit 15 and processed simultaneously. In the CRC circuit 15, the input data string is shifted by 1 bit by the shift registers 30 to 37 to generate an error detection code, and the generated data is output to the microcomputer 17. The microcomputer 17 adds this output after the target data to be processed and writes it in the transmission circuit 1. In the BCH circuit 14, the error correction code is generated and added by shifting the registers 38 to 41 to the input data string by 1 bit like the CRC circuit, and then the data is output. The scramble circuit 16 generates a random code according to the set initial value, and B
It scrambles by taking the exclusive OR with the serial data output from the CH circuit 14, and outputs the result to the receiving circuit 2. In the receiving circuit 2, the serial data processed as described in the first embodiment is converted into parallel data, the result is read by the CPU 17, and the necessary data processing is completed.

As described above, the series of data processing required for the communication device can be collectively performed, and the processing speed can be increased.

Although the processing at the time of transmission of the communication device has been described in the present embodiment, the processing at the time of reception can be similarly applied.

Needless to say, only the transmission circuit described in this embodiment can be used alone.

The receiving circuit can be used independently if a clock control circuit for controlling the output by the coincidence detecting circuit 13 is provided as in the transmitting circuit.

[0025]

By thus performing serial transmission / reception, serial transmission / reception can be performed regardless of the number of bits of the parallel / serial conversion circuit, the serial / parallel conversion circuit, and the writing / reading bits of the transmission control circuit and the reception control circuit.

In other words, data can be transmitted or received with the required number of bits depending on the situation, so that highly efficient data transmission can be performed as compared with the conventional data transmission / reception with a fixed number of bits.

Further, since unnecessary transmission / reception is not performed, for example, the CPU used for transmission / reception control can concentrate on other processing, and the processing efficiency can be improved.

If used for serial data processing of a communication device or the like, data can be processed efficiently and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a CRC circuit in FIG.

4 is a block diagram showing a configuration of a BCH circuit in FIG.

5 is a block diagram showing a configuration of a scramble circuit in FIG.

FIG. 6 is a block diagram showing a conventional serial input / output circuit.

[Explanation of Codes] 1 ... Transmission circuit, 2 ... Reception circuit, 3 ... Transmission control circuit, 4 ... Parallel-serial conversion circuit, 5 ... Transmission data counter, 7, 13 ... Match detection circuit, 8 ... Clock control circuit, 9 ... reception control circuit, 10 ... serial-parallel conversion circuit, 11 ... reception data counter, 14 ... BCH circuit, 15 ... CRC circuit, 16 ... scramble circuit, 17 ... microcomputer.

Claims (4)

[Claims] 1. A transmission side converts parallel data to be transmitted into parallel data by a parallel-serial conversion unit and sends the serial data, and a reception side converts the serial data into parallel data by a serial-parallel conversion unit. In a serial data input / output circuit that is generated from either the transmitting side or the receiving side and whose transmission timing is set according to a clock common to the transmitting and receiving sides, specify the number of bits for converting parallel data to serial data in the transmitting side. Control means and storage means for storing the designated value of the control means, counting means for counting the number of serial data sent, comparison means for comparing the outputs of the storage means and the counting means, and the output of the comparison means Serial input / output, characterized by including a clock control means for controlling a transmission / reception clock circuit. 2. A transmission side converts parallel data to be transmitted into parallel data by a parallel-serial conversion unit and sends the serial data, and a reception side converts the serial data into parallel data by a serial-parallel conversion unit. In a serial data input / output circuit that is generated from either the transmitting side or the receiving side and whose transmission timing is set according to a clock common to the transmitting and receiving sides, specify the number of bits for converting parallel data to serial data in the transmitting side. Control means and storage means for storing the designated value of the control means, counting means for counting the number of serial data sent, comparison means for comparing the outputs of the storage means and the counting means, and the output of the comparison means Serial input / output, characterized by including a clock control means for controlling a transmission / reception clock circuit. 3. On the transmitting side, parallel data to be transmitted is converted into serial data by a parallel-serial conversion section and sent out, and on the receiving side, the serial data is converted into parallel data by a serial-parallel conversion section, In a serial data input / output circuit that is generated from either the transmitting side or the receiving side and whose transmission timing is set according to a clock common to the transmitting and receiving sides, specify the number of bits for converting parallel data to serial data in the transmitting side. First control means, first storage means for storing specified values of the first control means, first counting means for counting the number of transmitted serial data, the first storage means, and the first First comparing means for comparing the outputs of the counting means and the first clock for inputting the output of the first comparing means to control the transmission / reception clock. Lock control means, second control means for designating the number of bits for converting serial data to parallel data on the receiving side, second storage means for storing the designated value of the second control means, and transmitted serial data. The second counting means for counting the number, the second storage means and the second comparing means for comparing the outputs of the second counting means and the output of the second comparing means are input to transmit and receive clocks. A serial input / output circuit comprising: a second clock control unit for controlling. 4. An error detecting means for generating, adding and detecting an error detecting code by inputting serial data output from a transmitting side and an output of the error detecting and outputting means for generating and adding an error correcting code. A mobile communication device comprising: an error correction means for detecting; a scrambling means for generating a random number to scramble serial data; and the serial input / output circuit according to claim 3.