JPH0722514A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit capable of correcting semiconductor element parameters such as resistance and circuit characteristics such as delay even after assembly. CONSTITUTION:When selecting a resistance 26 inside a resistance portion 29, a control signal 101 is set to 0V and control signals 102 and 103 are set to 5V. When only a transfer gate 1 is turned on and a voltage of 30V (value higher than insulation breakdown voltage of MOS capacity) is applied to an input terminal 81, an electric charge is stored in the MOS capacity 4. During this period, a transfer gate 13 is set to off state, thereby preventing the application of a voltage of 30V to the gate of a PMOS transistor forming a transfer gate 20. As the potential at a nodal point N0 rises, the MOS capacity 4 is subjected to dielectric breakdown and the potential at the nodal point N1 drops to almost 0V. A control signal 104 is set to 5V and the transfer gate 13 is turned on. Thus, the transfer gate 20 comes to have an ON state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit applied for correction of circuit characteristics including parameters of semiconductor elements such as resistance elements and delay.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, if a highly accurate characteristic is required in an analog circuit or the like, a certain fuse arranged in the circuit is cut by a laser device or the like. Thus, the parameters of the semiconductor element such as the resistance element are corrected.

FIG. 4 shows an example of this type of semiconductor integrated circuit, which is a relatively simple circuit configuration. As shown in FIG. 4, corresponding to terminals 87 and 88,
Resistors 66, 67 and 68 and fuses 69 and 70
It is composed of and. In the case of this conventional example, a combination of resistance values of several resistors 66, 67 and 68 can be obtained by arbitrarily cutting the fuses 69, 70 and 71. For example, when the fuses 69 and 70 are cut, the resistance values of the resistors 66, 67 and 68 are set as R ₆₆ , R ₆₇ and R ₆₈ , respectively, and the terminal 87 and the terminal 8 are set.
A resistance value of R ₆₆ + R ₆₇ + R ₆₈ is formed as the resistance value between 8 and, when the fuses 70 and 71 are cut, the resistance value R of the resistance 66 is between the terminals 87 and 88.
₆₆ is set.

In this case, it is assumed that the allowable value for the designed resistance value is ± 5%, the manufacturing variation is ± 10%, and the standard resistance value is 100Ω. The resistance values of the resistors 66, 67 and 68 in FIG. 4 are respectively R ₆₆ = 95Ω, R ₆₇ = 5Ω and R
Set ₆₈ = 6Ω. Accordingly, for example, by selecting the resistors 66 and 67, a resistance value of 100Ω can be obtained as the resistance value R between the terminals 87 and 88. However, since there is a variation of ± 10% in the manufacturing process, it is assumed that R ₆₆ = 104.5Ω and R ₆₇ = 5.5.
When it becomes Ω, the resistance value R between terminals 87 and 88
Results in R = R ₆₆ + R ₆₇ = 110Ω, which exceeds the design tolerance ± 5%. Therefore, in this case, it suffices to select and use only the resistor 66, and thereby the resistance value becomes R = R ₆₆ = 104.5Ω, and the resistance value within the design allowable value ± 5% can be obtained. You can

As an actual correction method, a correction operation including a fuse cutting operation is performed at the time of resistance measurement in a characteristic inspection performed in a wafer state.

[0006]

In the conventional semiconductor integrated circuit described above, as shown in the conventional example of FIG.
When the circuit element is corrected and the resistance value is set, the fuse portion provided inside the circuit may not be completely blown, which may make it impossible to surely correct the circuit. There is.

Further, in the actual correction work, since the resistance value is corrected and set at the stage of inspecting on the wafer, the resistance value is changed in a product after assembly in a plastic case, for example. However, there is a drawback that the correction cannot be performed.

[0008]

A semiconductor integrated circuit according to the present invention includes a MOS capacitance destruction circuit including a MOS transistor and a MOS capacitance which is dielectrically destroyed by a predetermined input voltage via a first control signal. A gate circuit that receives the level signal output from the MOS capacitance destruction circuit due to the insulation breakdown of the MOS capacitance and outputs the level signal to the gate via a second control signal, and a level signal output from the gate circuit A plurality of circuit connecting means including at least a transfer gate which functions to close a predetermined two terminals by being controlled by a plurality of circuit connecting means. It is characterized in that it is possible to correct circuit characteristics including the above after assembly of the semiconductor chip.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, transfer gates 1, 5 and 9 for selecting a MOS capacitor to be subject to dielectric breakdown, a transfer gate 13 for selecting and outputting a control signal for resistance selection, 15 and 17,
Inverters 2, 6 and 10 involved in turning on / off of transfer gates 1, 5 and 9, inverters 14, 16 and 18 involved in turning on / off of transfer gates 13, 15 and 17, PMOS transistors 3, 7
And 11, MOS capacitors 4, 8 and 12 to be subject to dielectric breakdown, and a transfer gate 2 for selecting a resistance
0, 22 and 24, these transfer gates 2
A correction circuit unit 25 including inverters 19, 21 and 23 involved in turning on / off 0, 22 and 24, and a resistor 2
And a resistance portion 29 including 6, 27 and 28.

As described above, the transfer gates 1, 5
And 9 are transfer gates for selecting the MOS capacitors 4, 8 and 12 to be subjected to dielectric breakdown, and the transfer gates 13, 15 and 17 are
The transfer gate is also applied to prevent circuit breakdown due to high voltage applied across the MOS capacitors 4, 8 and 12, respectively. The transfer gates 20, 22 and 24 are transfer gates for selecting the resistors 26 (resistance value R ₂₆ ), 27 (resistance value R ₂₇ ) and 28 (resistance value R ₂₈ ) included in the resistance unit 29, respectively. is there.

In FIG. 1, for explanation of operation, the insulation breakdown voltage of the MOS capacitors 4, 8 and 12 is set to 20V, and the power supply voltage V _DD is set to 5V. Further, the on-resistance value of the PMOS transistor 3 is R _P3 , and P that forms the transfer gate 1
The ON resistance values of the MOS transistor and the NMOS transistor are R _P1 and R _N1 , respectively, and the ON resistance value of the MOS capacitor 4 after the dielectric breakdown is R _C4 . And
With respect to these resistance values, in the present embodiment, R _P1 :
It is assumed that the relational expression of R _C4 = R _P3 : R _P1 = R _P3 : R _N1 = 100: 1 holds. This assumption is based on other PMOS
The same applies to the transistor 7, the transfer gate 5 and the MOS capacitor 6, and the PMOS transistor 11, the transfer gate 9 and the MOS capacitor 12.

Table 1 below shows how to select the resistance value,
FIG. 1 corresponds to the correction method and each operation mode of actual use.
Control signals 101, 102, 103, 104 shown in FIG.
5 is a state transition diagram of the voltage levels of 105 and 106, the voltage level of the input terminal 81, the selected resistance value, and the like. FIG.

[0014]

[Table 1]

First, a method of selecting the resistance value will be described. When selecting the resistance value, first the control signal 101
And 103 are set to 5V and the control signal 102 is 0
Set to V. As a result, only the transfer gate 5 is turned on. In this state, the input terminal 8
A voltage of 1 to 0 V is applied. The potential of the node N ₂ is almost 0
It becomes V (at the ratio of V _DD · 1/101). Next, when the control signal 105 is set to 5V while the control signals 104 and 106 are set to 0V, the transfer gate 15 is turned on, and the potential of the node N ₅ is approximately 0V (V _DD (At a ratio of 1/101), the transfer gate 22 is turned on. As a result, the resistors 26 and 27 are selected from the resistors included in the resistor unit 29, and the resistance value R between the terminals 82 and 83 is R =
It becomes R ₂₆ + R ₂₇ .

In this case, it is assumed that the allowable value for the designed resistance value is ± 5%, the manufacturing variation is ± 10%, and the standard resistance value is 100Ω. Then, the resistance values of the resistors 66, 67 and 68 in FIG. 4 are set to R ₂₆ = 95Ω, R ₂₇ = 5Ω and R, respectively.
Set ₂₈ = 6Ω. Therefore, as described above, the resistor 82
And 83 to select terminals 82 and 83
A resistance value of 100Ω is obtained as the resistance value R between them. However, since there is a variation of ± 10% in the manufacturing process, it is assumed that R ₂₆ = 104.5Ω and R ₂₇ = 5.
When it becomes 5Ω, the resistance value R between the terminals 82 and 83 becomes R = R ₂₆ + R ₂₇ = 110Ω, which exceeds the design allowable value ± 5%. Therefore, in this case, only the resistor 26 needs to be selected and used,
As a result, the resistance value becomes R = R ₂₆ = 104.5Ω, and the resistance value within the design allowable value ± 5% can be obtained. This means that it is necessary to correct by selecting only the resistor 26 as the resistance value between the terminals 82 and 83.

Next, a correction method for correcting the total resistance value (R ₂₆ + R ₂₇ ) of the resistors 26 and 27 to R ₁ will be described. First, the control signal 101 is set to 0V, and the control signal 1
02 and 103 are set to 5V. As a result, only the transfer gate 1 is turned on, and in this state, when a voltage of 30 V (value higher than the dielectric breakdown voltage of the MOS capacitor) is applied to the input terminal 81, charges are accumulated in the MOS capacitor 4. Therefore, the potential of the node N1 is 30V
Rise to. During this period, the transfer gate 13 is set to the off state so that the voltage of 30 V is not applied to the gate of the PMOS transistor forming the transfer gate 20. Then, as the potential of the node N ₁ rises, the MOS capacitor 4 is dielectrically broken down by the voltage, which causes the potential of the node N ₁ to be approximately 0 V from the relational expression of R _P3 : R _C4 = 100: 1. (At a ratio of V _DD · 1/101). Then, by setting the control signal 104 to 5V, the transfer gate 13 is turned on, and the potential of the node N ₄ is approximately 0V (V _DD · 1/10).
It becomes 1). Therefore, the transfer gate 20
Is turned on, whereby the resistor 26 among the resistors included in the resistor portion 29 is selected and the terminals 82 and 8 are selected.
The resistance value R between 3 is set to R = R ₂₆ + R _P20 + R _N20 . Note that R _P20 and R _N20 are a PMOS transistor forming the transfer gate 20 and an N transistor, respectively.
This is the on-resistance value of the MOS transistor.

The state transition diagram relating to the resistance value correction in this embodiment is as shown in Table 1 above, and in this way, even after the assembly process of the semiconductor integrated circuit, the input terminal 81 is connected. The resistance value can be easily selected and corrected by the input signal level and the plurality of control signals. Further, after the resistance value is corrected, when the resistance value R between the terminals 82 and 83 is actually used as R ₁ , the input terminal 81 is opened and the control signals 101, 102, 103, 104, 105 are opened. And 106
By fixing all potential levels of 5V, R = R
Can be obtained as ₁ .

Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing this embodiment. As shown in FIG. 2, in the present embodiment, the MO that is the target of the dielectric breakdown.
Transfer gates 30 and 39 for selecting the S capacity
And 47, transfer gates 35, 43 and 51 for selecting and outputting a control signal for delay time selection, inverters 32, 40 and 48 involved in turning on / off the transfer gates 30, 39 and 47, and transfer gates 35, 43. And the inverters 36, 44 and 52 involved in turning on and off, and the PMOS transistor 3
3, 41 and 49, MOS capacitors 34, 42 and 50 to be subject to dielectric breakdown, transfer gates 37, 45 and 53 for selecting delay time, and involvement in turning on / off of these transfer gates 37, 45 and 53 Correction circuit section 55 including inverters 38, 46 and 54, and delay circuit section 59 including delay blocks 56, 57 and 58.
6, 57 and 58 each have two inverters and one
It is formed of individual capacitors.

As shown in FIG. 2, in the overall circuit configuration, the correction circuit section 55 has exactly the same configuration as the correction circuit section 25 in the first embodiment described above, and the correction circuit section 55 of the first embodiment is the same. In this case, the resistance section 29 is provided and the resistance values of the resistances 26, 27 and 28 included in this resistance section 29 are selected, whereas in the present embodiment, the delay circuit section 59 is selected. The delay time of the signal output from the terminal 86 is selected by selecting the delay blocks 56, 57 and 58 included in the delay circuit section 59.

Now, the delay time per delay block is 5
With ns (nanoseconds), it can be seen that two delay blocks should be selected when a delay time of 10 ns is required. For example, it suffices to select the delay blocks 56 and 57 in FIG. 3, and in this case, the MOS capacitor 42 is dielectrically broken down. That is, as is apparent from the description of the operation of the first embodiment, the gate input to the transfer gate 45 via the transfer gate 43 becomes low level by the dielectric breakdown of the MOS capacitor 42, which causes the transfer gate 45 to operate. The delay block 5 included in the delay circuit section 59 is turned on.
8 is passed and between terminals 85 and 86 only delay blocks 56 and 57 are selected. Then, actually, the sum of the delay times of the delay blocks 56 and 57 is
It is practically used as the delay time value of the delay circuit section 59.

[0022]

As described above, the present invention uses MOS capacitors as means for selecting circuit elements, and
By performing insulation breakdown of the OS capacitance by a control signal or the like from the outside to perform the correction, it is possible to surely perform the correction on the semiconductor element, and also after the assembling process, the parameters of the semiconductor element and the circuit such as the delay. There is an effect that the characteristics can be set arbitrarily.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 5, 9, 13, 15, 17, 20, 22, 24, 3
0, 35, 37, 39, 43, 45, 47, 51, 53
Transfer gates 2, 6, 10, 14, 16, 18, 19, 21, 23,
32, 36, 38, 40, 44, 46, 48, 52, 5
4 Inverter 3, 7, 11, 33, 41, 49 PMOS transistor 4, 8, 12, 34, 42, 50 MOS capacity 25, 55 Correction circuit section 26-28, 67-69 Resistor 56-58 Delay block 58 Delay circuit Department

Claims (1)

[Claims] 1. A MOS capacitance destruction circuit including a MOS transistor and a MOS capacitance that is dielectrically destroyed by a predetermined input voltage via a first control signal, and the MOS capacitance destruction circuit by dielectric breakdown of the MOS capacitance. A gate circuit that receives a level signal output from the gate circuit and outputs the level signal to a gate via a second control signal; and a level signal output from the gate circuit controls the circuit to close a predetermined two terminals. And a plurality of circuit connecting means including at least a transfer gate that functions as described above. The plurality of circuit connecting means provide circuit characteristics including parameters of semiconductor elements such as resistors and delays after assembling the semiconductor chip. A semiconductor integrated circuit, which can be corrected.