JPH0722436A - Method and device for electric charge transfer - Google Patents

Abstract

PURPOSE:To enlarge dynamic range, with a linearity in voltage-electric charge conversion characteristics maintained, by having another electric charge transfer means for taking out a specified amount of electric change, accumulated in the first storage area, for each one cycle of pulse signal, for transfer. CONSTITUTION:Among the electric charge quantity converted by voltage-electric charge conversion mechanism, no unnecessary electric charge is supplied to an electric charge transfer mechanism at a post stage, and only the electric charge quantity proportional to input voltage is supplied. Far example, the electrons transferred in the direction B-B' are gradually accumulated n a storage area under a gate electrode 17 between n<-> areas 21 and 22. When the potential of the storage area becomes equal to or less than that of an n<+> area 23, the accumulated electrons are made to flow into the n<+> area 23 in accordance with phases when pulse voltage H1 becomes high level. The electrons transferred in the direction A-A' are, while pulse voltages H1 and H2 become high level and law level alternately, sequentially transferred into the direction A-A'.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CCD delay line, CCD
The present invention relates to a charge transfer element used for a comb filter or the like, and particularly to a charge input portion of the charge transfer element.

[0002]

2. Description of the Related Art In a CCD charge transfer device, charges (mainly electrons) are transferred as a bearer of a signal amount, so that a voltage-charge conversion is usually performed at an input portion. After the input signal is converted into electric charges, a desired number of transfer stages are transferred, or after signal processing is performed in the electric charge state, electric charge-voltage conversion is performed at the output section.

Therefore, it is necessary to correctly convert the input voltage signal into the charge amount signal at the input section, and a voltage-charge conversion mechanism having excellent linearity is required. As a voltage-charge conversion mechanism of CCD, a diode cutoff method, a potential balance method, etc. are known and have been used conventionally.

The voltage-charge conversion mechanism by the diode cutoff method will be described below with reference to FIGS. 10 and 11. FIG. 10A shows a cross-sectional view when a voltage-charge conversion mechanism and a charge transfer mechanism by a diode cutoff method are formed on a p-type semiconductor substrate. p-type semiconductor substrate 1
00 surface is provided with an n ⁺ region 101, and an n region 102 is provided at a position separated from the n ⁺ region 101 by a predetermined distance.
The pn junction between the n ⁺ region 101 and the p-type region forms the input diode 113. In the n region 102,
N ⁻ regions 103 and 104 are provided at a predetermined interval. Note that a predetermined number of n ⁻ regions are provided at equal intervals in the right direction in the figure, that is, in the direction in which charges are transferred, like the n ⁻ regions 103 and 104.

Between the n ⁺ region 101 and the n region 102, gate electrodes 105, 106 and 107 having an insulated gate structure by the double polysilicon technique are formed in this order. One end of the gate electrode 105 is the n ⁺ region 10
It is arranged so as to slightly overlap the upper part of 1 and the other end to slightly overlap the gate electrode 106 while maintaining insulation.

One end of the gate electrode 107 is connected to the gate electrode 10
6 overlaps a little while maintaining insulation, and n region 10
It is arranged so as to straddle the boundary line between 2 and the p-type region.
It Gate electrode 107 and n^-N with region 103^-Territory
Between areas 103 and 104 and n^-Shown in area 104 and in the figure
Not n^-Another n formed on the right side of the region 104 ^-
A gate electrode 1 having an insulated gate structure between the region and the region
08, 110 and 112 are provided.

Further, n ^- region 103 and n ^- region 104
Gate electrodes 109 and 111 having an insulated gate structure are provided on the upper side of the gate electrodes so that both ends slightly overlap the adjacent gate electrodes while maintaining the insulating property. In addition,
Gate electrodes are similarly provided on the n ⁻ regions provided at equal intervals in the right direction in the figure and between adjacent n ⁻ regions.
The gate electrodes are arranged so as to be slightly insulated from each other while being insulated from each other. Gate electrode 107-10
The sets of 8, 109-110, and 111-112 are connected to each other.

A predetermined DC voltage is applied to the n ⁺ region 101, and pulse voltages IG1 and IG2 are applied to the gate electrodes 105 and 107-108, respectively. The input voltage IN is applied to the gate electrode 106. The pulse voltage H1 is applied to the gate electrodes 109-110, and the pulse voltage H2 is applied to the gate electrodes 111-112. Note that pulse voltages H1 and H2 are similarly applied alternately to the gate electrode periodically provided in the right direction in the figure. The timing diagram for these voltages is shown in FIG.

10 (B) to 10 (D) are shown in FIG.
FIG. 6A shows a potential diagram of a channel region of the voltage-charge conversion mechanism and the charge transfer mechanism shown in FIG. In the figure, since the energy for electrons is taken as the vertical axis, the high potential portion is shown low (hereinafter referred to as the potential well). Since DC voltage ID is applied to n ⁺ region 101, electrons are always filled up to energy level ID.

When the pulse voltage IG1 or IG2 is at a high level, the potential of the channel region under each gate electrode becomes higher than the potential of the n ⁺ region 101 (hereinafter referred to as ON state), and conversely the pulse voltage IG1 or IG2. Is low, the levels of ID, IG1, and IG2 are selected so that the potential of the channel region under each gate electrode becomes lower than the potential of the n ⁺ region 101 (hereinafter referred to as OFF state).

The input voltage IN is applied to the gate electrode 106.
The potential of the lower channel region is selected to be higher than that of the n ⁺ region 101. In the case shown, the input voltage IN is
Furthermore, it is selected so as to fluctuate within a range such that it is lower than the potential of the channel region when IG1 or IG2 is in the ON state.

Since the potential of the n region 102 is higher than that of the p type region, the gate electrodes 107, 1
The potential of the channel region under 08 changes stepwise at the boundary between the n region 102 and the p-type region as shown in the figure. Further, since the potential of the n ⁻ region is lower than the potential of the n region, it changes stepwise at the boundary portion between the n region 102 and the n ⁻ regions 103 and 104 as shown in the figure. By changing the pulse voltages IG2, H1, and H2, these two-step staircase potential portions move up and down while maintaining the staircase shape.

FIG. 10B shows the state of the phase P2 shown in FIG. Since the pulse voltage IG1 is in the ON state, electrons in the n ⁺ region 101 are injected into the channel region below the gate electrodes 105 and 106. Since the pulse voltage IG2 is in the OFF state, the channel region under the gate electrode 107 serves as a potential barrier, and the injected electrons are blocked by this potential barrier. The electrons transferred in the previous cycle are accumulated in the potential well below the gate electrode 110.

FIG. 10C shows the state of the phase P3 shown in FIG. When the pulse voltage IG1 is turned off, a potential barrier is formed under the pulse voltage IG1, and the gate electrode 106
The electrons injected below are separated from the n ⁺ region 101.
At this time, the amount of electric charge accumulated under the gate electrode 106 is an amount of electric charge corresponding to the input voltage IN with reference to the DC voltage ID. In this way, the charge amount corresponding to the input voltage IN can be separated and taken out.

Further, since the pulse voltages H1 and H2 are both inverted, the potential under the gate electrodes 109, 110 is lowered and the potential under the gate electrodes 111, 112 is raised. Therefore, the charges accumulated under the gate electrode 110 are accumulated in the gate electrode 112 having a higher potential.
Move down. In this way, the charges are sequentially transferred.

FIG. 10D shows the state of the phase P4 shown in FIG. By turning on the pulse voltage IG2, the potential barrier under the gate electrode 107 disappears, and the charges accumulated under the gate electrode 106 are transferred to the n region 102 under the gate electrodes 107, 108 having higher potential. To be done. In this way, the amount of electric charge extracted corresponding to the input voltage IN is sequentially transferred to the right in the figure.

In the above-mentioned example, since the input voltage IN is applied to the gate electrode 106, the voltage-charge conversion characteristic becomes a positive phase characteristic. That is, as the input voltage IN increases, the potential well under the gate electrode 106 becomes deeper and the amount of transferred charges also increases.

A method of applying a constant DC voltage to the gate electrode 106 and applying an input voltage IN to the n ⁺ region 101 is also conceivable. In this case, the voltage-charge conversion characteristic is a reverse phase characteristic. That is, as the input voltage IN increases, the n ⁺ region 1
The energy of electrons filling 01 becomes low, the amount of charges injected under the gate electrode 106 becomes small, and the amount of charges transferred becomes small. However, the latter method is not normally used because the depletion layer width inside the semiconductor substrate is modulated by the input voltage IN and the substrate capacitance changes, and therefore the linearity of the voltage-charge conversion characteristic is poor.

In either case, the n ⁺ region 101
When the potential of the channel region below the gate electrode 106 is higher than that of the gate electrode 106, the signal charge amount corresponding to the potential difference is weighed.

FIG. 11A shows the relationship of the converted charge amount with respect to the input voltage IN. When a positive potential is applied to the surface of the p-type substrate via the insulating electrode, the p-type surface is depleted at first,
Eventually it will flip. In a region where the input voltage IN is low, the conductivity type of the p substrate surface under the gate electrode 106 is in a weak inversion state, and electrons are distributed from the substrate surface to a slightly deep region. Therefore, the differential capacitance between the gate electrode 106 and the p substrate is not constant as shown in FIG.

When the input voltage IN is V1 or more, the conductivity type of the substrate surface is in a strongly inverted state, and most of the electrons are concentrated on the substrate surface, so that the differential capacitance is constant as shown in FIG. 11 (B). become. When the input voltage IN becomes V4 or more, the insulating film under the gate electrode 106 causes electrostatic breakdown, and the input differential capacitance becomes zero.

As described above, since the differential capacitance is not constant when the input voltage IN is V1 or less, the relationship of the converted charge amount with respect to the input voltage IN is not linear as shown in FIG. Therefore, it is difficult to use the region where the input voltage is V1 or less as the signal region. Therefore, normally, the input signal is clamped to a predetermined DC potential so that the input voltage IN does not become V1 or less even at the lowest level of the input signal. Therefore, the converted charge amount Q1 when the input voltage IN is V1 is an unnecessary charge irrelevant to the input signal. This unnecessary charge is used as a fat zero bias charge to improve the transfer efficiency of the CCD.

The unnecessary charges are transferred through the CCD transfer path together with the signal charge amount corresponding to the input signal. On the other hand, CCD
The transfer path has a maximum transfer charge amount determined by the transfer path width, internal impurity profile, etc., and the transferable signal charge amount is limited by the physical size of the CCD and the transfer efficiency. If the converted charge amount becomes the maximum transfer charge amount Q3 when the input voltage IN is V3, the region where the input voltage is V3 or higher cannot be used as the signal region. Therefore, the dynamic range of the input signal is limited by the unnecessary charge amount Q1 and the maximum transfer charge amount Q3. Therefore, it is preferable to clamp the input signal to the DC potential so that the input voltage IN when the input signal is at the lowest level is V1 or higher and the input voltage IN when the input signal is at the highest level is V3 or lower.

[0024]

As described above,
In the voltage-charge conversion mechanism of the conventional charge transfer device,
Since the conversion characteristic becomes non-linear in the region where the input voltage is less than the predetermined value, this non-linear region cannot be used as the signal region.
This limits the lower limit of the dynamic range of the input signal. Further, the upper limit of the dynamic range is limited by the physical size of the charge transfer path and the like.

As described above, when the physical size of the charge transfer path is constant, the linearity of the voltage-charge conversion characteristic and the expansion of the signal dynamic range are in a reciprocal relationship. That is, if the linearity is improved, the dynamic range is reduced and the S / N is deteriorated. On the contrary, when the dynamic range is expanded, the linearity is deteriorated.

An object of the present invention is to provide a charge transfer device and a voltage-charge conversion method capable of expanding the dynamic range while maintaining the linearity of the voltage-charge conversion characteristic.

[0027]

According to the charge transfer method of the present invention, an input voltage is converted into a charge amount for each cycle of a periodic pulse signal, and the converted charge is transferred along a transfer path. In the method, a constant amount of electric charge is weighed from the converted electric charge, and the remaining electric charge obtained by removing the predetermined amount of electric charge from the converted electric charge is transferred for each cycle of the pulse signal. To do.

The charge transfer device of the present invention includes voltage-charge conversion means for converting an input voltage into a charge amount for each cycle of a periodic pulse signal, and a plurality of regions capable of accumulating charges. In a charge transfer device having a charge transfer means for transferring a charge by a pulse signal, a first storage area provided on the input side of the charge transfer means for storing a certain amount of charge, and the first storage area. A second storage area for accumulating charges overflowing from the area and transferring the charges to the charge transfer means, and a certain amount of charges accumulated in the first storage area are stored in the pulse signal 1
Other charge transfer means for taking out and transferring each cycle is included.

Further, another charge transfer device of the present invention is a voltage-charge conversion means for converting an input voltage into a charge amount for each cycle of a periodic pulse signal, and a plurality of regions capable of accumulating charges. And a charge transfer device for transferring charges by the pulse signal, the charge transfer device being provided adjacent to the charge transfer device for accumulating the charges converted by the voltage-charge conversion device. A third storage region, and a fourth storage region provided between the third storage region and the charge transfer means for accumulating the charge overflowing from the third storage region for each cycle of the pulse signal. Storage area, and another charge transfer means for transferring the charge remaining in the third storage area for each cycle of the pulse signal.

[0030]

In the charge quantity converted by the voltage-charge conversion means, only the remaining charge quantity excluding a constant charge quantity irrelevant to the input signal can be supplied to the charge transfer means.
Therefore, the charge transfer means does not need to transfer the unnecessary charges unrelated to the input signal. Therefore, if the amount of transferred charges is the same, the chip area of the charge transfer means can be reduced. Further, if the chip areas of the charge transfer means are the same, the entire range up to the maximum transfer charge amount can be used by the input signal, so the dynamic range is expanded.

[0031]

EXAMPLE A first example of the present invention will be described below with reference to FIGS. FIG. 1 shows a plan view of a charge transfer device according to a first embodiment. 2 (A), (C)
3A and 3B are sectional views taken along the lines AA 'and BB' of FIG. 1, respectively. AA ′ is the normal charge transfer direction, and B
-B 'is a direction in which a fixed amount of unnecessary charges are weighed and the extracted charges are discharged.

The charge transfer path 24 shown in FIG. 1 extends in the AA 'direction, and the electrons injected from the n ⁺ region 1 are transferred in the A'direction in the figure. Further, the charge transfer path 24 is branched at the portion of the gate electrode 13, and the branched transfer path extends in the B ′ direction. Some of the electrons injected from the n ⁺ region 1 are also transferred in the B ′ direction and absorbed in the n ⁺ region 23. These charge transfer paths are laterally defined by LOCOS (local oxidation) regions. How the electrons are branched and transferred will be described later in detail with reference to FIG.

In the A-A 'direction, as shown in FIG.
On the surface of the p-type semiconductor substrate⁺Region 1 and this n⁺region
N region 2 is provided at a position apart from 1 by a predetermined distance.
It n ⁺The pn junction between region 1 and p-type region 7 is the input
The diode 8 is formed. In the n region 2, n^-Territory
Areas 3, 4, 5, and 6 are provided at predetermined intervals. Na
In the right direction in the figure, that is, in the direction in which charges are transferred,
n^-Similar to the areas 5 and 6, a predetermined number of n is equally spaced.^-Area is
It is provided.

A gate electrode 9 having a double polysilicon type insulated gate structure is provided between the n ⁺ region 1 and the n region 2.
10 and 11 are formed in this order. Gate electrode 9
Is arranged so that one end thereof slightly overlaps the upper portion of the n ⁺ region 1 and the other end thereof slightly overlaps the gate electrode 10 while maintaining insulation. One end of the gate electrode 11 slightly overlaps the gate electrode 10 while maintaining the insulating property, and the main portion is arranged so as to straddle the boundary line between the n region 2 and the p-type region.

Between the gate electrode 11 and the n ⁻ region 3, n ⁻
Between regions 3 and 4, between n ⁻ regions 4 and 5, n ⁻ region 5
And 6 and between the n ⁻ region 6 and another n ⁻ region formed on the right side of the n ⁻ region 6 (not shown) have gate electrodes 12, 14 having an insulated gate structure, respectively. ,
15, 17 and 19 are provided.

Further, both ends of the n ⁻ regions 3 and 4 slightly overlap the gate electrodes 12 and 15 while maintaining the insulating property, and the central portion covers the gate electrode 14,
A gate electrode 13 having an insulated gate structure is provided. Further, the gate electrodes 16 and 18 having an insulated gate structure are formed on the n ⁻ regions 5 and 6 so that both ends slightly overlap the adjacent gate electrodes while maintaining insulation.
Is provided.

In addition, n provided at equal intervals in the right direction in the figure.
^- Similarly, between the regions a gate electrode is provided ^- n the area on and adjacent. These adjacent gate electrodes are arranged so as to be slightly insulated from each other while being insulated from each other.

The BB 'direction from the n ⁺ region 8 to the gate electrode 13 is common to the AA' direction as shown in FIG. 1, and is provided below the gate electrode 13 of the second polysilicon. The direction is changed by 90 degrees from the position of the first polysilicon gate electrode 14 and extends downward in the drawing. As shown in FIG. 2C, in the cross section in the BB ′ direction, the n region 2
Within the n ⁻ region 3, there is a predetermined distance from the n ⁻ region 2
1, 22 are provided in this order. In addition, n region 2
Is provided with an n ⁺ region 23 at a predetermined distance from.

Between n ^- regions 3 and 21 and n ^- region 21
Gate electrodes 14 and 17 each having an insulated gate structure are provided between and. A gate electrode 16 having an insulated gate structure is provided on the n ⁻ region 21 so that both ends thereof slightly overlap the gate electrodes 14 and 17 while maintaining insulation. Further, the gate electrode 20 having an insulated gate structure straddles the surface of the n ⁻ region 22, the n region 2 and the p-type region, one end thereof slightly overlaps with the gate electrode 17 while maintaining insulation, and the other end thereof is the n ⁺ region 23.
It is provided so that it slightly overlaps the top.

A predetermined DC voltage ID is applied to n ⁺ region 1, pulse voltage IG1 is applied to gate electrode 9, and pulse voltage IG2 is applied to gate electrodes 11 and 12. The input voltage IN is applied to the gate electrode 10. A pulse voltage H1 is applied to the gate electrodes 13, 14, and 15.
Pulse voltage H2 is applied to the gate electrodes 16 and 17.
Is being applied.

Further, the gate electrode 18 in the AA 'direction,
A pulse voltage H1 is applied to the gate electrode 20 in the 19 and BB ′ directions. Note that pulse voltages H1 and H2 are similarly applied alternately to the gate electrode periodically provided in the right direction in FIGS. 1 and 2A. The timing diagram for these voltages is shown in FIG.

2 (B) and 2 (D), the direction AA 'and the direction B are shown.
The potential figure of the channel region of a -B 'direction is shown. In the figure, since the energy for electrons is taken as the vertical axis, the high potential portion is shown low (hereinafter referred to as the potential well). Since DC voltage ID is applied to n ⁺ region 1, electrons are always filled up to energy level ID.

When the pulse voltage IG1 or IG2 is at a high level, the potential of the channel region under each gate electrode is higher than that of the n ⁺ region 1 (hereinafter referred to as ON state), and conversely the pulse voltage IG1 or IG2 is low. At the level, the levels of ID, IG1, and IG2 are selected so that the potential of the channel region under each gate electrode becomes lower than that of the n ⁺ region 1 (hereinafter, referred to as OFF state).

The input voltage IN is below the gate electrode 10.
The channel region potential is n ⁺Higher than region 1
Channel region when IG1 or IG2 is ON
It fluctuates in a range that is lower than the potential of
Choose

Since the potential of the n region 2 is higher than that of the p type region, the potential of the channel region under the gate electrodes 11 and 12 is at the boundary between the n region 2 and the p type region as shown in the figure. The potential well in the n region 2 changes stepwise so as to become deeper.

In addition, n ⁻ regions 3, 4, 5, 6, 21, 2
Since the potential of No. 2 is lower than the potential of the surrounding n region, the potential changes stepwise so that the potential well of the n region 2 becomes deeper at the boundary between the n ⁻ region and the n ⁺ region as shown in the figure. . Therefore, the n region portion sandwiched between the n ⁻ regions forms an electron storage region.

A DC voltage VDD higher than the DC voltage ID is applied to the n ⁺ region 23. DC voltage VDD
Is selected to be equal to the potential of the channel region of the p-type region under the gate electrode 20 when the pulse voltage H1 is at high level. As a result, when the pulse voltage H1 is at a high level, the electrons having the energy level VDD or higher accumulated in the channel region under the gate electrode 17 are absorbed in the n ⁺ region 23.

A method of transferring electrons will be described below with reference to FIGS. 3 and 4. In FIGS. 4A to 4G,
The left side of the figure shows the potential diagram in the AA 'direction, and the right side of the figure shows B.
A potential diagram in the −B ′ direction is shown.

FIG. 4A shows the potential of the channel region at the phase P1 of FIG. Pulse voltage IG1 is O
Due to the FF state, electrons in the n ⁺ region 1 are not injected into the channel region.

FIG. 4B shows the potential of the channel region at the phase P2 of FIG. Pulse voltage IG1 is O
Due to the N state, the electrons in the n ⁺ region 1 are injected to the channel region below the gate electrode 10.

FIG. 4C shows the potential of the channel region at the phase P3 of FIG. The pulse voltage IG1 is turned off again, and electrons are accumulated in the channel region under the gate electrode 10 separately from the n ⁺ region 1. At this time, the amount of charges separately stored is the amount of charges corresponding to the input voltage IN. This electric charge includes the unnecessary electric charge Q1 in the nonlinear region shown in FIG.

FIG. 4D shows the potential of the channel region at the phase P4 of FIG. Pulse voltage IG2 is O
The electrons in the N state and separated and accumulated under the gate electrode 10 are transferred to the potential well under the gate electrodes 11 and 12.

FIG. 4E shows the potential of the channel region at the phase P6 of FIG. Pulse voltage IG2 is O
The FF state is set, and the potential wells below the gate electrodes 11 and 12 become shallow. Further, the pulse voltage H1 becomes high level, and the potential well under the gate electrodes 13, 14, 15 becomes deep. Therefore, the electrons accumulated in the potential well below the gate electrodes 11 and 12 are transferred to the storage region below the gate electrode 14 having the deepest potential well. The electrons overflowing from the storage region under the gate electrode 14 get over the potential barrier of the n ⁻ region 4 and are accumulated in the storage region under the gate electrode 15.

FIG. 4F shows the potential of the channel region at the phase P7 of FIG. Similar to the state of FIG. 4B, since the pulse voltage IG1 is in the ON state, the n ⁺ region 1
The electrons inside are injected to the channel region below the gate electrode 10.

FIG. 4G shows the potential of the channel region at the phase P8 of FIG. Similar to the state of FIG. 4C, the pulse voltage IG1 is turned OFF again, and electrons are accumulated in the channel region under the gate electrode 10 separately from the n ⁺ region 1. At this time, since the input voltage IN has changed since the time of the phase P3, the amount of charges separated and accumulated in the channel region under the gate electrode 10 is different from that at the time of FIG. 4C, and the input voltage IN at this time is different. Is the amount of charge corresponding to.

Further, the pulse voltage H1 becomes low level and H2 becomes high level. The potential wells under the gate electrodes 13, 14, 15 become shallow, and the potential wells under the gate electrodes 16, 17 become deep. Therefore, the gate electrode 14
The electrons accumulated in the lower storage area are BB '
The electrons transferred to the storage region between the n ⁻ regions 21 and 22 in the direction and accumulated in the storage region under the gate electrode 15 are transferred to the storage region between the n ⁻ regions 5 and 6 in the AA ′ direction. It

The electrons transferred in the B-B 'direction are n^-Territory
Storage region below the gate electrode 17 between the regions 21 and 22
Gradually accumulates. The potential of this storage area
Is n ⁺If the potential is below the potential of region 23, it is accumulated.
The electrons are in a phase where the pulse voltage H1 becomes high level.
Let n⁺It flows into the area 23. Transferred in the A-A 'direction
In the generated electrons, pulse voltages H1 and H2 are alternately high level,
By repeating the low level, it is possible to rotate sequentially in the A-A 'direction.
Will be sent.

[0058] Here, the amount of charge transferred to the B-B 'direction, n ^- gate electrode 14 below the storage regions sandwiched by 3,4 and n ^- potential or internal between the regions 3 and 4 The impurity profile and the gate area of the storage region uniquely determine the input voltage IN. The amount of charge transferred in the BB ′ direction is shown in FIG.
By setting it so as to be equal to the unnecessary charge Q1 shown in (1), it becomes possible to transfer only the charge amount proportional to the signal voltage in the AA 'direction, excluding the unnecessary charge Q1.

Next, a second embodiment will be described with reference to FIGS. FIG. 5 shows a plan view of the charge transfer device according to the second embodiment. 6A and 6C are cross-sectional views taken along the lines AA ′ and BB ′ of FIG. 5, respectively.
AA 'is the normal charge transfer direction, and BB' is
This is the direction in which a certain amount of unnecessary charges are weighed and the extracted charges are discharged.

The charge transfer path 25 shown in FIG. 5 extends in the AA 'direction, and the electrons injected from the n ⁺ region 31 are transferred in the A'direction in the figure. Further, the charge transfer path 25 is branched at the portion of the gate electrode 44, and the branched transfer path extends in the B ′ direction. The side of the charge transfer path is LOCOS
It is defined by the area. Some of the electrons injected from the n ⁺ region 1 are also transferred in the B ′ direction and absorbed in the n ⁺ region 39. How the electrons are branched and transferred will be described later in detail with reference to FIG. 7.

In the AA 'direction, as shown in FIG. 6A, an n ⁺ region 31 and the n ⁺ region 31 are formed on the surface of the p-type semiconductor substrate 40.
^An n region 32 is provided at a position apart from the ⁺ region 31 by a predetermined distance. The pn junction between the n ⁺ region 31 and the p-type region forms the input diode 56. In the n region 32, n ⁻ regions 33, 34 and 35 are provided at predetermined intervals. Note that a predetermined number of n ⁻ regions are provided at equal intervals in the right direction in the figure, that is, in the direction in which charges are transferred, like the n ⁻ regions 34 and 35.

Between the n ⁺ region 31 and the n region 32, gate electrodes 41, 42 and 43 having an insulated gate structure are formed in this order. One end of the gate electrode 41 is n ⁺
It slightly overlaps the upper part of the region 31 and the other end is the gate electrode 4
It is placed on top of the two so as to slightly overlap while maintaining insulation. One end of the gate electrode 43 slightly overlaps the gate electrode 42 while maintaining the insulating property, and is arranged so as to straddle the boundary line between the n region 2 and the p-type region.

Between the gate electrode 43 and the n ⁻ region 33, n
^- between the region 34, n ^{- -} region 33 and the n region 34 and n ^-
Between the region 35 and n ⁻ region 35 and n not shown in the figure
^- Other n are formed on the right side of the region 35 ^- between the regions, the gate electrode 4 having a respective insulated gate structure
4, 46, 48 and 50 are provided.

Further, on the n ⁻ regions 33, 34, and 35, gate electrodes 45, 47, and 49 having an insulated gate structure are provided so that both ends slightly overlap the adjacent gate electrodes while maintaining the insulating property. Has been. Gate electrodes are similarly provided on the n ⁻ regions which are provided at equal intervals in the right direction in the drawing and between adjacent n ⁻ regions. These adjacent gate electrodes are arranged so as to be slightly insulated from each other while being insulated from each other.

The BB 'direction from the n ⁺ region 31 to the gate electrode 44 is common to the AA' direction as shown in FIG. 5, and the direction is changed by 90 degrees from the position of the gate electrode 44.
It extends downward in the figure. FIG. 6 is a sectional view taken along the line BB ′.
As shown in (C), in the n region 32, an n ⁻ region 36,
37 and 38 are provided in this order at predetermined intervals.
Also, one end overlaps the n ⁻ region 38 and the other end overlaps the n region 32.
The n ⁺ region 39 is provided so as to overlap the p-type region and cross the boundary of.

Gate electrode 44 is arranged so as to slightly overlap the upper portion of n ⁻ region 36. Gate electrodes 52 and 54 having an insulated gate structure are provided between the n ⁻ regions 36 and 37 and between the n ⁻ regions 37 and 38, respectively. Gate electrodes 51 and 53 having an insulated gate structure are formed on the n ⁻ regions 36 and 37 so that both ends slightly overlap adjacent gate electrodes while maintaining insulation.
Is provided. Further, a gate electrode 55 having an insulated gate structure is provided on the n ⁻ region 38 so that one end thereof slightly overlaps the gate electrode 54 while maintaining the insulating property and the other end thereof slightly overlaps the n ⁺ region 39. Has been.

Predetermined DC voltages ID and VDD are applied to the n ⁺ regions 31 and 39, respectively. Gate electrode 4
1, 45, 46, 53, 54 have a pulse voltage IG1, and gate electrodes 43, 51, 52, 55 have a pulse voltage IG1.
2 is applied. Input voltage IN is applied to the gate electrode 42.
And a DC voltage GND is applied to the gate electrode 44.

A pulse voltage H is applied to the gate electrodes 47 and 48.
1 is applied, and the pulse voltage H is applied to the gate electrodes 49 and 50.
2 is applied. Note that pulse voltages H1 and H2 are similarly applied alternately to the gate electrode periodically provided in the right direction of FIGS. 5 and 6A. The timing diagram for these voltages is shown in FIG.

FIGS. 6 (B) and 6 (D) show the direction AA ', B.
The potential figure of the channel region of a -B 'direction is shown. As in the case of FIG. 2, the figure has the vertical axis representing the energy for electrons, and therefore the high potential portion is shown low.
Since DC voltage ID is applied to n ⁺ region 31, electrons are always filled up to energy level ID. The pulse voltages IG1 and IG2, the input voltage IN and the DC voltage ID are selected in the same manner as in the first embodiment shown in FIG.

Since the potential of the n region 32 is higher than that of the p type region, the potential of the channel region under the gate electrode 43 is n region 32 as shown in the figure.
At the boundary between the p-type region and the n-type region 32, the n-region 32 potential well changes stepwise so as to become deep.

The potential well in the n region 32 portion under the gate electrode 43 is unnecessary for the operation of the charge transfer device,
It is difficult in manufacturing to align one end of the gate electrode 44 with the boundary position between the n region 32 and the p type region. Therefore, one end of the gate electrode 44 is slightly displaced from the boundary position between the n region 32 and the p-type region to the n region 32 side, so that the potential well is formed.

In addition, n ^- regions 33, 34, 35, 36,
Since the potentials of 37 and 38 are lower than the potential of the surrounding n region, the potential is stepwise so that the potential well of the n region 32 becomes deep at the boundary between the n ⁻ region and the n ⁺ region as shown in the figure. Change.

A DC voltage VDD higher than the DC voltage ID is applied to the n ⁺ region 39. DC voltage VDD
Is selected to be equal to the potential of the n ⁻ region 38 when the pulse voltage IG2 is at a high level. As a result, when the pulse voltage IG2 is at a high level, the electrons stored in the channel region under the gate electrode 54 and having the energy level VDD or higher are absorbed in the n ⁺ region 39.

A method of transferring electrons will be described below with reference to FIGS. 3 and 7. 7 (A) to (I),
The left side of the figure shows the potential diagram in the AA 'direction, and the right side of the figure shows B.
A potential diagram in the −B ′ direction is shown.

7A to 7C are similar to the operation of FIGS. 4A to 4C of the first embodiment. In FIG. 7C, a charge amount corresponding to the input voltage IN is separately accumulated in the channel region below the gate electrode 42. This charge is an unnecessary charge Q in the nonlinear region shown in FIG.
Contains 1.

FIG. 7D shows the potential of the channel region at the phase P4 of FIG. Pulse voltage IG2 is O
The N state is set, and the potential barrier under the gate electrode 43 is lowered.
The electrons that have been separated and accumulated under the gate electrode 42 are moved to the channel region under the gate electrode 44, and some of them are part of the gate electrode 5 in the BB ′ direction, which is deeper in the potential well.
Transferred to the potential well below 1,52.

FIG. 7E shows the potential of the channel region at the phase P6 of FIG. Pulse voltage IG2 is O
The FF state is set, and the potential well below the gate electrodes 51 and 52 becomes shallow. Therefore, among the accumulated electrons, electrons having energy lower than the potential barrier under the gate electrode 51 remain in the storage region under the gate electrode 52 sandwiched between the n ⁻ regions 36 and 37, but the potential under the gate electrode 51 is reduced. Electrons having higher energy than the barrier overflow and are transferred to the channel region below the gate electrode 44.

The amount of electrons separated below the gate electrode 52 is a constant amount determined by the energy difference between the potential barrier below the gate electrode 51 and the potential well below the gate electrode 51 and the area of the potential well.

FIG. 7F shows the potential of the channel region at the phase P7 of FIG. Similar to the state of FIG. 7B, since the pulse voltage IG1 is in the ON state, the n ⁺ region 1
The electrons inside are injected up to the channel region below the gate electrode 42.

The electrons accumulated in the channel region below the gate electrode 44 are transferred to the gate electrode 46 in the AA 'direction.
The data is transferred to the storage area sandwiched between the lower n ⁻ areas 33 and 34. Further, a certain amount of electrons accumulated in the storage region sandwiched between the n ⁻ regions 36 and 37 below the gate electrode 52 in the BB ′ direction are sandwiched between the n ⁻ regions 37 and 38 below the gate electrode 54. Are transferred to the storage area. Thus, the electrons injected from the n ⁺ region 31 are A−
The data is transferred separately in the A'direction and the BB 'direction.

FIG. 7G shows the potential of the channel region at the phase P8 of FIG. Similar to the state of FIG. 7C, the pulse voltage IG1 is turned off again, and electrons are accumulated in the channel region below the gate electrode 42 separately from the n ⁺ region 1. At this time, since the input voltage IN has changed since the time of phase 3, the amount of charges separated and accumulated in the channel region under the gate electrode 10 is different from that in the case of FIG. 7C.
The charge amount corresponds to the input voltage IN at this time.

Further, since the pulse voltage IG1 is at a low level, the potential wells below the gate electrodes 46 and 54 become shallow, but since the n ⁻ regions on both sides serve as potential barriers, accumulated electrons are Not transferred.

FIG. 7H shows the potential of the channel region at the phase P9 of FIG. Pulse voltage IG2 is O
Since it becomes the N state, the n ⁻ region 37 under the gate electrode 54,
The electrons accumulated in the storage area sandwiched by 38 are transferred to the n ⁺ area 39. In this way, BB '
All the electrons transferred in the direction are absorbed in the n ⁺ region 39.

FIG. 7I shows the potential of the channel region at the phase P10 of FIG. Since the pulse voltage H1 becomes high level and the pulse voltage H2 becomes low level,
The electrons accumulated in the storage region between the n ⁻ regions 33 and 34 below the gate electrode 46 are transferred to the storage region below the gate electrode 48 and between the n ⁻ regions 34 and 35 having deeper potential wells. To be done. In this way, the electrons transferred in the AA 'direction are pulse voltage H
1 and H2 are alternately transferred to the high level and the low level, so that they are sequentially transferred in the AA 'direction.

Here, the amount of charge transferred in the BB ′ direction is the potential difference between the storage region sandwiched between the n ⁻ regions 36 and 37 under the gate electrode 52 and the n ⁻ regions 36 and 37, that is, the inside. The impurity profile and the gate area of the storage region uniquely determine the input voltage IN. The charge amount transferred in the BB ′ direction is shown in FIG.
By setting it to be equal to the unnecessary charge Q1 shown in (A), the unnecessary charge Q1 is removed in the AA 'direction.
It is possible to transfer only the amount of charge proportional to the signal voltage.

Next, a third embodiment will be described with reference to FIGS. FIG. 8A shows a plan view of the charge transfer device according to the third embodiment. LOCO shown in FIG.
The charge transfer path 26 laterally defined by the S region extends in the left and right directions in the figure, and the electrons injected from the n ⁺ region 61 are transferred in the right direction in the figure.

FIG. 8B shows a sectional view of the charge transfer device according to the third embodiment. n ^{+ on the} surface of the p-type semiconductor substrate 67
A region 61 and n regions 66 and 62 are provided at predetermined distances from the n ⁺ region 61 with a predetermined space. The pn junction between the n ⁺ region 61 and the p-type region forms the input diode 68. In the n region 62,
N ⁻ regions 63, 64 and 65 are provided at a predetermined interval. Incidentally, in the right direction in the figure, that is, in the direction in which charges are transferred, a predetermined number of n ⁻ regions are provided at equal intervals as in the n ⁻ regions 64 and 65.

Between n ⁺ region 61 and n region 66, gate electrodes 69 and 70 having a double polysilicon type insulated gate structure are formed. One end of the gate electrode 69 slightly overlaps the upper part of the n ⁺ region 61, and the other end thereof slightly overlaps one end of the gate electrode 70 while maintaining insulation. The other end of the gate electrode 70 has an n region 66
It is arranged so that it slightly overlaps the upper part of the.

The p-type region sandwiched between the n regions 62 and 66 and n
^- Between the regions 63 are formed a gate electrode 72 having an insulated gate structure. A gate electrode 71 is formed between the gate electrodes 70 and 72 such that both ends thereof slightly overlap the gate electrodes 70 and 72 while maintaining insulation.

Between n ^- regions 63 and 64, n ^- region 64
And 65, and n ⁻ region 65 and n ⁻ not shown in the figure.
Between the other n ⁻ region formed on the right side of the region 65, a gate electrode 74 having an insulated gate structure,
76 and 78 are provided. Furthermore, n ⁻ region 6
Gate electrodes 73, 75, 77 having an insulated gate structure are provided on 3, 64, 65 such that both ends slightly overlap the adjacent gate electrodes while maintaining insulation.

In addition, n provided at equal intervals in the right direction in the figure.
^- Similarly, between the regions a gate electrode is provided ^- n the area on and adjacent. These adjacent gate electrodes are arranged so as to be slightly insulated from each other while being insulated from each other.

A predetermined DC voltage ID is applied to n ⁺ region 61, pulse voltage IG1 is applied to gate electrode 69, and pulse voltage IG2 is applied to gate electrodes 71-72. The input voltage IN is applied to the gate electrode 70. The pulse voltage H1 is applied to the gate electrodes 73-74 and 77-78, and the pulse voltage H2 is applied to the gate electrodes 75-76. 8 (A) and (B)
Similarly, pulse voltages H1 and H2 are alternately applied to the gate electrode periodically provided in the right direction. The timing diagram for these voltages is shown in FIG.

FIG. 8C is a potential diagram of the channel region of the charge transfer device shown in FIGS. 8A and 8B. In the figure, since the energy for electrons is plotted on the vertical axis, the high potential portion is shown low. n ⁺
Since the DC voltage ID is applied to the region 61, electrons are always filled up to the energy level ID. When the pulse voltage IG1 or IG2 is at a high level, the potential of the channel region under each gate electrode is higher than the potential of the n ⁺ region 61 (hereinafter referred to as ON state), and conversely, the pulse voltage IG1 or IG2 is at a low level. At this time, the potential of the channel region under each gate electrode becomes lower than the potential of the n ⁺ region 61 (hereinafter, referred to as OFF state), so that ID and IG respectively.
1. Choose the level of IG2.

The input voltage IN is below the gate electrode 70.
The channel region potential is n ⁺Higher than area 61
Channel region when IG1 or IG2 is ON
It fluctuates in a range that is lower than the potential of
Choose

Since the potential of the n region 66 is higher than that of the surrounding p type region, it changes stepwise so that the potential well of the n region 66 becomes deep at the boundary between the n region 66 and the p type region. Since the gate electrode 70 is arranged in the n region 66 so as to slightly overlap with each other, the overlapping channel region forms a potential well having a depth different from that of the channel region below the gate electrode 71. This potential well is not necessary for the operation of the charge transfer device, but it is difficult to completely align one end of the gate electrode 70 with the boundary between the n region 66 and the p-type region for manufacturing.
It is caused by arranging the region 66 and the gate electrode 70 so as to slightly overlap each other.

The channel regions under the gate electrodes 71 and 72 form deep potential wells (hereinafter referred to as storage regions) in the n regions 66 and 62, and the p-type region portion sandwiched between the n regions 66 and 62. Then, the potential becomes low and a potential barrier (hereinafter referred to as a barrier region) is formed for the electrons. Thus, the channel regions under the gate electrodes 71 and 72 form a convex potential well, and the potential well moves up and down while maintaining the convex shape in accordance with the change of the pulse voltage IG2.

Since the potentials of the n ⁻ regions 63, 64 and 65 are lower than the potentials of the surrounding n regions, the potential at the boundary between the n ⁻ regions and the n regions is the potential well of the n region 62 as shown in the figure. It changes like a staircase to become deeper. Therefore, the n region portion sandwiched between the n ⁻ regions forms an electron storage region.

A method of transferring electrons will be described below with reference to FIGS. 3 and 9. 9A to 9G show how the potential diagram corresponding to each phase in FIG. 3 changes.
Here, the potential well in the overlapping portion between the n region 66 and the gate electrode 70 is not necessary for operation and is therefore omitted.

FIG. 9A shows the potential of the channel region at the phase P1 of FIG. Pulse voltage IG1 is O
Due to the FF state, the electrons in the n ⁺ region 61 are not injected into the channel region.

FIG. 9B shows the potential of the channel region at the phase P2 of FIG. Pulse voltage IG1 is O
Because of the N state, the electrons in the n ⁺ region 61 are
Implanted in the lower channel region. At this time, the gate electrode 7
Electrons are also accumulated in the storage area below.

FIG. 9C shows the potential of the channel region at the phase P3 of FIG. The pulse voltage IG1 is turned off again, and electrons are accumulated in the channel region under the gate electrode 70 and the storage region under the gate electrode 71 separately from the n ⁺ region 61. At this time, the gate electrode 70
The amount of charge accumulated in the lower channel region is the amount of charge corresponding to the input voltage IN based on the DC voltage ID. This charge amount is the sum of the unnecessary charge Q1 in the nonlinear region shown in FIG. 11A and the signal charge Q (t) proportional to the input voltage IN.

The amount of charge accumulated in the storage region under the gate electrode 71 is constant regardless of the input voltage IN and is determined by the potential difference between the n ⁺ region 61 and the storage region under the gate electrode 71 and the area of this storage region. It is a value (this charge amount is Q _OFF ).

FIG. 9D shows the potential of the channel region at the phase P4 of FIG. Pulse voltage IG2 is O
The N state is set, and the convex potential well below the gate electrodes 71 and 72 becomes deep. Therefore, the charges accumulated in the channel region under the gate electrode 70 and the storage region under the gate electrode 71 first fill the storage region under the gate electrode 71. The accumulation of electrons causes the internal potential of this storage region to gradually decrease.

After the internal potential of this storage region becomes lower than the internal potential of the barrier region below the gate electrode 71, the electrons are transferred to the storage region below the gate electrode 72. At this time, the amount of charge accumulated in the storage region under the gate electrode 71 is uniquely determined by the potential difference of the internal potential between the storage region under the gate electrode 71 and the barrier region and the area of the storage region (this amount of charge is and Q _ON).

FIG. 9E shows the potential of the channel region at the phase P6 of FIG. Pulse voltage IG2 is O
In the FF state, some of the electrons accumulated under the gate electrode 71 are returned to the channel region under the gate electrode 70. At the same time, the pulse voltage H1 becomes high level, and the electrons accumulated in the storage region under the gate electrode 72 are
The data is transferred to the storage region below the gate electrode 74 deeper in the potential well.

The electrons transferred to the storage region under the gate electrode 74 are sequentially transferred to the right in the figure every time the pulse voltages H1 and H2 are inverted. This transferred charge amount is
Equal to Q1 + Q (t) + Q OFF -Q ON. Therefore, Q1
By selecting the potential difference between the internal potential of the storage region and the internal potential of the barrier region and the DC voltage ID such that + Q _OFF = Q _ON , only the charge amount Q (t) proportional to the input voltage IN is transferred to the charge transfer path. Can be supplied.

FIG. 9F shows the potential of the channel region at the phase P7 of FIG. As in the state of FIG. 9B, since the pulse voltage IG1 is in the ON state, the n ⁺ region 6
The electrons in 1 are injected into the channel region under the gate electrode 70 and the storage region under the gate electrode 71. That is, the constant amount of charge Q _ON accumulated under the gate electrode 71 in the state of FIG. 9D is equivalent to being returned to the n ⁺ region 61.

FIG. 9G shows the potential of the channel region at the phase P8 of FIG. Similar to the state of FIG. 9C, the pulse voltage IG1 is turned off again, and electrons are generated in the channel region under the gate electrode 70 and the gate electrode 71.
It is stored separately from the n ⁺ region 61 in the lower storage region. At this time, the amount of charges separately stored is Q1 + Q (t).
+ Q _OFF . That is, the sum of the charge amount Q (t) proportional to the input voltage IN at this point and the constant charge amount Q1 + Q _OFF, which is the same as in the case of FIG. 9C, is obtained.

After that, the same state as in FIG.
Only the charge amount proportional to the input voltage IN is 1 of the pulse voltage.
It is supplied to the charge transfer path every cycle. In the third embodiment, the unnecessary charges are returned to the electron supply source without extracting the unnecessary charges in the direction different from the charge transfer direction as in the first or second embodiment. Therefore, the charge transfer path for extracting the unnecessary charges is used. And it is not necessary to provide a drain.

As described above, the first, second and third
In both of the above embodiments, it is possible to supply only the charge amount proportional to the input voltage without supplying unnecessary charges to the charge transfer mechanism in the subsequent stage among the charge amounts converted by the voltage-charge conversion mechanism. Therefore, the maximum transfer charge amount of the charge transfer mechanism can be effectively used. In general, the charge transfer mechanism occupies a much larger proportion on the chip than the voltage-charge conversion mechanism portion. Therefore, not supplying unnecessary charges to the charge transfer mechanism is effective in reducing the chip area.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0112]

As described above, according to the charge transfer device of the present invention, it is possible to expand the signal dynamic range while ensuring the linearity without expanding the chip area.

If the signal dynamic range is the same, the chip area of the charge transfer mechanism can be reduced, and the chip size and power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of a charge transfer device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a charge transfer device according to a first embodiment of the present invention and a potential diagram of a channel region.

FIG. 3 is a timing diagram of pulse signals and input signals for operating the charge transfer device according to the embodiment.

FIG. 4 is a potential diagram for explaining the operation of the charge transfer device according to the first embodiment of the present invention.

FIG. 5 is a plan view of a charge transfer device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a charge transfer device according to a second embodiment of the present invention and a potential diagram of a channel region.

FIG. 7 is a potential diagram for explaining the operation of the charge transfer device according to the second embodiment of the present invention.

FIG. 8 is a plan view, a cross-sectional view, and a potential diagram of a channel region of a charge transfer device according to a third embodiment of the present invention.

FIG. 9 is a potential diagram for explaining the operation of the charge transfer device according to the third embodiment of the present invention.

FIG. 10 is a cross-sectional view of a charge transfer device according to a conventional example and a potential diagram of a channel region.

FIG. 11 is a graph showing a relationship between an input voltage-converted charge amount and an input voltage-input differential capacity according to a conventional charge transfer device.

[Explanation of symbols]

1, 23, 31, 39, 61, 101 n ⁺ regions 2, 32, 62, 66, 102 n regions 3, 4, 5, 6, 21, 22, 33, 34, 35, 3
6, 37, 38, 63, 64, 65, 103, 104
n ^- region 7, 40, 67, 100 p substrate 8, 56, 68, 113 input diode 9, 10, 11, 12, 13, 14, 15, 16, 1
7, 18, 19, 20, 41, 42, 43, 44, 4
5, 46, 47, 48, 49, 50, 51, 52, 5
3, 54, 55, 69, 70, 71, 72, 73, 7
4, 75, 76, 77, 78, 105, 106, 10
7, 108, 109, 110, 111, 112 Gate electrodes 24, 25, 26 Charge transfer path

Claims (5)

[Claims] 1. A charge transfer method for converting an input voltage into a charge amount for each cycle of a periodic pulse signal and transferring the converted charges along a transfer path, wherein: A charge transfer method, wherein a fixed amount of electric charge is weighed from the converted electric charge, and the remaining electric charge obtained by removing the fixed amount of electric charge from the converted electric charge is transferred. 2. The charge transfer method according to claim 1, wherein the fixed amount of charges is separated from the remaining charges, transferred in a direction different from the transfer path, and discarded. 3. A voltage-charge conversion means for converting an input voltage into a charge amount for each cycle of a periodic pulse signal, and a plurality of regions capable of accumulating charges, and transferring the charges by the pulse signal. In the charge transfer device having a charge transfer unit for storing a predetermined amount of charge, the first storage region provided on the input side of the charge transfer unit for storing a certain amount of charge, and the charge overflowing from the first storage region. A second storage area for accumulating and transferring to the charge transfer means, and a certain amount of charge accumulated in the first storage area for each cycle of the pulse signal, and another charge to be transferred A charge transfer device having transfer means. 4. A voltage-charge conversion means for converting an input voltage into an electric charge amount for each cycle of a periodic pulse signal, and a plurality of regions capable of accumulating the electric charge, and transferring the electric charge by the pulse signal. A charge transfer device having a charge transfer means for storing a charge converted by the voltage-charge conversion means, the charge transfer device being provided adjacent to the charge transfer means.
Storage region of the third storage region, and a fourth storage region provided between the third storage region and the charge transfer means for accumulating the charge overflowing from the third storage region for each cycle of the pulse signal. A charge transfer device comprising: a storage area; and another charge transfer means for transferring the electric charge remaining in the third storage area for each cycle of the pulse signal. 5. The charge transfer device according to claim 3, wherein a drain for absorbing the transferred charges is provided at the end of the other charge transfer means.