JPH07222438A - Synchronous-rectification dc-dc converter - Google Patents

Synchronous-rectification dc-dc converter

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Publication number
JPH07222438A
JPH07222438A JP6010726A JP1072694A JPH07222438A JP H07222438 A JPH07222438 A JP H07222438A JP 6010726 A JP6010726 A JP 6010726A JP 1072694 A JP1072694 A JP 1072694A JP H07222438 A JPH07222438 A JP H07222438A
Authority
JP
Japan
Prior art keywords
load
heavy
light
converter
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6010726A
Other languages
Japanese (ja)
Inventor
Tokuyuki Henmi
徳幸 逸見
Yoshiya Akanuma
慶也 赤沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP6010726A priority Critical patent/JPH07222438A/en
Publication of JPH07222438A publication Critical patent/JPH07222438A/en
Pending legal-status Critical Current

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  • Direct Current Feeding And Distribution (AREA)
  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To obtain the synchronous-rectification DC-DC converter in which, when a load is short-circuited in a heavy load mode, a current for a light load rises immediately with the restoration of the load by a method wherein, when a synchronous rectifying element is set to continuity in the heavy load mode, a main switching element for a light load is turned off and a light-load control circuit having an overcurrent drooping characteristic is operated irrespective of the heavy load mode or a light load mode. CONSTITUTION:In a heavy load mode, a light-load control circuit 122 is utilized, a FET 5 is operated, a heavy-load control circuit 121 controls FETs 3, 4 so as to be turned on and off in such a way that a load voltage detected by resistances 9, 10 is kept at a prescribed value. At this time, the FET 5 is turned off during the ON- period of the FET 4 by an interlock circuit 123. When a load 11 is short-circuited in the heavy load mode, an overcurrent protective circuit 124 cuts off a power supply for the heavy-load control circuit 121 due to the voltage rise of a load-current detection resistance 13, and it turns off the FETs 3, 4. At this time, an overcurrent drooping circuit inside the light-load control circuit 122 functions, and a load current is limited to a prescribed current. As soon as the load 11 is restored, the light-load control circuit 122 is returned to an operation in a normal state.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電圧が変動するDC電源
から定電圧のDC電源を作り出す、いわゆるDCチョッ
パと呼ばれるDC−DCコンバータであって、特にDC
出力平滑用のリアクトルとコンデンサを共通にした2つ
のDCチョッパ、即ち転流ダイオードと主スイッチ素子
を持つ軽負荷用のDCチョッパ、および転流ダイオード
に並列の転流用のスイッチ素子(同期整流素子)と前記
の主スイッチ素子とは別の主スイッチ素子を持ち、この
新たな2つのスイッチ素子を同期して互いに反転側にオ
ン/オフする同期整流式の重負荷用のDCチョッパを備
えた同期整流DC−DCコンバータに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter called a DC chopper, which produces a constant voltage DC power supply from a DC power supply whose voltage fluctuates.
Two DC choppers with a common output smoothing reactor and capacitor, namely a light load DC chopper with a commutation diode and a main switch element, and a commutation switch element (synchronous rectification element) in parallel with the commutation diode. And a main switch element different from the above main switch element, and the synchronous rectification is provided with a DC hopper for heavy load of a synchronous rectification, which turns on / off the two new switch elements in synchronization with each other. The present invention relates to a DC-DC converter.

【0002】なお、以下各図において同一の符号は同一
もしくは相当部分を示す。
In the following drawings, the same reference numerals indicate the same or corresponding parts.

【0003】[0003]

【従来の技術】図2は従来のこの種の同期整流DC−D
Cコンバータ(DCチョッパ)の構成例を示す。同図に
おいて1は電圧の変動する直流電源、2は電源電圧の脈
動を抑える電解コンデンサ、3は重負荷モード時の主ス
イッチ素子としてのNチャネルFET、4は重負荷モー
ド時の転流ダイオードに代わるスイッチ素子(同期整流
素子という)としてのnチャネルFET、5は軽負荷モ
ード時の主スイッチ素子としてのPチャネルFET、6
は軽負荷モード時に動作する転流ダイオード(フライホ
イルダイオードともいう)、7は出力電流平滑用のリア
クトル、8は出力電圧平滑用の電解コンデンサ、9,1
0は出力電圧検出用の分圧抵抗、11は負荷である。ま
た12Lは抵抗9,10を介して出力電圧を検出し、こ
の出力電圧を一定とするように比較的長い定周期でFE
T5をオン/オフする軽負荷制御部、12Hは同じく出
力電圧を検出しこの出力電圧を一定とするように比較的
短い定周期でFET3,4をオン/オフする重負荷制御
部である。
2. Description of the Related Art FIG. 2 shows a conventional synchronous rectification DC-D of this type.
The structural example of a C converter (DC chopper) is shown. In the figure, 1 is a DC power supply whose voltage fluctuates, 2 is an electrolytic capacitor that suppresses the pulsation of the power supply voltage, 3 is an N-channel FET as a main switching element in the heavy load mode, 4 is a commutation diode in the heavy load mode. N-channel FET as an alternative switch element (referred to as a synchronous rectifying element), 5 is a P-channel FET as a main switch element in the light load mode, 6
Is a commutation diode (also called a flywheel diode) that operates in the light load mode, 7 is a reactor for smoothing the output current, 8 is an electrolytic capacitor for smoothing the output voltage, and 9, 1
Reference numeral 0 is a voltage dividing resistor for detecting the output voltage, and 11 is a load. Further, 12L detects the output voltage through the resistors 9 and 10, and the FE is fixed at a relatively long fixed period so as to keep the output voltage constant.
A light load control unit for turning on / off T5, and a heavy load control unit 12H for detecting the output voltage and turning on / off the FETs 3 and 4 in a relatively short fixed period so as to keep the output voltage constant.

【0004】この例では、重負荷モードとはポータブル
機器などの動作モードをいい、軽負荷モードとは同じく
待機モードをいう。この待機モードではDC出力は液晶
パネルの表示やメモリ保持等の微小負荷のみに供給され
る。そして重負荷モード,軽負荷モードの別は外部で判
別され、図2では外部信号によって軽負荷制御部12L
と重負荷制御部12Hの動作が切換えられる。
In this example, the heavy load mode refers to the operation mode of portable equipment and the like, and the light load mode refers to the standby mode. In this standby mode, the DC output is supplied only to a minute load such as display on the liquid crystal panel or memory retention. Then, the heavy load mode and the light load mode are discriminated externally, and in FIG.
And the operation of the heavy load control unit 12H is switched.

【0005】軽負荷モードでは重負荷制御部12Hの電
源は切られたまま、軽負荷制御部12Lのみが生かされ
る。従ってFET3,FET4は常時オフで、FET5
が軽負荷制御部12Lによって所定周期でオン/オフさ
れる。そしてFET5のオフ時にはリアクトル7の電流
は転流ダイオード6によって維持される。周知のように
FET5の出力電圧は次式(1)または(1a)で表さ
れる。
In the light load mode, the light load control unit 12H is powered off while only the light load control unit 12L is used. Therefore, FET3 and FET4 are always off, and FET5
Is turned on / off at a predetermined cycle by the light load control unit 12L. When the FET 5 is off, the current in the reactor 7 is maintained by the commutation diode 6. As is well known, the output voltage of the FET 5 is represented by the following equation (1) or (1a).

【0006】[0006]

【数1】 出力電圧(平均値)=(入力電圧)×(オン時間)/(周期)・・・(1) =(入力電圧)×(オン比率) ・・・(1a) なおこの例では入力電圧は電源1の電圧であり、オン時
間はFET5のオン/オフの1周期中におけるオン時間
である。軽負荷制御部12Lは抵抗9,10を介し負荷
11の電圧を検出し、この値を所定値に保つようFET
5のオン比率を制御する。この例ではFET5の開閉周
期は比較的長く,オン比率は比較的小さい。
## EQU1 ## Output voltage (average value) = (input voltage) × (on time) / (cycle) ... (1) = (input voltage) × (on ratio) ... (1a) In this example, The input voltage is the voltage of the power source 1, and the on-time is the on-time in one cycle of turning on / off the FET 5. The light load control unit 12L detects the voltage of the load 11 via the resistors 9 and 10 and FET so as to keep this value at a predetermined value.
Control the ON ratio of 5. In this example, the open / close cycle of the FET 5 is relatively long and the ON ratio is relatively small.

【0007】一方、重負荷モードでは軽負荷制御部12
Lの電源は切られ、重負荷制御部12Hのみが生かされ
る。従って、FET5は常時オフで、FET3とFET
4が所定周期で交互にオン(つまりFET3のオン時に
はFET4がオフ、FET3のオフ時にはFET4がオ
ン)される。つまりFET4は転流ダイオード6と並列
になって転流ダイオードの役割を果たす。この理由は転
流ダイオード6の順電圧降下VFが大きく、重負荷時に
はこの損夫が無視できないので、電圧降下の小さいFE
T4に転流電流を流しDCチョッパの効率を高めるため
である。このようにFET4はFET3のオン/オフに
同期して夫々オン/オフされるのでこのDCチョッパは
同期整流式DCチョッパと呼ばれる。
On the other hand, in the heavy load mode, the light load control unit 12
The power of L is turned off, and only the heavy load control unit 12H is used. Therefore, FET5 is always off, and FET3 and FET
4 are alternately turned on in a predetermined cycle (that is, the FET 4 is turned off when the FET 3 is turned on, and the FET 4 is turned on when the FET 3 is turned off). That is, the FET 4 serves as a commutation diode in parallel with the commutation diode 6. The reason for this is that the forward voltage drop VF of the commutation diode 6 is large and this loss cannot be ignored under heavy load, so FE with a small voltage drop is used.
This is because a commutation current is passed through T4 to improve the efficiency of the DC chopper. In this way, the FET 4 is turned on / off in synchronism with the turning on / off of the FET 3, and this DC chopper is called a synchronous rectification type DC chopper.

【0008】この重負荷モードでもFET3の出力電圧
は前記(1)式で表される。そして重負荷制御部12H
は抵抗9,10を介し負荷11の電圧を検出し、この値
を所定値に保つようにFET3のオン比率を制御し、こ
のFET3に同期してFET4をオン/オフする。ここ
でFET3がオン、FET4がオフすると、リアクトル
7を介し出力へ電流が流れる。ただしリアクトル7によ
り電流は徐々に増加する。次にFET3がオフ、FET
4がオンすると、リアクトル7に蓄えられたエネルギー
は負荷11とFET4を通し流れ、電流は徐々に減少す
る。この例では、重負荷モードではFET3,4の開閉
周期に比較的短かく、FET3のオン比率は比較的大き
い。
Even in this heavy load mode, the output voltage of the FET 3 is expressed by the above equation (1). And the heavy load control unit 12H
Detects the voltage of the load 11 via the resistors 9 and 10, controls the ON ratio of the FET 3 to keep this value at a predetermined value, and turns the FET 4 ON / OFF in synchronization with the FET 3. When the FET 3 is turned on and the FET 4 is turned off here, a current flows to the output through the reactor 7. However, the current gradually increases due to the reactor 7. Next, FET3 is off, FET
When 4 is turned on, the energy stored in the reactor 7 flows through the load 11 and the FET 4, and the current gradually decreases. In this example, the open / close cycle of the FETs 3 and 4 is relatively short in the heavy load mode, and the ON ratio of the FET 3 is relatively large.

【0009】[0009]

【発明が解決しようとする課題】ところで、図2の回路
では外部からの信号入力により軽負荷モード時と重負荷
モード時とで制御部12Lと12Hを完全に切り換えて
いるため、重負荷モード時に瞬時の負荷短絡により、短
絡保護が働くと、重負荷制御部12Hの電源が落とさ
れ、次にバックアップのため軽負荷用DC値を利用しよ
うとしても軽負荷制御部12Lの電源は切られているの
で、負荷短絡が解除されていても、電源を再起動させな
いと出力が出ないため回復に時間が掛かり、DC−DC
コンバータの用途によってはこの図2の方式が使用でき
ないことがあった。そこで本発明はこの問題を解消でき
る同期整流DC−DCコンバータを提供することを課題
とする。
By the way, in the circuit of FIG. 2, since the control sections 12L and 12H are completely switched between the light load mode and the heavy load mode by the signal input from the outside, in the heavy load mode. When the short circuit protection is activated due to an instantaneous load short circuit, the heavy load control unit 12H is powered off, and then the light load control unit 12L is powered off even if the light load DC value is used for backup. Therefore, even if the load short circuit is released, it takes time to recover because the output is not output unless the power supply is restarted.
The method of FIG. 2 may not be used depending on the application of the converter. Therefore, an object of the present invention is to provide a synchronous rectification DC-DC converter that can solve this problem.

【0010】[0010]

【課題を解決するための手段】前記の課題を解決するた
めに、請求項1の同期整流DC−DCコンバータは、平
滑リアクトル(7など)と負荷(11など)との直列回
路に直列に、負荷へ給電する極性に設けた第1のスイッ
チ素子(軽負荷用主スイッチ素子5など)を介して直流
電源(1など)を接続し、負荷と並列に平滑コンデンサ
(8など)を接続し、前記平滑リアクトルと負荷との直
列回路に並列に、平滑リアクトルの電流を維持する極性
にダイオード(転流ダイオード6など)を接続し、第1
のスイッチ素子と並列に同じ通電極性に第2のスイッチ
素子(重負荷用主スイッチ素子3など)を接続し、かつ
前記ダイオードと並列に同じ通電極性に第3のスイッチ
素子(重負荷用同期整流素子4など)を接続してなり、
負荷の電圧を検出する手段(抵抗9,10など)、前記
電圧検出手段によって検出された負荷電圧を所定値に保
つように、第1の所定周期で第1のスイッチ素子をオン
/オフ駆動制御する第1の制御手段(軽負荷制御回路1
22など)、前記電圧検出手段によって検出された負荷
電圧を所定値に保つように、第2の所定周期で第2およ
び第3のスイッチ素子を、前者をオンするときは後者を
オフに、前者をオフするときは後者をオンに、同期して
オン/オフ駆動制御する第2の制御手段(重負荷制御回
路121など)を備えた同期整流DC−DCコンバータ
において、軽負荷モード,重負荷モードの別を指定する
外部信号に基づいて、軽負荷モードでは第1の制御手段
を作動させ、重負荷モードでは第1および第2の制御手
段を作動させる手段(制御部120など)と、第2の制
御手段が第3のスイッチ素子をオンする期間、第1の制
御手段が第1のスイッチ素子をオンする信号を無効化す
る手段(インタロック回路123など)とを備えたもの
とする。
In order to solve the above-mentioned problems, the synchronous rectification DC-DC converter according to claim 1 is connected in series with a series circuit of a smoothing reactor (7 etc.) and a load (11 etc.). A DC power source (1 or the like) is connected through a first switch element (such as a light load main switch element 5) provided in a polarity for supplying power to a load, and a smoothing capacitor (8 or the like) is connected in parallel with the load, A diode (commutation diode 6 or the like) is connected in parallel to the series circuit of the smoothing reactor and the load so as to maintain the current of the smoothing reactor, and
The second switch element (main switch element 3 for heavy load, etc.) is connected in parallel with the same switch polarity as the above switch element, and the third switch element (for heavy load) is connected in parallel with the diode and has the same switch polarity. Synchronous rectifier 4 etc.) is connected,
A means for detecting a load voltage (resistors 9, 10, etc.), and an ON / OFF drive control for the first switch element at a first predetermined cycle so as to keep the load voltage detected by the voltage detecting means at a predetermined value. First control means (light load control circuit 1
22), so that the load voltage detected by the voltage detecting means is kept at a predetermined value, the second and third switch elements are turned on in the second predetermined cycle, the latter is turned off when the former is turned on, and the former is turned on. In the synchronous rectification DC-DC converter including the second control means (the heavy load control circuit 121 and the like) for synchronously performing ON / OFF drive control when turning off the latter, the light load mode and the heavy load mode Based on an external signal that specifies whether the first control means is activated in the light load mode and the first and second control means are activated in the heavy load mode (control section 120 or the like), and the second control means. It is assumed that the first control means invalidates a signal for turning on the first switch element while the third control element turns on the third switch element (interlock circuit 123 or the like).

【0011】また、請求項2の同期整流DC−DCコン
バータは、請求項1に記載の同期整流DC−DCコンバ
ータにおいて、負荷の電流を検出する手段(負荷電流検
出抵抗13など)と、重負荷モードにおいてこの電流検
出手段によって検出された負荷電流が所定値を越えたと
きは少なくとも第2の制御手段から第2,第3のスイッ
チ素子に与えられるオン信号を無効化する手段(過電流
保護回路124など)とを備えたものとする。
A synchronous rectification DC-DC converter according to a second aspect of the present invention is the synchronous rectification DC-DC converter according to the first aspect, wherein a means for detecting a load current (load current detection resistor 13, etc.) and a heavy load. In the mode, when the load current detected by the current detection means exceeds a predetermined value, at least means for invalidating the ON signal given to the second and third switch elements from the second control means (overcurrent protection circuit And the like) and the like.

【0012】また請求項3の同期整流DC−DCコンバ
ータでは、請求項2記載の同期整流DC−DCコンバー
タにおいて、前記オン信号の無効化手段は第2の制御手
段の電源をしゃ断するものであるようにする。また請求
項4の同期整流DC−DCコンバータでは、請求項2ま
たは3に記載の同期整流DC−DCコンバータにおい
て、第1の制御手段は前記負荷電流が所定値を越えたと
きは、第1のスイッチ素子のオン比率を下げ負荷電流を
垂下させる手段(過電流垂下回路など)を備えたもので
あるようにする。
Further, in the synchronous rectification DC-DC converter according to claim 3, in the synchronous rectification DC-DC converter according to claim 2, the invalidating means of the ON signal cuts off the power supply of the second control means. To do so. Further, in the synchronous rectification DC-DC converter according to claim 4, in the synchronous rectification DC-DC converter according to claim 2 or 3, the first control means controls the first control circuit when the load current exceeds a predetermined value. A means for lowering the ON ratio of the switch element to droop the load current (such as an overcurrent drooping circuit) is provided.

【0013】[0013]

【作用】重負荷用スイッチング回路の短絡保護は重負荷
制御回路の電源をラッチ動作で落とすのに対して、軽負
荷用スイッチング回路の短絡保護は軽負荷制御回路の電
源を落とさず、この軽負荷制御回路内の過電流垂下回路
で電流を制限する。そして重負荷用スイッチング回路が
動作している時も、軽負荷用スイッチング回路を常にに
動作させておき、但し重負荷用の同期整流素子(つまり
FET4)がオン期間のタイミングには強制的に軽負荷
用の主スイッチ素子(つまりFET5)はオフする様に
インタロックをかける。
[Function] While the short circuit protection of the heavy load switching circuit turns off the power supply of the heavy load control circuit by the latch operation, the short circuit protection of the light load switching circuit does not turn off the power supply of the light load control circuit. The current is limited by the overcurrent droop circuit in the control circuit. Even when the heavy load switching circuit is operating, the light load switching circuit is always operated, but the heavy load synchronous rectifying element (that is, the FET 4) is forcibly lightened at the timing of the ON period. The main switch element for load (that is, FET 5) is interlocked so as to be turned off.

【0014】これにより重負荷モードの時に負荷が瞬時
ショートを起こして、短絡保護が働いて重負荷用スイッ
チング回路が停止してしまっても、瞬時に軽負荷用の回
路が働きスイッチングを開始するため、バッアップに必
要な電力は供給できる。また、同期整流素子FET4が
オンの時は、軽負荷用主スイッチ素子FET5がオンす
ることがないため、入力−グランド間の短絡電流が流れ
ることがない。
As a result, even if the load causes a momentary short circuit in the heavy load mode and the short circuit protection works to stop the heavy load switching circuit, the light load circuit immediately starts switching. , The power required for the backup can be supplied. Further, when the synchronous rectifying element FET4 is turned on, the light load main switching element FET5 does not turn on, so that a short-circuit current between the input and the ground does not flow.

【0015】[0015]

【実施例】図1は本発明の一実施例としての回路構成を
示し、この図は図2に対応する。図1において13は負
荷電流検出抵抗、120は新たな制御部である。また制
御部120内において、121はFET3,4おオン/
オフを制御する重負荷制御回路、122はFET5のオ
ン/オフを制御する軽負荷制御回路、123は後述のイ
ンタロック回路、124は同じく後述の過電流保護回路
である。なお出力電圧検出用分圧抵抗9,10の検出電
圧は重負荷制御回路121および軽負荷制御回路122
に入力される。また負荷電流検出抵抗13の検出電圧は
過電流保護回路124および軽負荷制御回路に入力され
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit configuration as an embodiment of the present invention, and this figure corresponds to FIG. In FIG. 1, 13 is a load current detection resistor, and 120 is a new control unit. In the control unit 120, a FET 121 turns on FETs 3 and 4 /
A heavy load control circuit for controlling OFF, a light load control circuit for controlling ON / OFF of the FET 5, a reference numeral 123 for an interlock circuit described later, and a reference numeral 124 for an overcurrent protection circuit also described later. The detection voltage of the voltage dividing resistors 9 and 10 for detecting the output voltage is the heavy load control circuit 121 and the light load control circuit 122.
Entered in. The detection voltage of the load current detection resistor 13 is input to the overcurrent protection circuit 124 and the light load control circuit.

【0016】軽負荷モードでは重負荷制御回路121の
電源は外部信号によって切られ、FET3,4はオンす
る信号が無く、オフに保たれる。他方、軽負荷制御回路
122は生かされ、抵抗9,10によって検出された負
荷11の電圧を所定値に保つようにFET5を所定周波
数でオン/オフ制御する。次に重負荷モードでは外部信
号によって軽負荷制御回路122は生かされたまま、し
たがってFET5は動作のまま重負荷制御回路121の
電源が生かされる。そこで重負荷制御回路121は抵抗
9,10によって検出された負荷電圧を所定値に保つよ
う同期整流方式で、この例ではFET5とは異なる所定
周波数でFET3,4をオン/オフ制御する。ここでイ
ンタロック回路123は重負荷制御回路121によるF
ET4のオンのタイミングを検出し、FET4のオン期
間中、軽負荷制御回路122からのFET5のオン信号
を無効として強制的にFET5をオフするようにインタ
ロックを行い、電源短絡を防ぐ。
In the light load mode, the power source of the heavy load control circuit 121 is turned off by an external signal, and the FETs 3 and 4 are kept off because there is no signal to turn them on. On the other hand, the light load control circuit 122 is utilized to control the FET 5 on / off at a predetermined frequency so as to keep the voltage of the load 11 detected by the resistors 9 and 10 at a predetermined value. Next, in the heavy load mode, the light load control circuit 122 is kept alive by the external signal, so that the FET 5 is kept operating and the power source of the heavy load control circuit 121 is kept alive. Therefore, the heavy load control circuit 121 uses a synchronous rectification method to keep the load voltage detected by the resistors 9 and 10 at a predetermined value, and in this example, turns on / off the FETs 3 and 4 at a predetermined frequency different from that of the FET 5. Here, the interlock circuit 123 is the F by the heavy load control circuit 121.
The timing of turning on the ET4 is detected, and during the ON period of the FET4, the ON signal of the FET5 from the light load control circuit 122 is invalidated and interlocked so as to forcibly turn off the FET5, thereby preventing a power supply short circuit.

【0017】なおこの重負荷モードでは。NチャネルF
ET3のオン時にPチャネルFET5がオフするタイミ
ングと、オンするタイミングとが存在する。後者のタイ
ミングつまりFET3,5が共にオンする場合、Nチャ
ネルFET3のオン抵抗がPチャネルFET5のオン抵
抗より低く、電流はNチャネルFET3を流れるためF
ET5のオン影響は表れない。
In this heavy load mode. N channel F
There is a timing at which the P-channel FET 5 is turned off and a timing at which it is turned on when the ET3 is turned on. In the latter timing, that is, when the FETs 3 and 5 are both turned on, the on-resistance of the N-channel FET 3 is lower than the on-resistance of the P-channel FET 5, and the current flows through the N-channel FET 3 so that F
The on-effect of ET5 does not appear.

【0018】この重負荷モードで負荷11が短絡する
と、制御部120内の過電流保護回路124は、負荷電
流検出抵抗13の電圧が所定値を越えたことからこの短
絡を知り、重負荷制御回路121の電源を切ってFET
3,4をオフする。しかし軽負荷制御回路122はその
まま生かされる。但しこのとき軽負荷制御回路122に
も負荷電流検出抵抗13の電圧が入力されているので、
この軽負荷制御回路122内の図外の過電流垂下回路が
働き、FET5のオン比率を下げ出力電圧下降(垂下)
させて負荷電流を所定値に制限する。しかし負荷が復帰
すると直ちに軽負荷制御回路122は正常時の動作に戻
り、出力電圧を復帰する。
When the load 11 is short-circuited in this heavy load mode, the overcurrent protection circuit 124 in the control unit 120 knows this short circuit because the voltage of the load current detection resistor 13 exceeds a predetermined value, and the heavy load control circuit Turn off the power of 121 and turn off the FET
Turn off 3 and 4. However, the light load control circuit 122 is used as it is. However, at this time, since the voltage of the load current detection resistor 13 is also input to the light load control circuit 122,
An overcurrent drooping circuit (not shown) in the light load control circuit 122 operates to lower the ON ratio of the FET 5 and lower the output voltage (droop).
Then, the load current is limited to a predetermined value. However, as soon as the load is restored, the light load control circuit 122 returns to the normal operation and restores the output voltage.

【0019】[0019]

【発明の効果】本発明によれば、重負荷モードで同期整
流素子FET4の導通時のみ、軽負荷用主スイッチ素子
FET5をインタロック回路123を介し強制的にオフ
するのみで、重負荷モード,軽負荷モードにかからわず
過電流垂下回路を持つ軽負荷制御回路122を生かすよ
うにしたので、重負荷モードの負荷短絡時に、過電流保
護回路124によって重負荷制御回路121の電源が切
られても、負荷回復と共に直ちに軽負荷用の出力電源が
立上がり、バックアップに必要な電力を供給することが
できる。
According to the present invention, in the heavy load mode, only when the synchronous rectifying element FET4 is conductive, the light load main switch element FET5 is forcibly turned off through the interlock circuit 123. Since the light load control circuit 122 having the overcurrent drooping circuit is utilized regardless of the light load mode, the power supply of the heavy load control circuit 121 is turned off by the overcurrent protection circuit 124 when the load is short-circuited in the heavy load mode. Even if the load is restored, the output power supply for the light load immediately rises, and the power required for backup can be supplied.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例としての回路図FIG. 1 is a circuit diagram as an embodiment of the present invention.

【図2】図1に対応する従来の回路図FIG. 2 is a conventional circuit diagram corresponding to FIG.

【符号の説明】[Explanation of symbols]

1 直流電源 2 電解コンデンサ 3 重負荷用主スイッチ素子(NチャネルFET) 4 重負荷用同期整流素子(nチャネルFET) 5 軽負荷用主スイッチ素子(PチャネルFET) 6 転流ダイオード 7 平滑リアクトル 8 平滑コンデンサ 9,10 出力電圧検出用分圧抵抗 11 負荷 13 負荷電流検出抵抗 120 制御部 121 重負荷制御回路 122 軽負荷制御回路 123 インタロック回路 124 過電流保護回路 1 DC power supply 2 Electrolytic capacitor 3 Main switch element for heavy load (N channel FET) 4 Synchronous rectifying element for heavy load (n channel FET) 5 Main switch element for light load (P channel FET) 6 Commutation diode 7 Smoothing reactor 8 Smoothing capacitor 9,10 Output voltage detection voltage dividing resistor 11 Load 13 Load current detection resistor 120 Control unit 121 Heavy load control circuit 122 Light load control circuit 123 Interlock circuit 124 Overcurrent protection circuit

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】平滑リアクトルと負荷との直列回路に直列
に、負荷へ給電する極性に設けた第1のスイッチ素子を
介して直流電源を接続し、 負荷と並列に平滑コンデンサを接続し、 前記平滑リアクトルと負荷との直列回路に並列に、平滑
リアクトルの電流を維持する極性にダイオードを接続
し、 第1のスイッチ素子と並列に同じ通電極性に第2のスイ
ッチ素子を接続し、かつ前記ダイオードと並列に同じ通
電極性に第3のスイッチ素子を接続してなり、 負荷の電圧を検出する手段、 前記電圧検出手段によって検出された負荷電圧を所定値
に保つように、第1の所定周期で第1のスイッチ素子を
オン/オフ駆動制御する第1の制御手段、 前記電圧検出手段によって検出された負荷電圧を所定値
に保つように、第2の所定周期で第2および第3のスイ
ッチ素子を、前者をオンするときは後者をオフに、前者
をオフするときは後者をオンに、同期してオン/オフ駆
動制御する第2の制御手段を備えた同期整流DC−DC
コンバータにおいて、 軽負荷モード,重負荷モードの別を指定する外部信号に
基づいて、軽負荷モードでは第1の制御手段を作動さ
せ、重負荷モードでは第1および第2の制御手段を作動
させる手段と、 第2の制御手段が第3のスイッチ素子をオンする期間、
第1の制御手段が第1のスイッチ素子をオンする信号を
無効化する手段とを備えたことを特徴とする同期整流D
C−DCコンバータ。
1. A direct current power supply is connected in series to a series circuit of a smoothing reactor and a load via a first switch element provided in a polarity for supplying power to the load, and a smoothing capacitor is connected in parallel with the load, A diode is connected in parallel to the series circuit of the smoothing reactor and the load in a polarity that maintains the current of the smoothing reactor, a second switching element is connected in parallel with the first switching element and in the same conduction polarity, and A third switch element is connected in parallel with the diode with the same conduction polarity, a means for detecting a load voltage, and a first predetermined value so as to keep the load voltage detected by the voltage detection means at a predetermined value. First control means for ON / OFF driving control of the first switch element in a cycle, second and third in a second predetermined cycle so as to keep the load voltage detected by the voltage detection means at a predetermined value The switching element, turns off the latter when turning on the former, to turn on the latter when turning off the former, synchronous rectification DC-DC having a second control means for controlling synchronization with ON / OFF driving
In the converter, means for activating the first control means in the light load mode and activating the first and second control means in the heavy load mode based on an external signal designating the light load mode and the heavy load mode. And a period in which the second control means turns on the third switch element,
Synchronous rectification D, characterized in that the first control means comprises means for invalidating a signal for turning on the first switch element.
C-DC converter.
【請求項2】請求項1に記載の同期整流DC−DCコン
バータにおいて、 負荷の電流を検出する手段と、 重負荷モードにおいてこの電流検出手段によって検出さ
れた負荷電流が所定値を越えたときは少なくとも第2の
制御手段から第2,第3のスイッチ素子に与えられるオ
ン信号を無効化する手段とを備えたことを特徴とする同
期整流DC−DCコンバータ。
2. The synchronous rectification DC-DC converter according to claim 1, wherein: means for detecting a load current; and a load current detected by the current detecting means in the heavy load mode exceeds a predetermined value. A synchronous rectification DC-DC converter comprising at least means for invalidating an ON signal given to the second and third switch elements from the second control means.
【請求項3】請求項2記載の同期整流DC−DCコンバ
ータにおいて、 前記オン信号の無効化手段は第2の制御手段の電源をし
ゃ断するものであることを特徴とする同期整流DC−D
Cコンバータ。
3. The synchronous rectification DC-DC converter according to claim 2, wherein the means for invalidating the ON signal shuts off the power supply of the second control means.
C converter.
【請求項4】請求項2または3に記載の同期整流DC−
DCコンバータにおいて、 第1の制御手段は前記負荷電流が所定値を越えたとき
は、第1のスイッチ素子のオン比率を下げ負荷電流を垂
下させる手段を備えたことを特徴とする同期整流DC−
DCコンバータ。
4. The synchronous rectification DC- according to claim 2 or 3.
In the DC converter, the first control means includes means for lowering the ON ratio of the first switch element to droop the load current when the load current exceeds a predetermined value.
DC converter.
JP6010726A 1994-02-02 1994-02-02 Synchronous-rectification dc-dc converter Pending JPH07222438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6010726A JPH07222438A (en) 1994-02-02 1994-02-02 Synchronous-rectification dc-dc converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6010726A JPH07222438A (en) 1994-02-02 1994-02-02 Synchronous-rectification dc-dc converter

Publications (1)

Publication Number Publication Date
JPH07222438A true JPH07222438A (en) 1995-08-18

Family

ID=11758303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6010726A Pending JPH07222438A (en) 1994-02-02 1994-02-02 Synchronous-rectification dc-dc converter

Country Status (1)

Country Link
JP (1) JPH07222438A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731731A (en) * 1995-05-30 1998-03-24 Linear Technology Corporation High efficiency switching regulator with adaptive drive output circuit
US6320359B1 (en) 2000-02-24 2001-11-20 Fujitsu Limited DC-DC converter and controller for detecting a malfunction therein
WO2001099265A1 (en) * 2000-06-22 2001-12-27 Intel Corporation Dual drive buck regulator
US6911806B2 (en) 1995-11-28 2005-06-28 Fujitsu Limited DC to DC converter producing output voltage exhibiting rise and fall characteristics independent of load thereon
JP2006296186A (en) * 2005-03-18 2006-10-26 Fujitsu Ltd Switching converter
JP2008130950A (en) * 2006-11-24 2008-06-05 Denso Corp Semiconductor device
US7737666B2 (en) 2003-08-04 2010-06-15 Marvell World Trade Ltd. Split gate drive scheme to improve reliable voltage operation range
US8716995B2 (en) 2010-11-24 2014-05-06 Rohm Co., Ltd. Control circuit for switching power supply
JP2014131374A (en) * 2012-12-28 2014-07-10 Ntt Facilities Inc Grid-connection control device
US8912777B2 (en) 2011-08-18 2014-12-16 Rohm Co., Ltd. Control circuit and control method for switching power supply, and switching power supply and electronic apparatus using control circuit and control method
JP2019083609A (en) * 2017-10-30 2019-05-30 株式会社ダイヘン Step-down chopper circuit and robotic control device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731731A (en) * 1995-05-30 1998-03-24 Linear Technology Corporation High efficiency switching regulator with adaptive drive output circuit
US6911806B2 (en) 1995-11-28 2005-06-28 Fujitsu Limited DC to DC converter producing output voltage exhibiting rise and fall characteristics independent of load thereon
US7129682B2 (en) 1995-11-28 2006-10-31 Fujitsu Limited DC to DC converter producing output voltage exhibit rise and fall characteristics independent of load thereon
US6320359B1 (en) 2000-02-24 2001-11-20 Fujitsu Limited DC-DC converter and controller for detecting a malfunction therein
WO2001099265A1 (en) * 2000-06-22 2001-12-27 Intel Corporation Dual drive buck regulator
US7737666B2 (en) 2003-08-04 2010-06-15 Marvell World Trade Ltd. Split gate drive scheme to improve reliable voltage operation range
US8076915B2 (en) 2005-03-18 2011-12-13 Fujitsu Limited Switching converter
JP2006296186A (en) * 2005-03-18 2006-10-26 Fujitsu Ltd Switching converter
JP2008130950A (en) * 2006-11-24 2008-06-05 Denso Corp Semiconductor device
US8716995B2 (en) 2010-11-24 2014-05-06 Rohm Co., Ltd. Control circuit for switching power supply
US8912777B2 (en) 2011-08-18 2014-12-16 Rohm Co., Ltd. Control circuit and control method for switching power supply, and switching power supply and electronic apparatus using control circuit and control method
JP2014131374A (en) * 2012-12-28 2014-07-10 Ntt Facilities Inc Grid-connection control device
JP2019083609A (en) * 2017-10-30 2019-05-30 株式会社ダイヘン Step-down chopper circuit and robotic control device

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