JPH07222065A - Signal processing circuit for charge coupled element - Google Patents

Abstract

PURPOSE:To obtain an image with high S/N and high image quality by eliminating a fixed pattern noise independently of the effect of ambient temperature fluctuation. CONSTITUTION:The processing circuit is provided with intermediate amplifiers 16, 17 amplifying sampling signals c1, c2 at a gain of Av to provide outputs of signals f1, f2 respectively, clamp circuits 20, 21 holding a DC voltage level for an optical black period in the signals f1, f2 to be voltages VD1, VD2 respectively, and sampling circuits 18, 19 sampling the signals f1, f2 based on the application of sampling pulses PA1, PA2 whose timing differs from a timing of sampling pulses P1, P2 and providing outputs of sampling signals g1, g2 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a charge-coupled device, and more particularly to a signal processing circuit for a two-dimensional charge-coupled device having a dual channel readout structure suitable for a high resolution television camera.

[0002]

2. Description of the Related Art Charge coupled devices (hereinafter referred to as CCDs) have become more and more pixels in order to improve image quality, and ultra high resolution CCDs having 2 million pixels or more have been developed for high definition television cameras such as high vision. ing. In the course of this development, there are problems such as high density of pixel patterns and high speed of clock rate to be solved, and also problems such as reduction of sensitivity per unit pixel.

As a technique for solving the problems of high density of pixel pattern and high speed of clock rate, a dual channel read structure (see, for example, the journal of television science, 4th edition).
1 (1987, No. 11, page 988). This is because two horizontal shift registers having the same structure are arranged in parallel in the vertical direction with a transfer electrode sandwiched therebetween, and the signal charges transferred from the vertical shift register are distributed to the upper and lower horizontal shift registers every other pixel. It is a thing. This has the effect of relaxing the pattern rules and halving the clock rate.

There are two major problems when sampling the output signal of an ultra high resolution CCD having a horizontal shift register having such a dual channel read structure. The first problem is vertical stripe-shaped fixed pattern noise and resolution deterioration caused by variations in the DC voltage levels of the output amplifiers of the two horizontal shift registers. A second problem is the S / N deterioration due to the influence of noise of the sampling circuit system itself such as switching noise for the pixel signal whose level is lowered due to the increase in the number of pixels.

Referring to FIG. 5, which shows a block diagram of a signal processing circuit of a conventional CCD, this conventional signal processing circuit of a CCD is a photoelectric conversion element group corresponding to pixels arranged in a matrix of columns and rows on a semiconductor substrate. And a vertical shift register group for vertical transfer of each signal charge of the photoelectric conversion elements in the column direction, and a photoelectric conversion element group adjacent to the right side of the imaging area 1 and covered with a light shield. And a corresponding vertical shift register, and an optical black area 2 for outputting an optical black level which is a photoelectric conversion element output corresponding to a black portion of a subject, and an output of the vertical shift register of the imaging area 1 and the optical black area 2. The horizontal shift registers 3 and 5 which are connected to every other pixel on the side and arranged vertically with the transfer electrode 4 interposed therebetween, and the horizontal shift registers 3 and 5. Of the output amplifiers 6 and 7 connected to the respective output sides of the output amplifiers, and the preamplifiers 8 and 9 that preamplify the outputs of the output amplifiers 6 and 7 and output the signals a1 and a2, respectively. a noise removal circuit 10, which removes the noise of a2 and outputs signals b1 and b2, respectively.
11 and the signals b1 and b2 are sampled to obtain the signal c
Sampling circuits 12 and 1 for respectively outputting 1 and c2
3, a mixing circuit 14 that adds the signals c1 and c2 and outputs a continuous signal d, and a buffer circuit 15 that receives the supply of the signal d and outputs the output signal e to the process circuit.

Next, referring to FIG. 5, the operation of the conventional signal processing circuit of the charge coupled device will be described. The signal charges photoelectrically converted in the image pickup region 1 are vertically transferred by the vertical shift register and are transferred in the horizontal direction. Every other pixel is distributed to the horizontal shift registers 3 and 5. Here, each of the horizontal shift registers 3 and 5 is assumed to be the first and second channels. The signal charges transferred to each of the horizontal shift registers 3 and 5 are transferred to each other with a phase difference of 180 °, and are output as output signals s1 and s2 of the output amplifiers 6 and 7 of the first and second channels, respectively. It is supplied to the amplifiers 8 and 9. Preamplifier 8, 9
Each of which amplifies the signals s1 and s2 and outputs the signals a1 and a, respectively.
2 is supplied to each of the noise elimination circuits 10 and 11.

The noise elimination circuits 10 and 11 are reflection type noise elimination circuits used in, for example, the signal processing circuit of the charge-coupled device described in JP-A-1-208975, and are provided with a delay line whose output terminal is grounded. A differential operation is performed between the input signal of the delay line and the reflected signal returned to the input terminal, the potential difference between the signals in the feedthrough period and the signal period is obtained in an analog manner, and the signal b1, which is the effective signal voltage component of each channel, is calculated. b2 is supplied to each of the sampling circuits 12 and 13. The sampling circuits 12 and 13 generate the signal b1 in response to the supply of the sampling pulses P1 and P2 which are generated every two pixel cycles and have a phase difference of one pixel cycle from each other.
B2 is alternately sampled for each pixel period, and signals c1 and c2 are supplied to the mixing circuit 14 and converted into a continuous signal d. The buffer circuit 15 supplies the output signal e corresponding to the continuous signal d to the process circuit (not shown) in the subsequent stage.

Effective signal voltage component signal b1 of the first channel
Referring also to FIG. 6 which is a time chart of the sampling process of, the CCD output signal s1 from the output amplifier 6
Is the signal a which is amplified by the preamplifier 8 as described above.
It is output as 1. Signal s1 and its amplified signal a1
Is based on a reset period tr in which the output unit is reset by a reset pulse, a feedthrough period tf in which the detection capacitance unit after reset is discharged to a constant potential, and a signal period ts in which signal charges are injected into the detection capacitance unit. As described above, the potential differences Vs1, Vs2, ... Between the feed through period tf and the signal period ts are effective signal voltages.

The signal a1 is supplied to the noise elimination circuit 10,
A differential operation is performed to obtain the potential difference between the signals in the feed through period tf and the signal period ts, and the potential difference Vs is obtained.
, Bs2, ... Is output as a signal b1. The signal b1 is supplied to the sampling circuit 12, is sampled by the sampling pulse P1, and is generated as a signal c1. On the other hand, similarly for the second channel, the signal s
2, a2, b2 and then in the sampling circuit 13,
A sampling signal c2 is generated by the sampling pulse P2. These signals c1 and c2 are added in the mixing circuit 14 to generate a continuous signal d. However, the switching noise Vsn is mixed during the sampling operation for the signals b1 and b2. This kind of ultra high resolution CCD
Is the noise Vs because the signal level is low as described above.
Since n cannot be ignored, it becomes a factor of S / N deterioration.

Two-channel sampling signals c1 and c2
Referring also to FIG. 7, which shows a time chart of the DC voltage level balance adjustment operation,
The window pattern for adjustment is imaged by the CD and the output signal is observed with an oscilloscope. When the offset levels of the output amplifiers 7 and 8 differ, the DC levels VD1 and VD2 of the sampling signals c1 and c2 of the first and second channels for imaging the same pattern also differ. Therefore, since the continuous signal d converted by the mixing circuit 14 becomes a level corresponding to VD1 and VD2 alternately for every pixel period, it is output as fixed pattern noise of the difference ΔVD between these DC levels VD1 and VD2, and the period is displayed on the screen. Vertical stripes. Therefore, in this conventional CCD signal processing circuit, the DC level VD1 of each of the signals c1 and c2 corresponding to the optical black level is obtained.
So that B and VD2B are equal,
The offset level adjusting circuit in 11 is manually adjusted for balance. However, CC due to changes in ambient temperature
It is not possible to prevent the fixed pattern noise from being generated due to the mutual fluctuation of the DC levels VD1B and VD2 due to the collapse of the balance state caused by the temperature drift of the D element and each circuit.

[0011]

In the signal processing circuit of the conventional charge-coupled device described above, the switching noise of the sampling circuit system with respect to the pixel signal whose signal level is lowered due to the increase in the number of pixels corresponding to ultra-high resolution is S / N. There was a drawback that it became a deterioration factor.

Further, there is a drawback that fixed pattern noise in the form of vertical stripes occurs due to variations in the DC voltage levels of the signals of the two channels due to temperature drift due to changes in the ambient temperature, which causes deterioration of resolution.

An object of the present invention is to solve the above-mentioned drawbacks and to eliminate a switching noise and a fixed pattern noise caused by a temperature drift to provide a signal processing circuit of a charge coupled device having a high S / N and a high resolution. To provide.

[0014]

A signal processing circuit for a charge-coupled device according to the present invention is a first photoelectric conversion circuit which is arranged in a matrix on a semiconductor substrate and outputs a first signal charge photoelectrically converted from an image to be picked up. A conversion element group, and a second photoelectric conversion element group which is arranged adjacent to the first photoelectric conversion element group and which is covered with a light shield and outputs a photoelectrically converted second signal charge corresponding to an optical black level. A first and a second shift register for respectively transferring a first and a second charge signal obtained by alternately dividing the charge signal for one horizontal scanning, which is composed of the first and the second signal charges, every pixel period, First and second output amplifier circuits connected to the respective output sides of the first and second shift resisters and outputting first and second video signals corresponding to the first and second charge signals, respectively; The first and First and second noise elimination circuit 2 of the noise removed by the first and second noise cancellation signal, respectively of the video signal output, respectively, said first and second
The effective signal component of each of the noise-removed signals is sampled in response to the supply of the first and second sampling pulses at predetermined first and second timings, respectively, and the first and second sampling signals are respectively sampled. The first and second sampling circuits for outputting, and the first and second sampling signals are amplified by a predetermined gain to obtain the first and second sampling signals.
First and second intermediate amplification circuits for respectively outputting first and second intermediate amplification signals, and first and second first and second intermediate charge signals corresponding to the second signal charges in the first and second intermediate amplification signals, respectively. First and second clamp circuits for holding a DC voltage level at a predetermined first voltage, respectively;
And a second respective intermediate amplified signal to the first and second
Sampling in response to the supply of the third and fourth sampling pulses of the third and fourth timings respectively different from the timing of
The third and fourth sampling circuits for outputting the sampling signal of 1 and the mixing circuit for adding the third and fourth sampling signals to each other to convert into a continuous signal.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, which illustrates an embodiment of the invention in common with like reference numerals / numerals and blocks in FIG. The CCD signal processing circuit includes an imaging area 1, an optical black area 2, a transfer electrode 4, horizontal shift registers 3 and 5, output amplifiers 6 and 7, preamplifiers 8 and 9, and noise common to the conventional one. In addition to the removal circuits 10 and 11, the sampling circuits 12 and 13, the mixing circuit 14, and the buffer circuit 15, signals f1 and f2 obtained by amplifying the sampling signals c1 and c2 from the sampling circuits 12 and 13, respectively.
Sampling in response to the supply of the intermediate amplifiers 16 and 17 for supplying the signals f1 and f2 and the sampling pulses PA1 and PA2 to output the sampling signals g1 and g2 and supply them to the mixing circuit 14. Circuits 18 and 19 are provided.

Next, the operation of this embodiment will be described with reference to FIG. 1 and FIG. 2 which is a time chart of the sampling process of the signal b1. First, as in the prior art, first,
The signal charges photoelectrically converted in the imaging region 1 are distributed to the horizontal shift registers 3 and 5 every other pixel in the horizontal direction, and are output as the output signals s1 and s2 of the output amplifiers 6 and 7 of the first and second channels, respectively. The signals are supplied to the preamplifiers 8 and 9, respectively, amplified and output as signals a1 and a2. In the following, the first channel will be representatively described as in the conventional case. The signal a1 is supplied to the noise elimination circuit 10 and becomes the signal b1 including the potential differences Vs1, Vs2 ,.
1 is supplied to the sampling circuit 12 and is generated as a signal c1 sampled by the sampling pulse P1. This signal c1 is supplied to the intermediate amplifier 16,
While the required amplification is performed, as will be described later, the potential difference Vt1, Vt2 in which the DC level is always held at the potential corresponding to the optical black level by the clamp circuit 20.
The signal f1 including ... Is supplied to the second-stage sample circuit 18.

The sampling circuit 18 is supplied with the sampling pulse PA1 whose timing is 180 ° out of phase so that the signal f1 and the sampling pulse P1 do not overlap each other, and resamples the signal f1 to generate the output signal g1. . On the other hand, also in the second channel, similarly, the sampling signal g2 is generated by the sampling pulse PA2 in the sampling circuit 19 via the signals s2, a2, b2, c2, and f2. These, signal g
1 and g2 are added by the mixing circuit 14 and converted into a continuous signal d. The buffer circuit 15 supplies the output signal e corresponding to the continuous signal d to the subsequent process circuit.

As in the conventional case, the switching noise Vsn is mixed in the output signal c1 when the signal b1 is sampled. Similarly, in the sampling circuit 18 of the second stage, the switching noise Vtn is mixed in the output signal g1. Here, these switching noises Vsn and Vt
If the circuit configurations of the sampling circuits 12 and 18 are the same, the sizes of n are substantially equal, and Vsn = Vtn. Further, when the gain of the intermediate amplifier 16 is Av, the potential difference Vt
1 = Av · Vs1, Vt2 = Av · Vs2, ...
Therefore, the switching noise to signal ratio Vtn / Vt1, Vtn / Vt2, ... In the output signal g1 is equal to the switching noise to signal ratio Vsn / Vs in the signal c1.
1, Vsn / Vs2, ..., It becomes smaller by the gain Av of the intermediate amplifier 16, that is, 1 / Av. Therefore, switching noise at the time of sampling is effectively suppressed by the above-described two-stage sampling.

Referring to FIG. 3, which is a circuit diagram showing the configurations of the intermediate amplifier 16 and the clamp circuit 20, the intermediate amplifier 16 comprises an operational amplifier circuit A61, an input resistor Ri and a feedback resistor Rf, and the clamp circuit 20 comprises: Optical level sampling circuit 201, integrating capacitor CI, sample and hold capacitor CH, reference voltage source VD1, and differential amplifier circuit 202 that is an integrating circuit.
Including and The gain Av of the intermediate amplifier 16 in this figure is Av
= -Rf / Ri.

Referring also to FIG. 3 and FIG. 4, which is a time chart of the operations of the intermediate amplifier 16, the clamp circuit 20, the sampling circuit 18, and the mixing circuit 14, the output signal f1 of the intermediate amplifier 16 from the imaging region 1 is output. The DC voltage level of the OB period supplied from the optical black level (OB) region 2 following the supplied effective display period signal is the sampling pulse P synchronized with the OB period.
In response to the supply of B, the sample is held in the capacitor CH of the sampling circuit 201. The sampled and held OB level VOB is subjected to a differential operation with the reference voltage VD1 in the differential amplifier circuit 202 and fed back to the negative input terminal of the intermediate amplifier 16. As a result, the output signal f1
The potential difference between the above DC voltage level and the reference voltage VD1 is controlled to be always 0. On the other hand, the same operation is performed in the intermediate amplifier 17 and the clamp circuit 21 of the second channel, and the DC voltage level of the output signal f2 in the OB period is controlled to always be the reference voltage VD2. By the above operation, the DC voltage levels of the OB periods of the first and second channels are always held at the reference voltages VD1 and VD2 without being affected by the ambient temperature.

As described above, these signals f1 and f2 are alternately sampled by the sampling circuits 18 and 19 into the signals g1 and g2, and these signals g1 and g2 are converted into the continuous signal d by the mixing circuit 14. At this time, by performing the balance adjustment so that the reference voltages VD1 and VD2 are the same in the initial state, it is possible to always maintain the balanced state without being affected by the ambient temperature fluctuation.

In the present embodiment, the intermediate amplifier is shown as the inverting amplifier structure, but it is needless to say that the same effect can be obtained by the non-inverting amplifier structure.

[0023]

As described above, the signal processing circuit of the charge-coupled device of the present invention includes an intermediate amplifier circuit in which each channel has a predetermined gain, and a clamp circuit which holds the DC voltage level in the OB period at a set voltage. Since the second sampling circuit that further samples the intermediate amplified signal at a different timing from the first sampling circuit is provided, switching noise of the first sampling circuit is not amplified and sampled, and S / N deterioration is prevented. There is an effect that it can be suppressed.

Further, since the influence of the change in the ambient temperature is eliminated, the vertical stripe fixed pattern noise caused by the temperature drift can be greatly suppressed, and a high quality display image can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal processing circuit of a charge coupled device according to the present invention.

FIG. 2 is a time chart showing an example of an operation in the signal processing circuit of the charge coupled device according to the present embodiment.

FIG. 3 is a circuit diagram showing a configuration of an intermediate amplifier and a clamp circuit of FIG.

FIG. 4 is a time chart showing an OB level clamp operation in the signal processing circuit of the charge coupled device according to the present embodiment.

FIG. 5 is a block diagram showing an example of a conventional signal processing circuit of a charge coupled device.

FIG. 6 is a time chart showing an example of the operation of the conventional signal processing circuit of the charge coupled device.

FIG. 7 shows O in the signal processing circuit of the conventional charge coupled device.
It is a time chart which shows B level clamp operation.

[Explanation of symbols]

 1 Imaging Area 2 Optical Black Area 3,5 Horizontal Shift Register 4 Transfer Electrode 6,7 Output Amplifier 8,9 Preamplifier 10,11 Noise Reduction Circuit 12,13 Sampling Circuit 15 Buffer Circuit

Claims (2)

[Claims] 1. A first photoelectric conversion element group that is arranged in a matrix on a semiconductor substrate and outputs a first signal charge that is photoelectrically converted of an image to be captured, and a first photoelectric conversion element group that is adjacent to the first photoelectric conversion element group. A second photoelectric conversion element group that is arranged in a line and is covered with a light shield to output a second signal charge that is photoelectrically converted corresponding to an optical black level; and one horizontal scanning portion including the first and second signal charges. Are connected to the output sides of the first and second shift resisters, which transfer first and second charge signals, respectively, which are obtained by alternately dividing the charge signal of FIG. First and second output amplifier circuits that output first and second video signals corresponding to the first and second charge signals, respectively, and noises of the first and second video signals are removed, respectively. First and second First to output noise-removed signals respectively
And a second noise removing circuit, and first and second timing first predetermined effective signal components of the first and second noise removing signals, respectively.
And first and second sampling circuits for sampling in response to the supply of the second and second sampling pulses and outputting first and second sampling signals, respectively, and the first and second sampling signals are predetermined. First and second intermediate amplification circuits for amplifying with a gain and outputting first and second intermediate amplification signals, respectively, and the second of the first and second intermediate amplification signals.
And a second DC voltage level corresponding to the signal charge of the first and second DC voltage levels, respectively, which are held at predetermined first voltages.
Clamp circuit, and the third and fourth different intermediate amplification signals of the first and second timings from the first and second timings, respectively.
Third and fourth for sampling and outputting third and fourth sampling signals in response to the supply of the third and fourth sampling pulses, respectively, at
And a mixing circuit for adding the third and fourth sampling signals to each other and converting the signals into a continuous signal. 2. The first and second intermediate amplifier circuits each include an operational amplifier circuit including an input resistance and a feedback resistance, and the first and second clamp circuits each output a period during which the second signal charge is output. Fifth and sixth holding the first and second DC voltage levels as sampled fifth and sixth sampling signals in response to supply of fifth and sixth sampling pulses respectively synchronized with
Sampling circuit, first and second reference voltage sources for supplying first and second reference voltages equal to the first voltage, each of the fifth and sixth sampling signals, and the first and second sampling signals. And a differential amplifier circuit that supplies the first and second difference signals of the differential operation result with each of the second reference voltages to the input terminals of the first and second intermediate amplifier circuits, respectively. The signal processing circuit of the charge-coupled device according to claim 1.