JPH07221981A - Image forming device and its method - Google Patents

Abstract

PURPOSE:To save toner consumption by generating video data for reducing toner consumption while shifting an interleave pattern designation signal in the unit of prescribed scanning line interval based on a horizontal synchronizing signal. CONSTITUTION:A mode setting register 3 stores an edge detection pattern group and an interleave pattern group and one or plural patterns in the pattern groups are selected via an MPU I/F under the control of an MPU. As to the edge detection pattern group, a respective signal to left edge detection, right edge detection, both edge detection and no edge detection is selected by the register 3 and the selected signal is fed to an edge detection circuit 1. In the case of interleaving, the respective pattern is selected by the register 3 via the MPU I/F and fed to a mask pattern generating circuit 2. Since the edge pattern and the interleave pattern are optionally selected by the register 3 in this way, toner consumption is saved depending on a print state and a type of a printer.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a laser printer and LE.
To reduce the toner consumption on the engine side in an image forming apparatus that forms a matrix-shaped dot image, such as an electrophotographic recording apparatus applied to a D printer or other page printer, a facsimile, or a digital copying machine. Relates to the invention.

[0002]

2. Description of the Related Art Conventionally, a dot-matrix pixel pattern is formed by repeatedly scanning a laser beam modulated based on video data serially output from an image controller along a generatrix of a photosensitive drum in a main scanning direction. Laser printers for forming a laser are known. Further, the array-shaped pixel forming means arranged in one row in the main scanning direction is arranged in a matrix on the photosensitive drum which relatively moves in the sub-scanning direction while controlling lighting for one line simultaneously or in block units based on video data. L forming a pixel pattern
ED printers are also known.

In this type of page printer, the dot latent image written on the photosensitive drum is visualized with developing toner, the toner image is transferred to a transfer paper, and then a fixing device is used. Although the toner image is fixed, in such a printer, the toner consumption greatly affects the running cost, and the page printer is 300 dpi or 600 d.
Since the print quality is extremely high like pi, when confirming the print format or the created document, for example, it may be required to suppress the toner consumption rather than the print quality. .

As such a toner-saving type image forming apparatus, many dot thinning or line thinning type image forming systems have been proposed in the past. For example, if odd dots or odd lines are thinned out uniformly, As a result, horizontal stripes or vertical stripes in the form of fine line prints are not preferable. Therefore, there is also a technique in which the odd-numbered dots are thinned out, for example, the odd-numbered lines and the even-numbered lines are thinned out without uniformly thinning out the odd-numbered dots, and the mode selection circuit thins out the odd-numbered dots in the odd-numbered lines and the even-numbered lines in the even-numbered lines. (JP-A-62-127771,
Hereinafter referred to as staggered thinning technology)

However, in such a method, since the thinning control is performed regardless of the shape of the print font, the print shape may be disturbed. For this reason, a technique has been proposed in which dots at the edge portion at the boundary position of printing are detected and the dots at the edge portion are not thinned out, and the other dots are thinned out based on a predetermined rule. . (JP-A-2
-144574, hereinafter referred to as edge detection technology)

[0006]

However, both the staggered thinning technique and the edge detection technique have been independently developed independently of each other. In the conventional technique, it is extremely difficult to use the two in combination because of the circuit configuration. Have difficulty.

In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide an invention relating to a toner saving type image formation capable of performing staggered thinning and edge detection in a toner consumption saving mode with a simple circuit configuration or software control. To do. Another object of the present invention is to provide an invention relating to a toner saving type image formation capable of arbitrarily reducing the toner consumption without causing the print shape to be disturbed.

[0008]

SUMMARY OF THE INVENTION The present invention generates video data for toner consumption reduction by appropriately inverting print bits of video data corresponding to an original image, and converts the video data into a matrix dot image. It is applied as an image forming device that supplies to the engine side that forms
The feature of the invention according to claim 1 is that the bit change position is detected while taking the logical product of the video data of one or a plurality of scanning lines and the edge pattern designating signal set appropriately, and the bit change position is detected. The edge detection means for transmitting the corresponding bit data as it is, the thinning means for performing the thinning control while taking the logical product of the video data and the predetermined thinning pattern designating signal, and the data obtained by both means. Means for transmitting data while taking a logical sum, and for generating the video data for toner consumption reduction while shifting the thinning pattern designating signal in units of predetermined scanning line intervals based on the horizontal synchronizing signal. In this case, it is preferable that the value of the mode register that stores the thinning pattern and / or the edge pattern can be changed appropriately.

In the case of character information such as a print font, there is no particular problem because the head bit data is a non-print bit "0", but as in the case of image data or ruled lines, the head bit data is a print bit. In the case of, since there is no previous bit data, that data cannot be detected as an edge. Therefore, in such a case, when the leading bit data of each scanning line is a print bit, it is preferable to provide means for transmitting the bit data as it is.

Video data is generally a binary signal.
1 "is configured as a print bit, but a binary signal"
There is also an engine that configures 0 "as a print bit. In such a case, changing the bit thinning circuit for toner consumption reduction according to the type of print bit makes the circuit configuration complicated. The video data is inverted based on the control signal and sent to the bit decimating circuit for toner consumption reduction, the decimating circuit decimates the bit, and then the decimating data is inverted again to directly or smooth the circuit. It is preferable that the engine can be supplied through a pseudo high-density circuit.

In the above invention, the zigzag thinning and the edge detection in the toner consumption saving mode are configured by a simple circuit configuration, but the same operation can be performed in software control.

The invention according to claim 5 is to achieve the above object by software, and is characterized in that the step A is for offsetting the video data line by a predetermined scanning line interval unit based on the horizontal synchronizing signal. After that, the process shifts to the bit thinning control step B for each scanning line, and in the control step B, the bit change position is detected while the video data of one or a plurality of scanning lines is taken in based on the video clock. The method is characterized by including a step B1 of transmitting the bit data corresponding to the position as it is, and a step B2 of performing thinning control on the bit data not corresponding to the changed position.

In the step A, the number of scanning lines is set to a constant m.
By dividing by (2, 3 ...) And offsetting the video data according to the remainder, staggering can be easily performed in units of 2 lines or 3 lines.

In the step of detecting the leading bit data as an edge, in the bit thinning control step B, before the changing position detecting step, when the leading bit data of each scanning line is a print bit, the bit data is detected. It is preferable to provide a step B ₀ of transmitting data as it is.

Before the step A, "1" is printed when the binarized signal is "0" in order to correspond to the video data in which the binarized signal "0" is used as a print bit. Inversion means may be used so as to make it a bit.

[0016]

Therefore, according to the present invention, the zigzag thinning and the edge in the toner consumption saving mode can be achieved by effectively utilizing the horizontal synchronizing signal or the vertical synchronizing signal with a simple circuit configuration using a logic circuit or with simple software control. Detection can be done easily. Further, according to the present invention, since the edge pattern and the thinning pattern can be arbitrarily selected by the mode selection register, it is possible to achieve the most preferable toner consumption reduction according to the printing state and the print type to be output. Further, according to the present invention, not only one-dimensional edge detection in the main scanning direction but also two-dimensional edge detection including the sub-scanning direction can be performed. Further, according to the present invention, it is possible to commonly use both the video data in which the binarized signal "1" is configured as the print bit and the video data in which the binarized signal "0" is configured as the print bit. , It is versatile without being limited to the type of video data.

[0017]

Embodiments of the present invention will now be illustratively described in detail with reference to the drawings. However, the dimensions, materials, shapes, relative positions and the like of the components described in this embodiment are not intended to limit the scope of the present invention thereto, but are merely examples, unless otherwise specified. Not too much. Figure 3
Shows an overall configuration of an image processing circuit used in an LED printer or a laser printer to which the present invention is applied,
12 is an SR in which bitmap data for a predetermined page is stored
Bit map memory consisting of AM, control logic 13
3 based on the video clock VCLK transmitted from
Video data VDATA of 00 dpi is serially transmitted to the thinning control circuit 14.

Then, the thinned-out video data VDATA 'appropriately thinned out by the control circuit 14 is guided to a pseudo high-density circuit 15 which carries out pseudo high-density together with smoothing, and the pseudo high-density circuit 15 makes the high density. By supplying video data to the LED head or the laser circuit 11 and exposing the photoconductor drum 16 on the print engine side by the head circuit 11, a toner consumption saving latent image can be formed. In the figure, the control logic 13 is composed of an MPU for transmitting various control signals such as vertical synchronization, horizontal synchronization and other control signals to the corresponding block together with the video clock.
For smoothing or pseudo densification,
Further, as will be described later, it is a line buffer for temporarily storing reference line data in order to perform thinning control by referring to bitmap data of a plurality of lines.

The toner saving thinning control circuit 1
As shown in FIG. 1, reference numeral 4 includes an edge detection circuit 1, a mask pattern generation circuit 2, and a mode setting register 3 for transmitting a control signal from a control logic (MPU) 13 to each circuit. The mode setting register 3 stores the edge detection pattern group shown in FIG. 2A and the thinning pattern group shown in FIG. 2B, which are controlled by the MPU (not shown) via the MPUI / F. One or more patterns are selected from the pattern group. The edge detection pattern group shown in FIG.
(10) to detect only the right edge, (01) to detect only the right edge, and (1 to detect both edges.
1) If the edge detection is not further performed, the signal (00) is selected by the mode setting register 3 via the MPUI / F, and the signal is transmitted to the edge detection circuit 1. The thinning pattern group shown in FIG. 2B is R4 (100) when thinning 3 dots, R6 (010) when thinning 5 dots, and R8 (001) when thinning 7 dots. Is selected by the mode setting register 3 via the MPUI / F, and the signal is transmitted to the mask pattern generation circuit 2. Next, detailed configurations of these circuits will be described.

FIG. 4 shows the edge detection circuit 1, which includes the preceding position, the current position,
And a 3-bit shift register 21 including three flip-flops F / Fs 21C, 21B, and 21A that sequentially and serially store the following three line bit data based on the video clock, the left edge, the right edge shown in FIG. It is composed of AND gates 22L and 22R that detect the absence of an edge and an OR gate 24 that selectively sends these data. Reference numeral 25 is an inverter that inverts a signal to AND the AND gate 22L.

Next, the operation of the circuit 1 will be described. F / F2 of the shift register 21 by the horizontal synchronizing signal
After resetting 1A, B, and C, the bit data of the corresponding scanning line is serially transmitted from the first bit. When the left edge designating signal L is output from the mode setting register 3, the left edge AND gate 22L sends the designating signal together with the rear-to-current bit signal to the F / F 21C, 21.
The bit change of 0 to 1 of the bit signal is detected by taking out from B and performing the AND, and when the subsequent data is the non-printing bit (0) through the OR gate 24, the current printing is performed. The bit (1) data is sent as it is as edge data.

When the right edge designating signal R is output from the mode setting register 3, the right edge AND gate 22R takes out the preceding and present bit signals together with the designating signal from the flip-flops F / Fs 21B and 21A. , AND
By detecting the bit change of 1 to 0 of the bit signal, if the preceding data is a non-printing bit (0), the current printing bit (1) data is detected through the OR gate 24. It is sent as it is as edge data.

On the other hand, when detecting both edges, the same operation as described above is performed by sending out both the left edge designating signal L and the right edge designating signal R from the mode setting register 3.

When the edge detection is not further performed, since the edge designating signal is not sent from the mode setting register 3, the mask signal MASK from the mask generating circuit 2 and the current bit signal B are processed by the edgeless AND gate 23. By taking the AND and transmitting it, bit data is transmitted based on the thinning pattern designating signal from the mask generation circuit 2.

FIG. 5 is a block diagram of the mask generation circuit 2, and FIG. 6 is a detailed configuration diagram thereof. Referring to the time chart of FIG. 7, 31 is the SDAT of the edge detection circuit 1.
A clock timing circuit that shifts VCLK by 3 clocks corresponding to A.
32C, 32B, 32A, an inverter 33, and an AND gate 34. When VCLK is transmitted for 3 clocks, a counter enable signal CNTEN is oscillated, and the AND gate 34 synchronizes with the inverted signal of VCLK to binary the counter clock CNTCLK. It transmits to the counter 35. On the other hand, R4, R6, and R8 are 3 dots, 5 dots,
A Hi signal is transmitted corresponding to each thinning pattern of 7 dots, and the operation of the corresponding AND gates 471 to 473 of the counter value detection circuit 47 and the corresponding AND gates 361 to 363 of the load signal generation circuit 36 are performed. Allow.

On the output side of the binary counter 35, an inverter 39 and an AND gate 3 are provided corresponding to the thinning pattern.
61 to 363 and F / Fs 371 to 373 are serially arranged in parallel with the load signal generating circuit 37 to configure the load signal generating circuit 37, and NAND gates 381 and 382.
The load signal is transmitted to the binary counter 35 via the load signal selector 38 composed of 383 and NOR gate 384. As a result, the counter 35 is cleared in units of 4 bits in the case of a 3-dot thinning pattern, in units of 6 bits in the case of a 5-dot thinning pattern, and in units of 8 bits in the case of a 7-dot thinning pattern. A thinning pattern designating signal MASK that repeats in units of 4, 6, and 8 bits is generated corresponding to CNTCLK.

AND of the load signal generating circuit 36
Of the gates 361 to 363, only one AND gate is valid based on R4, R6, and R8. Specifically, since the thinning pattern designating signal R4 is Hi, only the AND gate 361 is valid. Therefore, in units of 4 bits, In the case of the 5-dot thinning pattern, the counter 35 is cleared in units of 6 bits, and in the case of the 7-dot thinning pattern, the counter 35 is cleared in units of 8 bits, and a repeating signal in units of 4, 6, or 8 bits is generated in response to the counter clock. Is generated.

On the other hand, 40 is an F / F for switching the selection signal SEL to the Hi / Lo level for each odd / even scanning line.
In the line number detection circuit consisting of, the selection signal SEL output from the line number detection circuit 40 is cleared from Hi (odd line) every time the horizontal synchronization signal LSYNC is input after being cleared based on the vertical synchronization signal VSYNC. Lo (even line),
Switching from Lo to Hi.

The selection signal SEL is ANDed as it is.
AND gates 431 to 43 of the selector circuit 43 transmit the inverted signal to the gate 41 and also via the inverter 42.
3 and the other input terminals of the AND gates 431 to 433 are respectively connected to the AND gate 4 of the counter value detection circuit 47.
71 to 473 are connected to the output terminals. The AND gates 471 to 473 of the counter value detection circuit 47 have a signal R.
Which AND gate is to be made effective is selected based on 4, R6, and R8. Since the signal R4 is Hi in this embodiment.
Only the AND gate 471 is valid.

Further, since the AND gates 431 to 433 are not effective when the inversion selection signal SEL is at the Lo level, the lines of the AND gates 471/431 are effective only in the even scanning lines in the present embodiment, while the odd number is odd. In the scan line, the line of AND gate 46/41 becomes effective. This achieves staggered thinning.

AND which becomes effective in odd scan lines
To the gate 46, three signal lines C0, C1 and C2 are connected through the inverters 45, 45 and 45, so that the Hi signal is output from the AND gate 46 only when the pulse of C3 is generated from the binary counter 35. Is output, A
With the selection signal SEL of the odd scan line at the ND gate 41
The AND signal is taken and the mask signal MASK becomes Hi via the OR circuit 44.

Therefore, in the odd line, the mask signal MASK becomes Hi only when the pulse of C3 is generated, and the mask signal MASK becomes Lo in the case of the other pulses of C0, C1 and C2. Therefore, the 3-dot thinning-out in which the mask signal MASK becomes Hi is repeatedly performed for every 4th bit video data.

On the other hand, signal lines C0 and C2 are connected to the AND gate 471 which becomes effective at the even scanning line via the inverters 45, 45, and C1 is directly connected to the AND gate 471. Therefore, the Hi signal is output from the AND gate 471 only when the C1 pulse is generated from the binary counter 35, and the AND gate 471 outputs the Hi signal.
Then, the mask signal becomes Hi through the OR circuit 44 by taking the AND with the inversion selection signal SEL of the even scanning line.

Therefore, in the even scan line, the mask signal MASK becomes Hi only when the pulse of C1 is generated, and the mask signal MASK becomes Lo in the case of the other pulses of C0, C2, and C3. Therefore, the 3-dot thinning-out in which the mask signal becomes Hi is repeatedly performed for each video data of the second bit. Therefore, by repeating the odd scan line and the even scan line to perform the thinning control, the even scan line is bit-by-bit 2, 6, 10 ... And the odd scan line is bit-by-bit 4, 8, 12 ... A print bit (1) is sent to the edge detection circuit 11 side, and as a result, zigzag thinning can be performed by shifting by 2 bits for each odd / even scanning line.

In the above embodiment, one-dimensional edge detection along the main scanning line direction is performed. However, when edge detection in the sub-scanning direction is also required as in the case of vertical line ruled lines. There is.

FIG. 8 shows the overall construction of an image processing circuit to which the present invention is applied and which performs thinning-out control in two dimensions. Three scanning lines are stored in the bit map memory 12 in which bit map data for a predetermined page is stored. After storing the minute video data in the buffer RAM 50, the RAM control 52
3 × 3 sample window 50 based on the signal from
In the thinning-out control circuit 51, the edge of the bit of interest and the adjacent bits located above, below, left and right of the bit of interest are detected.

The edge detection circuit 61, as shown in the sample window 501 of FIG. 9 and FIG. AND
By taking. Which of the detected edges is to be selected is determined by the AN of the mode setting register 65 for selecting the edge detection mode shown in FIG. 11 via the MPUI / F and the edge detection data obtained from the circuit of FIG.
This is performed by an edge selection circuit composed of an AND gate 64 and an OR gate 66 that take D. Then, in the mode setting register 65, the edge detection pattern data from “OOOO” to “1111” is selected by the MPUI / F.

That is, the mode is as shown in FIG.
"OOOO" when the edge is OFF, "10" when the edge is upper
“00” for the left edge, “1100” for the upper + left edge, etc. are stored in the mode setting register 65. Then, the edge detection mode data stored in the mode setting register 65 and the edge detection data shown in FIG. 9 are ANDed by the AND gate 64 to perform edge selection.

When the edge is OFF, the mask signal MA
By ANDing SK and the bit A of interest with the AND gate 67, the masked video data is OR gate 6
8 is sent. As a result, the two-dimensional processing is smoothly performed.

The circuit has a circuit configuration assuming that the printing bit, that is, the black dot printed on the photosensitive drum side is "1" and the non-printing bit is "0". There is also an image processing circuit adapted to generate video data in which the print bit is "0" and the non-print bit is "1" in accordance with the characteristics on the engine side. In such a case, it is not versatile and it is not a good idea to newly configure the thinning control circuit in response to the difference in the type of the video data. In such a case, any of the above video data can be handled by using a logic circuit as shown in FIG. That is, in FIG. 12A, 71 and 72 are exclusive OR gates, which transmit video data and control data from the MPU, specifically, "0" or "1" corresponding to the type of video signal. The control data and the video data input to the thinning control circuit 70 or the thinning data output from the thinning control circuit 70 are configured to be exclusive ORed. According to such a circuit,
When the print bit is "0", the video data is as shown in FIG.
As shown in (B), the control data of "1" is generated in the MPU (not shown), and the gate 71 performs an exclusive OR of the control data to input the video data to the thinning control circuit 70. Is inverted and the inverted video data is input to the thinning control circuit 70, so that the normal video data thinning control circuit whose print bit is "1"
Thinning control is possible. Then, the thinned data after the thinning control is again subjected to exclusive OR with the control data, so that the data is inverted again, and the thinned data with the print bit "0" is supplied to the processing circuit of the next process or the engine side.

On the other hand, when the print bit is "1", the video data input to the thinning control circuit 70 is also generated by generating the control data of "0" as shown in FIG. Further, none of the thinning data output from the thinning control circuit 70 is inverted. Therefore, according to such an embodiment, it is not necessary to newly configure the thinning-out control circuit corresponding to the difference in the type of the video data, and the commonization is possible. The inversion of the video data and the thinned-out data is not necessarily limited to the exclusive OR gate, and other inversion circuits can be used or software inversion can be performed. The thinning control can be performed by software without necessarily using a hardware circuit.

FIG. 13 is a flow chart for performing the thinning control by software. First, it is judged whether the print bit of the video data for the thinning control is "1" or "0".
In the case of 0 ", the data is inverted by the inversion circuit as shown in FIG. 12 or by software, and then the process goes to the line number detecting step A (STEP 0).

In the line number detecting step A, the counter is reset at the stage when the vertical synchronizing signal is input, and then the line count number is counted at the stage when the horizontal synchronizing signal is input next, and the count is performed by the constant m. Divide the number. For example, when the constant m is 2, the remainder is 1 when the scanning line is odd, and the remainder is 0 when the scanning line is even. And the remainder is 1
If it is 1 or not (if it is an odd number), the process shifts to the thinning control step B without offsetting the video data. (STEP1)

In the thinning control step B, when the leading bit data of each scanning line is the print bit (1), the bit data is sent as it is and the print bit (1) is written in the bit buffer. (STEP2) Then, the process proceeds to the edge detecting step. For example, when one-dimensional processing is performed, the trailing data is a non-printing bit (0) as shown in FIG. 2B. If the current print bit (1) data is an edge, the left edge is viewed. If the previous data is a non-print bit (0), the current print bit (1) data is viewed as an edge. There is an edge and both edges are detected to see the left and right edges, but this embodiment exemplifies the step of detecting both edges. (STEP3) That is, in STEP3, first, the bit change between the latter and the current bit is detected, and if there is a change of (0 → 1), the bit data of the current bit is transmitted as it is and the print bit ( The left edge can be detected by writing 1),
Next, by detecting a bit change between the current position and the previous position, and if there is a change (1 → 0), the current bit data is transmitted as it is and the print bit (1) is written in the bit buffer. The right edge can be detected.

When two-dimensional processing is performed based on the reference bits before and after the current bit, pattern matching may be performed by software based on the data shown in FIG. ,

After performing the edge detection, it is detected whether or not the current bit data is at the thinning point,
When it is at the thinning point, the non-printing bit (0) is written in the bit buffer, and when it is not the thinning point, the printing bit (1) is written in the bit buffer. (STEP 4) The thinning-out position may be set by hardware using the above-mentioned mode setting register 3 or the like, or may be set by software while counting the video clock.

After the above processing is completed, the bit position is incremented by 1 bit and the thinning control is repeatedly performed by the same operation. (STEP5)

After the thinning control of all the bits of one scanning line is completed, the process returns to (STEP1 '), and at the stage when the next horizontal synchronizing signal is input, the line count number is divided by a constant m to obtain the remainder. If 0 is 0 (even number), the video data is offset by 2 bits, and then the above-described thinning control step is performed.

The thinning control is performed in the same manner as the above-described line operation.
Since the bits are offset, the thinning-out position is delayed by 2 bits as compared with the preceding scanning line, and by repeating this, staggered thinning-out control can be performed.

According to this technique, therefore, the thinning control in the toner consumption saving mode can be easily performed while the staggered thinning and edge detection are easily performed by effectively utilizing the horizontal synchronizing signal or the vertical synchronizing signal. Further, by appropriately deleting or adding the above steps, it is possible to set the most preferable toner consumption saving mode according to the print type.

[0051]

As described above, according to the present invention, a zigzag thinning and edge detection in a toner consumption saving mode can be performed with a simple circuit configuration or a simple software without any disturbance in the print shape and arbitrarily reducing the toner consumption. It can be done under control. It has various remarkable effects.

[Brief description of drawings]

FIG. 1 is a basic block diagram showing a basic configuration of the present invention (one-dimensional edge processing).

2A and 2B show edge detection patterns used in the drawing and thinning patterns in FIG. 2B, respectively.

FIG. 3 is a block diagram showing an image processing apparatus incorporating the present invention (one-dimensional edge processing).

FIG. 4 is a detailed circuit diagram showing an example of the edge detection circuit of FIG.

FIG. 5 is a block diagram showing an example of the mask generation circuit of FIG.

6 is a detailed circuit diagram showing an example of the mask generation circuit of FIG.

7 is a time chart diagram of FIG.

FIG. 8 is a block diagram showing an image processing apparatus incorporating the present invention (two-dimensional edge processing).

FIG. 9 is an edge detection circuit used in FIG.

FIG. 10 is an edge selection circuit used in FIG.

11 is an edge selection mode used in FIG. 9;

FIG. 12 is a block diagram for using a common thinning-out control circuit even if there is a difference in the type of video data.

FIG. 13 is a flowchart showing the basic operation of the present invention.

[Explanation of symbols]

 1 Edge Detection Circuit 2 Mask Pattern Generation Circuit 13 Control Logic (MPU) 3 Mode Setting Register 40 Line Detection Circuit

Claims (7)

[Claims] 1. A video data for toner consumption reduction is generated by appropriately inverting print bits of video data corresponding to an original image, and the video data can be supplied to an engine side which forms a matrix dot image. In the image forming apparatus configured as described above, the bit change position is detected while taking the logical product of the video data of one or a plurality of scanning lines and the edge pattern designating signal set appropriately, and the bit data corresponding to the change position is unchanged. An edge detecting means for sending data, a thinning means for performing thinning control while taking a logical product of the video data and a predetermined thinning pattern designating signal, and a data while taking a logical sum of the data obtained by both means. And a means for transmitting the thinning pattern designating signal based on the horizontal synchronizing signal. An image forming apparatus wherein the produced configured to be able to video data for reducing the toner consumption amount while shifting interval basis 2. The image forming apparatus according to claim 1, further comprising means for transmitting the bit data as it is when the leading bit data of each scanning line is a print bit. 3. The image forming apparatus according to claim 1, wherein a numerical value of a mode register for storing the thinning pattern and / or the edge pattern can be appropriately changed. 4. An image forming apparatus for forming a matrix dot image while supplying video data having a binary signal "0" as a print bit to an engine side, by reversing the video data to reduce toner consumption. Image forming apparatus capable of supplying the data to the engine side directly or through a smoothing circuit or a pseudo high-density circuit by inverting the thinned-out data again after sending out to the bit thinning-out circuit for 5. A video data for toner consumption reduction is generated by appropriately inverting print bits of video data corresponding to an original image, and the video data can be supplied to an engine side which forms a matrix dot image. In the image forming method of the present invention, after the step A of offsetting the video data in units of predetermined scanning line intervals based on the horizontal synchronizing signal, the process proceeds to the bit thinning control step B for each scanning line, and the control step B
In step B1, detecting the bit change position and transmitting the bit data corresponding to the change position as it is while fetching the video data of one or more scanning lines based on the video clock, and the bit data not corresponding to the change position. Forming method including the step B2 of performing thinning control for 6. The image forming method according to claim 5, wherein the step A is a step of dividing the number of scanning lines by a constant m and offsetting the video data by a predetermined number of bits corresponding to the remainder. 7. In the bit thinning-out control step B, before the change position detecting step, a step B ₀ for transmitting the bit data as it is when the leading bit data of each scanning line is a print bit is provided. Claim 5 characterized by the above
Image forming method described