JPH07221625A - Buffer circuit - Google Patents

Abstract

PURPOSE:To reduce the through current by limiting a current made flow between the drains of a pair of transistors for driving whose polarities are mutually different by a current limiting means. CONSTITUTION:The current limiting means 100 limits the current made flow between the drain of a first P-channel transistor 101 and the drain of a first N-channel transistor 104. Thus, a potential difference is generated between the gate of a second P-channel transistor 102 connected to the drain of the first P-channel transistor 101 and the gate of a second N-channel transistor 105 connected to the drain of the first N-channel transistor 104. Thus, by shifting the driving timings of the second P-channel transistor 102 and the second N- channel transistor 105 as the transistors for output, the time when both second P-channel transistor 102 and second N-channel transistor 105 are turned to an on state is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a buffer circuit used in a drive unit or the like that drives a heavy load bus inside an SI.

[0002]

2. Description of the Related Art A conventional output buffer circuit will be described with reference to FIG. In FIG. 5, 51 is a P-channel transistor, 52 is an N-channel transistor, 53 is an input terminal, and 54 is an output terminal. The source of the P-channel transistor 51 is connected to the power supply voltage source, and the source of the N-channel transistor 52 is connected to the ground voltage source. The input terminal 53 is configured by connecting the gates of a P-channel transistor 51 and an N-channel transistor 52 to each other, and an input signal is applied to the input terminal 53.
The output terminal 54 is configured by connecting drains of a P-channel transistor 51 and an N-channel transistor 52 to each other, and an output signal is obtained from the output terminal 54. This is the simplest output buffer circuit with a CMOS inverter configuration.

FIG. 6 shows an input voltage range (that is, an ON voltage range) in which a current of each transistor in this CMOS inverter flows. The ON voltage range of the P-channel transistor 51 is from the ground voltage VSS to the power supply voltage VD.
Threshold voltage Vtp of P-channel transistor rather than D
Range up to a low voltage (VDD-Vtp). On the other hand, the ON voltage range of the N-channel transistor 52 is a range from a voltage (VSS + Vtn) higher than the ground voltage VSS by the threshold voltage Vtn of the N-channel transistor to the power supply voltage VDD. Therefore, the input voltage range in which both transistors conduct current is a voltage (VSS + Vt) higher than the ground voltage VSS by Vtn.
n) to a voltage (VDD-Vtp) lower than the power supply voltage VDD by Vtp. Since the input voltage has a gradient in the time axis direction, the CMOS inverter causes a so-called through current to flow from the power supply to the ground in the time range in which the input voltage falls within this input voltage range.

[0004]

In the CMOS inverter used as the output buffer circuit, the width of the transistor is increased or the transistors are connected in parallel to enhance the driving capability. Along with this, the shoot-through current becomes large and the wasteful current consumption becomes remarkable.

As described above, the conventional output buffer circuit has a problem that the through current is large and the current consumption of the LSI is increased.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a buffer circuit capable of reducing a shoot-through current.

[0007]

In order to achieve the above-mentioned object, the invention of claim 1 is characterized in that the current limiting means is inserted between the gates of a pair of output transistors having different polarities. The drive timing of the output transistor is shifted.

Specifically, the solving means devised by the invention of claim 1 is intended for a buffer circuit for driving a load in accordance with an input signal, and includes first and second P-channel transistors and first and second P-channel transistors. N-channel transistor, first and second
Current limiting means for limiting a current flowing between the first terminal and the second terminal, the sources of the first and second P-channel transistors being a first voltage source. Connected, the sources of the first and second N-channel transistors are connected to a second voltage source, and the drain of the first P-channel transistor and the gate of the second P-channel transistor are the current limiting means. Of the first N-channel transistor, the drain of the first N-channel transistor and the gate of the second N-channel transistor are connected to the second terminal of the current limiting means, and An input signal is input to an input terminal where a gate and a gate of the first N-channel transistor are connected, and a drain of the second P-channel transistor and the second It is an arrangement in which the output signal from the output terminal and the drain channel transistors are connected is output.

According to a second aspect of the present invention, the current limiting means is composed of a pair of transistors having polarities different from each other. Specifically, a buffer circuit for driving a load according to an input signal is targeted. And the first, second and third
P-channel transistor and the first, second and third N
A channel transistor, and the first and second P
The source of the channel transistor is connected to a first voltage source, the sources of the first and second N-channel transistors are connected to a second voltage source, the drain of the first P-channel transistor and the second The gate of the P-channel transistor, the source of the third P-channel transistor and the drain of the third N-channel transistor are connected to each other, and the drain of the first N-channel transistor and the gate of the second N-channel transistor The source of the third N-channel transistor and the drain of the third P-channel transistor are connected to each other, and the gate of the first P-channel transistor, the gate of the first N-channel transistor and the third
An input signal is input to the input terminal where the gate of the P-channel transistor and the gate of the third N-channel transistor are connected, and the drain of the second P-channel transistor and the drain of the second N-channel transistor The output signal is output from the output terminal connected to.

[0010]

According to the structure of the invention of claim 1, the current limiting means limits the current flowing between the drain of the first P-channel transistor and the drain of the first N-channel transistor. Therefore, between the gate of the second P-channel transistor connected to the drain of the first P-channel transistor and the gate of the second N-channel transistor connected to the drain of the first N-channel transistor. It is possible to generate a potential difference. This allows
By shifting the driving timing of the second P-channel transistor and the second N-channel transistor as the output transistor, the time for which both the second P-channel transistor and the second N-channel transistor are in the ON state is shortened. can do.

According to the second aspect of the present invention, a pair of third P-channel transistor and third N-channel transistor whose drain and source are connected to each other and whose gates are both connected to the input terminal are formed. The current limiting means can be realized. Here, for example, the first
N-channel transistor and a third N-channel source connected to the drain of the first N-channel transistor
By changing the driving strength of the channel transistor, it is possible to change the timing at which the second P-channel transistor is turned on and the timing at which the second N-channel transistor is turned off. Similarly, by changing the driving strength of the first P-channel transistor and the third P-channel transistor whose source is connected to the drain of the first P-channel transistor, the second P-channel transistor is changed. It is possible to change the timing of transition to the off state and the timing of transition of the second N-channel transistor to the on state. This makes it possible to further shorten the time during which both the second P-channel transistor and the second N-channel transistor are in the ON state.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

An output buffer circuit according to an embodiment of the present invention is shown in FIG. In FIG. 1, 100 is a current limiting circuit which has a first terminal and a second terminal and limits a current flowing from the first terminal to the second terminal by a voltage value of another terminal or another signal, and 101 is a driving circuit. First P as a transistor
A channel transistor, 102 is a second P-channel transistor as an output transistor, 104 is a first N-channel transistor as a driving transistor,
105 is a second N-channel transistor as an output transistor, 107 is an input terminal, 108 is an output terminal,
109 is a first node and 110 is a second node.

First and second P-channel transistors 1
The power supply voltage VDD is applied to the sources of 01 and 102,
On the other hand, the first and second N-channel transistors 104,
The ground voltage VSS is applied to the source of 105. The first node 109 is a connection point where the drain of the first P-channel transistor 101, the gate of the second P-channel transistor 102, and the first terminal of the current limiting circuit 100 are connected, and the second node 109 110 is a connection point at which the drain of the first N-channel transistor 104, the gate of the second N-channel transistor 105, and the second terminal of the current limiting circuit 100 are connected. In addition, the input terminal 107 has a gate of the first P-channel transistor 101 and the first N-channel transistor 10
The drain of the second P-channel transistor 102 and the drain of the second N-channel transistor 105 are connected to the output terminal 108.

FIG. 2 shows the current limiting circuit 100 as shown in FIG.
It is a connection diagram when it comprises using the circuit shown to (a). In the figure, 103 is a third P-channel transistor as a current limiting transistor, and 106 is a third N-channel transistor also as a current limiting transistor. Third P-channel transistor 103
Of the third N-channel transistor 106 is connected to the drain of the third N-channel transistor 106 to form a first terminal of the current limiting circuit 100, which is connected to the first node 109. Of the P-channel transistor 103 is connected to form a second terminal of the current limiting circuit 100, which is connected to the second node 110. In addition, the third P-channel transistor 10
The gates of the third and third N-channel transistors 106 are both connected to the input terminal 107. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The operation of the output buffer circuit will be described below with reference to FIG.

First, attention is paid to the DC-like operation. When the input voltage is the power supply voltage VDD, the first N-channel transistor 104 and the third N-channel transistor 106 are turned on, and the first P-channel transistor 101 and the third P-channel transistor 103 are turned off. Therefore, in terms of DC, the first node 109 and the second node 1
10 is the ground voltage VSS. Therefore, the second P-channel transistor 102 is turned on,
The second N-channel transistor 105 is turned off and outputs VDD as an output voltage. On the other hand, when the input voltage is VSS, the on and off states of each transistor are reversed, and VSS is output as the output voltage. As described above, the circuit of FIG. 2 is a buffer circuit which outputs the signal values VDD and VSS in the same state with respect to the inputs VDD and VSS, respectively.

Next, the transient operation will be described. As an initial condition, the first node 109 and the second node 1
The voltage of 10 is VDD, the input terminal 107 and the output terminal 10
The voltage of 8 is VSS. Further, by setting the transistors 101, 103, 104 and 106 of the input stage smaller than the size of the transistors 102 and 105 of the output stage, the input capacitance can be reduced as compared with the conventional example shown in FIG. it can. As a result, as shown in FIG. 3A, the input voltage can change from the ground voltage VSS to the power supply voltage VDD at a time T0 with a sufficiently fast rise.

In this case, as shown in FIG. 3 (b), first, at time T0, the first N-channel transistor 104 transitions to the ON state, discharge is started at the second node 110, and the second node 110 is discharged. The voltage drop at 110 begins.
Next, the voltage of the second node 110 is (VDD-Vtn)
At time T1 at which the third P-channel transistor 106
Shifts to the ON state, discharge is started at the first node 109, and the voltage of the node 109 starts dropping. Next, at time T2 when the voltage of the first node 109 becomes (VDD-Vtp), the second P-channel transistor 102 is turned on. Further, at time T3 when the voltage of the second node 110 becomes (VSS + Vtn), the second N-channel transistor 105 transitions to the off state. After that, the voltages of the first node 109 and the second node 110 approach the ground voltage VSS.

Therefore, when T2≤T3, the transistors 102 and 105 in the output stage are both turned on from the time T2 to the time T3. Also, T
If 2 ≧ T3, the output stage transistors 102, 10
There is no time for both 5 to be on.

As described above, in the output buffer circuit of this embodiment, the first node 109 to the second node 11 are connected.
Since the current flowing to 0 can be limited, the first node 109
And a second node 110 can generate a potential difference. As a result, the timing at which the second N-channel transistor 105 transitions to the off state (time T3)
And the timing (time T2) at which the second P-channel transistor 102 transitions to the ON state becomes small.
As a result, the time during which both the second N-channel transistor 105 and the second P-channel transistor 102 are turned on is shortened, and the shoot-through current is reduced.

The times T2 and T3 can be changed by changing the driving strength of the transistors 106 and 104, respectively. As a result, the second P-channel transistor 102 and the second N-channel transistor 1
It is possible to further shorten the time when both 05 and 05 are in the ON state.

On the other hand, when the input signal falls from the power supply voltage VDD to the ground voltage VSS, the ON and OFF states of each P-channel transistor and each N-channel transistor are switched, and the same operation is performed.

Another example of the current limiting circuit 100 is shown in FIG.
There are circuits as shown in (b) to (d). In FIG. 4B, 203 is a first diode and 204 is a second diode. When the circuit of FIG. 4B is used, the voltage of the first node 109 is the same as that of the example of FIG.
It drops while maintaining a value higher than 0 by a diode voltage Vd. In FIG. 4C, 205 is a P-channel transistor, 206 is an N-channel transistor,
In FIG. 4D, 207 is a P-channel transistor and 208 is an N-channel transistor. Figure 4
When the circuit of (c) or FIG. 4 (d) is used, when the rising waveform is input as in the example of FIG. 4, the current for discharging the electric charge at the first node 109 is limited. , The voltage drop rate of the first node 109 is slower than the voltage drop rate of the second node 110.

Therefore, according to the output buffer circuit in which the circuits shown in FIGS. 4B to 4D are used as the current limiting circuit 100, as in the case where the circuit of FIG. The difference between the timing at which the N-channel transistor 105 transitions to the OFF state and the timing at which the second P-channel transistor 102 transitions to the ON state becomes small. As a result, the N-channel transistor 105 and P
The time during which both the channel transistor 102 and the channel transistor 102 are in the ON state is shortened, and the shoot-through current is reduced.

On the other hand, when the input signal falls, the ON and OFF states of each P-channel transistor and each N-channel transistor are switched, and the same operation is performed.

In the circuits of FIGS. 4A to 4D, when the symmetry between the operation when the input signal rises and the operation when the input signal falls is not required, the P-channel transistor and the N-channel transistor are It is also possible to remove either one or one of the two diodes.

[0028]

As described above, according to the buffer circuit of the first aspect of the present invention, the current flowing between the drains of the pair of driving transistors having different polarities can be limited by the current limiting means. A potential difference can be generated between the gates of a pair of different output transistors. Thus, by shifting the driving timing of the pair of output transistors, the time during which both of the pair of output transistors are in the ON state can be shortened, so that the shoot-through current can be reduced.

According to the buffer circuit of the second aspect of the present invention, the current limiting means can be realized by the pair of current limiting transistors having different polarities. Further, by changing the driving strength of the driving transistor and the current limiting transistor, it is possible to further shorten the time in which both the pair of output transistors are in the ON state.

Therefore, according to the present invention, it is possible to realize the buffer circuit capable of reducing the through current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a connection diagram showing a connection relationship of the output buffer circuit.

3A is a timing diagram showing an input signal input to the output buffer circuit, and FIG. 3B is a timing diagram showing an operation of the output buffer circuit.

4A to 4D are circuit diagrams showing an example of a current limiting circuit of the output buffer circuit.

FIG. 5 is a circuit diagram showing a configuration of a conventional output buffer circuit.

FIG. 6 is a diagram showing an operating voltage range of the conventional output buffer circuit.

[Explanation of symbols]

 100 Current Limiting Circuit 101 First P-Channel Transistor 102 Second P-Channel Transistor 103 Third P-Channel Transistor 104 First N-Channel Transistor 105 Second N-Channel Transistor 106 Third N-Channel Transistor 107 Input Terminal 108 Output terminal 109 First node 110 Second node 203 First diode 204 Second diode 205,207 P-channel transistor 206,208 N-channel transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Norio Utsumi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Masahiro Gion, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A buffer circuit for driving a load according to an input signal, comprising: first and second P-channel transistors; first and second N-channel transistors; and first and second terminals. And current limiting means for limiting a current flowing between the first terminal and the second terminal, wherein sources of the first and second P-channel transistors are connected to a first voltage source, The sources of the first and second N-channel transistors are connected to a second voltage source, and the drains of the first P-channel transistor and the second
The gate of the P-channel transistor is connected to the first terminal of the current limiting means, and the drain of the first N-channel transistor and the gate of the second N-channel transistor are the second terminal of the current limiting means. Connected to the
The gate of the first P-channel transistor and the first
An input signal is input to an input terminal connected to the gate of the N-channel transistor, and an output signal is output from the output terminal connected to the drain of the second P-channel transistor and the drain of the second N-channel transistor. A buffer circuit characterized by being output. 2. A buffer circuit for driving a load according to an input signal, comprising first, second and third P-channel transistors, and first, second and third N-channel transistors, The sources of the first and second P-channel transistors are connected to a first voltage source, the sources of the first and second N-channel transistors are connected to a second voltage source, and the first P-channel is connected. The drain of the transistor and the second
The gate of the P-channel transistor, the source of the third P-channel transistor, and the drain of the third N-channel transistor are connected to each other, and
The drain of the channel transistor, the gate of the second N-channel transistor, the source of the third N-channel transistor and the drain of the third P-channel transistor are connected to each other, and the gate of the first P-channel transistor is connected. An input signal is input to an input terminal to which the gate of the first N-channel transistor, the gate of the third P-channel transistor, and the gate of the third N-channel transistor are connected, and the second P-channel transistor is input.
A buffer circuit, wherein an output signal is output from an output terminal to which a drain of a channel transistor and a drain of the second N-channel transistor are connected.