JPH07221618A - Semiconductor transmitter - Google Patents

Abstract

PURPOSE:To prevent the destruction of a gallium arsenide field effect transistor (GaAsFET) by changing abnormality signals at the time of gate voltage abnormality to optical signals, transmitting them, changing them to electric signals and interrupting a drain bias voltage applied to the FET. CONSTITUTION:When a gate voltage applied to the gate of GaAsFET 1 goes out of an appropriate range due to the abnormality of a gate bias voltage generation circuit 2 or the like, a window comparator 8 outputs electric abnormality signals. The signals are converted to optical abnormality signals in an electric/optic converter 9, passed through an optical cable 10, turned to the abnormality signals by an optic/electric converter 12 inside a power source part 18 and inputted to an interruption circuit 16. Then, the interruption circuit 16 interrupts the drain bias generated in a drain bias voltage generation circuit 5 and applied to the drain of the GaAsFET 1. Thus, the destruction of the GaAsFET 1 is prevented. Also, by using the optical signals for the delivery of the abnormality signals, the malfunction of the interruption circuit 16 due to noise from an outside or the like is prevented as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply for a semiconductor transmitter.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing a conventional semiconductor transmitter. 1 gallium arsenide field effect transistor in FIG. (Ga As F ield E ffect T ra
2 is a gate bias voltage generating circuit for supplying a gate voltage to the GaAs FET 1, and 3 and 4 are gate bias voltages generated by the gate bias voltage generating circuit 2 depending on a division ratio thereof. These are a gate-side dividing resistor and a ground-side dividing resistor that have optimum values for the gate voltage. Reference numeral 5 is a drain bias voltage generating circuit for applying a drain voltage to the drain of the GaAsFET 1.

The conventional semiconductor transmitter is constructed as described above, and the gate bias voltage, which is a constant negative voltage generated by the gate bias voltage generating circuit 2, is applied to the gate side division resistor 3.
And the ground side division resistor 4 optimizes the gate voltage of the GaAsFET 1 and applies it to the gate of the GaAsFET 1. The drain bias voltage generated by the drain bias voltage generating circuit 5 is applied to the drain of the GaAsFET 1 as the drain voltage.

[0004]

In the conventional semiconductor transmitter as described above, the gate voltage is not applied to the gate of the GaAs FET 1 due to a failure of the gate bias voltage generating circuit 2 or the gate bias voltage approaches zero potential. When the drain voltage is applied while fluctuating in the direction, the GaAsFET 1 has a problem that an excessive current flows in the drain of the GaAsFET 1 to destroy the GaAsFET 1.

The present invention has been made to solve the above problems, and when the gate bias voltage is cut off due to an abnormality in the gate bias voltage generating circuit, and the direction in which the gate bias voltage approaches zero potential. The purpose is to obtain a power supply that cuts off the drain bias voltage and prevents the GaAsFET from being destroyed when it fluctuates.

[0006]

In the semiconductor transmitter according to the present invention, the gate voltage is input to the window comparator, and when the gate voltage is out of the proper value range, an electrical abnormality signal is output. Is converted to an abnormal optical signal by an electro-optical converter, the optical abnormal signal is transmitted to the power supply unit by an optical cable, and the optical abnormal signal is converted to an abnormal signal which is an electric signal by the electric power converter in the power supply unit, and a cutoff circuit To shut off the drain bias voltage applied to the GaAs FET.

Further, when the drain bias voltage is cut off by the window comparator, the electro-optical converter, the opto-electrical converter, and the blocking circuit, the gate voltage fluctuation time is lengthened to facilitate the blocking in time. G to do
Add a capacitor to the gate of the aAsFET.

Further, low frequency power amplification field-effect transistor a gate voltage constituting a source follower (F ie
ld E ffect T ransistor; following FE
(Referred to as “T”), and after amplifying the current and inputting the output to the window comparator, when the gate voltage is out of the proper value range, an electrical abnormality signal is output, and the electrical abnormality signal is converted into an electro-optical signal. Converter to an optical anomaly signal, the optical anomaly signal is transmitted to the power supply section by an optical cable, the power supply section converts the optical anomaly signal into an electrical anomaly signal by an electro-optical converter, and drives the cutoff circuit. GaAsF
It cuts off the drain bias voltage applied to ET.

Further, the gate voltage is connected via a resistor to the base of a pnp transistor forming an emitter follower for current amplification, and the output thereof is input to a window comparator. When the gate voltage is out of a proper value range, an electric power is supplied. An abnormal signal is output, the electrical abnormal signal is converted into an optical abnormal signal by the electro-optical converter, the optical abnormal signal is transmitted to the power supply unit by the optical cable, and the optical abnormal signal is converted into an electrical signal by the electro-optical converter in the power supply unit. Is converted into an abnormal signal, the cutoff circuit is driven, and the drain bias voltage applied to the GaAs FET is cut off.

When the drain bias voltage is cut off by the cut-off circuit after passing through the source follower, the window comparator, the electro-optical converter, the opto-electrical converter, and the cut-off circuit,
A capacitor is added to the gate of the GaAs FET so as to lengthen the fluctuation time of the gate voltage so as to facilitate interruption in time.

Further, when the drain bias voltage is cut off by the cut-off circuit after passing through the emitter follower, the window comparator, the electro-optical converter, the opto-electrical converter, and the cut-off circuit, the fluctuation of the gate voltage is facilitated in time. A capacitor is added to the gate of the GaAs FET to lengthen the time.

[0012]

In the semiconductor transmitter configured as described above, the gate voltage of the GaAsFET is input to the window comparator. Therefore, when a gate voltage outside the proper range is applied to the gate of the GaAs FET due to a failure of the gate bias voltage generation circuit, the gate voltage is input to the window comparator, an electrical abnormality signal is generated, and an optical abnormality is generated by the electro-optical converter. The signal is converted into a signal and is input to the opto-electric converter of the power supply unit via the optical cable, is changed into an abnormal signal which is an electric signal, and is input to the cutoff circuit.
The drain bias voltage applied to the aAsFET is cut off so that the drain voltage is not applied to the drain of the GaAsFET and the breakdown of the GaAsFET is prevented.

Further, a large-capacity capacitor is added to the gate of the GaAs FET to make the fluctuation time for the gate voltage to change outside the proper range, thereby providing a window comparator, an electro-optical converter, an optical cable, an opto-electric converter. After the signal passes, the interruption of the drain bias voltage by the interruption circuit is facilitated in time.

Further, in the semiconductor transmitter configured as described above, the gate voltage applied to the GaAs FET is connected to the gate of the FET constituting the source follower. The source follower has a high input impedance due to its elemental and circuit properties, and the output voltage becomes almost equal to the input voltage. Therefore, when a gate voltage outside the proper range is applied to the gate of the GaAs FET due to a failure of the gate bias circuit, the gate voltage is input to the window comparator via the source follower composed of the FET, and an electrical abnormality signal is generated. , Is converted into an optical abnormal signal by the electro-optical converter, is input to the opto-electric converter of the power supply unit via the optical cable, is converted to an abnormal signal that is an electrical signal, is input to the cutoff circuit, and is applied to the GaAs FET in the cutoff circuit. Cut off the drain bias voltage generated,
A drain voltage is prevented from being applied to the drain of ET to prevent destruction of the GaAs FET.

Further, in the semiconductor transmitter configured as described above, the gate voltage applied to the GaAsFET is connected to the base of the pnp transistor forming the emitter follower via the resistor. The output voltage of the emitter follower is almost equal to the input voltage and the input impedance is high due to its circuit property. Therefore, when a gate voltage outside the proper range is applied to the gate of the GaAs FET due to a failure of the gate bias circuit, the gate voltage is p
Through an emitter follower composed of an np transistor, an electric abnormality signal is generated by being input to a window comparator, converted into an optical abnormality signal by an electro-optical converter, and input to an opto-electric converter of a power supply unit via an optical cable. An abnormal signal, which is an electric signal, is converted into an abnormal signal, which is input to the cutoff circuit and cuts off the drain bias voltage applied to the GaAsFET in the cutoff circuit so that the drain voltage is not applied to the drain of the GaAsFET and the GaAsFET is prevented from being destroyed.

Further, by adding a large-capacity capacitor to the gate of the GaAs FET to make the fluctuation time of the gate voltage fluctuate outside the proper range, a source follower, a window comparator, an electro-optical converter, an optical cable, an opto-electrical device. Through the converter and the signal, the interruption of the drain bias voltage by the interruption circuit is facilitated in time.

Further, a large-capacity capacitor is added to the gate of the GaAs FET to make the fluctuation time of the gate voltage fluctuate out of the proper range, so that an emitter follower, a window comparator, an electro-optical converter, an optical cable, an opto-electrical device. Through the converter and the signal, the interruption of the drain bias voltage by the interruption circuit is facilitated in time.

[0018]

【Example】

Example 1. FIG. 1 is a diagram showing an embodiment of the present invention,
1, 2, 3, 4, and 5 are exactly the same as the above-mentioned conventional device. 6 is a drain bias terminal connected to the drain of the GaAsFET 1, 7 is a grounded drain bias terminal, 8 is connected to the gate of the GaAsFET 1, and when the input gate voltage is out of the proper range of the gate voltage of the GaAsFET 1, electrical A window comparator that outputs an abnormal signal, 9 is an electro-optical converter that converts the electrical abnormal signal of the window comparator 8 into an optical abnormal signal, 10 is an optical cable through which the optical abnormal signal is transmitted, and 11 is connected to the electro-optical converter 9. Abnormality detection optical cable connector, 12 is an optical-electrical converter for converting an optical abnormal signal into an abnormal signal which is an electric signal, 1
3 is an abnormal input optical cable connector connected to the photoelectric converter 12, 14 is a drain bias output terminal connected to the drain bias terminal 6, 15 is a drain bias output return terminal connected to the drain bias ground terminal 7, and 16 is An abnormal signal of the output of the photoelectric converter 12 and the drain bias voltage generated by the drain bias voltage generation circuit 5 are input, and when the output of the photoelectric converter 12 does not output the abnormal signal, the drain bias voltage is output to output the abnormal signal. A cutoff circuit that cuts off the drain bias voltage,
Reference numeral 17 is a transmitter section, and 18 is a power supply section.

In the semiconductor transmitter configured as described above, the gate voltage applied to the gate of the GaAsFET 1 is input to the window comparator 8. The window comparator 8 has an input voltage outside the proper range of the gate voltage of the GaAsFET 1. At the time of, it is set to output an electrical abnormality signal. Further, this electrical abnormality signal is converted into an optical abnormality signal which is an optical signal by the electro-optical converter 9,
It is sent to the power supply unit 18 via the optical cable 10. This optical abnormal signal is converted into an abnormal signal which is an electric signal by the photoelectric converter 12 in the power supply unit 18, and the cutoff circuit 1
6 is input. Therefore, the gate bias voltage generation circuit 2
When the gate voltage applied to the gate of the GaAsFET 1 is out of the proper range due to the abnormality of, the window comparator 8 outputs an electrical abnormality signal, and the electrical abnormality signal is converted into an optical abnormality signal by the electro-optical converter 9. Optical cable 1
An abnormal signal is input to the cutoff circuit 16 by the photoelectric converter 12 in the power supply 18 via 0, and the cutoff circuit 16 is generated by the drain bias voltage generation circuit 5
Since the drain bias applied to the drain of No. 1 is cut off, an excessive current flows to the GaAsFET 1 to prevent the breakdown. Further, since the optical signal is used to deliver the abnormal signal, it is possible to prevent the interruption circuit from malfunctioning due to external noise or the like.

Example 2. FIG. 2 shows G in the first embodiment.
A large-capacity capacitor 19 is added to the gate of the aAsFET1, and even if the gate voltage is out of the proper value range due to a failure of the gate bias voltage generation circuit 2 or the like, the gate of the GaAsFET1 is compared with the case without the capacitor 19. It is possible to lengthen the fluctuation time of the gate voltage applied to the gate circuit and facilitate the blocking of the drain bias voltage by the blocking circuit 16 in terms of time.

Example 3. FIG. 3 shows G in the first embodiment.
An FET 20 having a gate connected to the gate of the aAsFET 1, a drain connected to the bias voltage V _DS , and a source grounded via a load resistor 21 is added, and the source of the FET 20 is connected to the input of the window comparator 8. The FET 20 and the load resistor 21 constitute a so-called source follower, which has a high input impedance and a voltage gain of about 1. Therefore, according to this configuration, the first embodiment
The circuit below the window comparator 8 described in the first embodiment can be connected to the GaAsFET 1 without changing the effect described in 1 above and without impairing the operation of the GaAsFET 1 that is sensitive to the fluctuation of the gate voltage value.

Example 4. FIG. 4 shows G in the first embodiment.
The base of the aAsFET 1 is connected to the gate of the aAsFET 1 via the current controlling resistor 22, the collector is connected to the bias voltage -V _C , and the emitter is grounded via the load resistor 21 to which the pnp transistor 23 is added.
Is connected to the input of the window comparator 8. The pnp transistor 23 and the load resistor 21 constitute a so-called emitter follower, which has a high input impedance and a voltage gain of about 1. Therefore, with this configuration, the effect described in the first embodiment is not changed, and moreover, the GaAs FET sensitive to the fluctuation of the gate voltage value.
The circuits below the window comparator 8 described in the first embodiment can be connected to the GaAsFET 1 without impairing the operation of the first embodiment.

Example 5. FIG. 5 shows G in the third embodiment.
A large-capacity capacitor 19 is added to the gate of the aAsFET1, and even if the gate voltage is out of the proper value range due to a failure of the gate bias voltage generation circuit 2 or the like, the gate of the GaAsFET1 is compared with the case without the capacitor 19. It is possible to lengthen the fluctuation time of the gate voltage applied to the gate circuit and facilitate the blocking of the drain bias voltage by the blocking circuit 16 in terms of time.

Example 6. FIG. 6 shows G in the fourth embodiment.
A large-capacity capacitor 19 is added to the gate of the aAsFET1, and even if the gate voltage is out of the proper value range due to a failure of the gate bias voltage generation circuit 2 or the like, the gate of the GaAsFET1 is compared with the case without the capacitor 19. It is possible to lengthen the fluctuation time of the gate voltage applied to the gate circuit and facilitate the blocking of the drain bias voltage by the blocking circuit 16 in terms of time.

[0025]

Since the present invention is constructed as described above, it has the following effects.

When the gate voltage of the GaAs FET is out of the proper value range, the window comparator generates an electrical abnormality signal which is an electrical signal, and the electro-optical converter converts the electrical abnormality signal to an optical abnormality signal which is an optical signal, and a transmitter is transmitted through an optical cable. Is sent to the power supply section from the power supply section to an abnormal signal which is an electric signal by the electro-optical converter, and the drain bias voltage of the GaAsFET is cut off by driving the cutoff circuit by the signal to prevent the GaAsFET from being destroyed. At that time, by using the optical signal and the optical cable for transmitting the abnormal signal to the transmitter section and the power supply section, it is possible to prevent the malfunction of the interruption circuit due to the external noise or the like.

By inserting a source follower between the gate of the GaAsFET and the comparator, the operation from the window comparator to the drain bias voltage cutoff circuit can be operated without affecting the operation of the GaAsFET which is sensitive to the change of the gate voltage. Can be done.

By inserting an emitter follower between the gate of the GaAsFET and the comparator, the operation from the window comparator to the drain bias voltage cutoff circuit can be performed without affecting the operation of the GaAsFET sensitive to the change in the gate voltage. Can be operated.

Further, by connecting a large-capacity capacitor to the gate of the GaAsFET, the change time for the gate voltage to change outside the proper value range is moderated, and from the detection of the gate potential outside the proper value range to the drain bias voltage cutoff. Can be facilitated in terms of time.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing Embodiment 4 of the present invention.

FIG. 5 is a diagram showing a fifth embodiment of the present invention.

FIG. 6 is a diagram showing Embodiment 6 of the present invention.

FIG. 7 is a diagram showing a conventional semiconductor transmitter.

[Explanation of symbols]

 1 GaAsFET 2 Gate Bias Voltage Generating Circuit 3 Gate Side Dividing Resistor 4 Ground Side Dividing Resistor 5 Drain Bias Voltage Generating Circuit 6 Drain Bias Terminal 7 Drain Bias Ground Terminal 8 Wind Comparator 9 Electro-Optical Converter 10 Optical Cable 11 Abnormality Detection Optical Cable Connector 12 Optical Electrical converter 13 Abnormal input optical cable connector 14 Drain bias output terminal 15 Drain bias output return terminal 16 Interruption circuit 17 Transmitter section 18 Power supply section 19 Capacitor 20 FET 21 Load resistor 22 Current control resistor 23 pnp transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04B 10/08 10/28 10/26 10/14 10/04 10/06 9372-5K H04B 9 / 00 Y

Claims (4)

[Claims] 1. A gallium arsenide field effect transistor for amplifying a high frequency, a drain bias terminal connected to the drain of the gallium arsenide field effect transistor, a grounded drain bias ground terminal, and the gallium arsenide field effect transistor. Connected to the gate of the transistor,
The other side electrode is grounded to the ground side dividing resistor and the gate of the gallium arsenide field effect transistor, and the other side electrode is connected to a gate bias voltage generating circuit for generating a gate bias voltage. A gate side division resistor for applying a gate voltage to the gate of the gallium arsenide field effect transistor according to a division ratio with the side division resistor, and a gate voltage applied to the gate side division resistor and the ground side division resistor and the gate side division resistor. A window comparator that outputs an electrical abnormality signal when the voltage is out of the proper gate voltage range, an electro-optical converter that converts the electrical abnormality signal of this window comparator into an optical abnormality signal, and this electrical-optical converter are connected. Anomaly detection optical cable connector,
An optical cable that is connected to one end of this abnormality detection optical cable connector, an abnormal input optical cable connector that is connected to the other end of this optical cable, and an optical abnormal signal that is connected to this abnormal input optical cable connector and converts the abnormal optical signal into an abnormal signal that is an electrical signal An opto-electric converter, a drain bias voltage generating circuit for generating a drain bias voltage of the gallium arsenide field effect transistor, a drain bias output terminal connected to the drain bias terminal, and a drain bias ground terminal. The drain bias output return terminal, the above-mentioned abnormal signal and the above-mentioned drain bias voltage are input, the drain bias voltage is output when the abnormal signal shows no abnormality, and the drain bias voltage is cut off when the abnormal signal shows abnormal. Drain bias output terminal Semiconductor transmitting apparatus characterized by being configured with a shutdown circuit connected to the serial drain bias return terminal. 2. A low-frequency power amplification field effect transistor in which a gate voltage is connected to a gate, a source is grounded via a load resistor, a drain is connected to a bias voltage, and the gate voltage is current-amplified and input to a window comparator. The semiconductor transmission device according to claim 1, further comprising: 3. A pnp circuit in which a gate voltage is connected to a base via a current control resistor, an emitter is grounded via a load resistor, a collector is connected to a collector bias voltage, and the gate voltage is current-amplified and input to a window comparator.
The semiconductor transmission device according to claim 1, further comprising a transistor. 4. The semiconductor transmitting device according to claim 1, wherein a capacitor is added to the gate of the gallium arsenide field effect transistor.