JPH07220482A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a consuming current and drive at high velocity in a semiconductor memory device using a ferroelectric film for a capacitor accumulating electric charges. CONSTITUTION:A group of memory cells connected to one word line WL1 or WL2 is divided optionally. Divided memory cells 51, 53 or 52, 54 share one division cell plate line DCP1 or DCP2. The division cell plate line is connected to a cell plate line CP via a selection transistor T1 or T2, and a gate of the selection transistor T1 or T2 is controlled by the word line WL1 or WL2. Accordingly, since only a necessary cell plate for a read/write operation is selectively driven, a load capacity is reduced, a consuming current is decreased and a high-speed operation is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a capacitor having a ferroelectric film.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device, a device of a type in which charges are stored in a capacitor formed inside and data is stored depending on the presence or absence of the charges is mainly used. Such a semiconductor memory device is generally called a dynamic type memory (hereinafter referred to as DRAM), and a silicon oxide film has been used as an insulating film of its capacitor. In recent years, a semiconductor memory device has been known in which a ferroelectric film made of a ferroelectric material is used as an insulating film of a capacitor to make data storage non-volatile.

FIG. 8 shows the relationship between the voltage applied to the ferroelectric substance and the self-polarization of the ferroelectric substance. As shown in FIG. 8, the transition of the polarization state of the ferroelectric substance shows a hysteresis characteristic, and Even when the voltage applied to the dielectric becomes zero, the residual polarization Pr remains in the ferroelectric. When a ferroelectric film made of such a ferroelectric material is used as an insulating film of a capacitor of a semiconductor memory device, it becomes possible to retain data in the capacitor even after the power is turned off, which makes nonvolatile storage of data possible. Can be realized.

A conventional semiconductor memory device having a capacitor having a ferroelectric film will be described below with reference to the drawings.

First, the structure of the conventional semiconductor memory device will be described. FIG. 7 is a circuit diagram showing the conventional semiconductor memory device 1. In FIG. 7, the semiconductor memory device 1 is
Bit lines for writing data to and reading data from the memory cells 2 and 3 for storing bit data, the dummy cells 4 and 5, the sense amplifier 6, and the memory cells 2 and 3, respectively. BLB1, B
LB2, word lines WLB1 and WLB2 for selecting memory cells 2 and 3, and cell plate line CPB
And dummy word lines DWL1 and DWL2. The memory cells 2 and 3 have memory cell capacitors C1 and C2 having ferroelectric films and MOS transistors T1 and T2, respectively. Similarly, the dummy cells 4 and 5 are connected to the dummy cell capacitors C3 and C4 having a ferroelectric film and the MO cells.
It has S transistors T3 and T4, respectively. One electrode of each of the memory cell capacitors C1 and C2 and the dummy cell capacitors C3 and C4 is a cell plate line C.
It is connected to PB and MOS transistors T1 and T2
Is the memory cell capacitors C1 and C2 and the bit line BLB
1 and BLB2 are respectively connected at the time of selection, and the MOS transistors T3 and T4 are dummy cell capacitors C3 and C4.
And the bit lines BLB2 and BLB1 are connected when selected.

Next, the write operation of the semiconductor memory device 1 as described above will be described. For example, when writing data “1” to the memory cell 2, first, the bit line BLB1
By applying a high level potential to the word line and the word line WLVI and a low level potential to the cell plate line CPB, a positive voltage is applied to the memory cell capacitor C1,
The polarization state of the memory cell capacitor C1 is the state S1 in FIG.
Becomes Next, the potential applied to the cell plate CPB transitions to a high level, so that the voltage applied to the memory cell capacitor C1 becomes zero, and the memory cell capacitor C1
The polarization state of 1 transits to the state S2 of FIG. Next, cell plate line CPB, word line WLB1, bit line BLB
Even if the potentials applied in the order of 1 are returned to the low level, the polarization state of the memory cell capacitor C1 remains in the state S2 of FIG. In this way, the data "1" is written in the memory cell 2, and the polarization state of the memory cell capacitor C1 is maintained without change even if the power supply is removed.

When writing data "0" to the memory cell 2, first, a low level potential is applied to the bit line BLB1, a high level potential is applied to the word line WLB1, and further the cell plate line CPB. A low level potential is applied to. Next, by shifting the potential applied to the cell plate line CPB to a high level, a negative voltage is applied to the memory cell capacitor C1, and the polarization state of the memory cell capacitor C1 becomes the state S3 in FIG. Next, when the potential applied to the cell plate line CPB and the word line WLB1 in this order returns to the low level, the polarization state of the memory cell capacitor C1 becomes the state S4 in FIG. 8, and the data “0” is written in the memory cell 2. . The polarization state of the memory cell capacitor C1 remains unchanged even when the power supply is removed, as in the case where the data "1" is written.

Next, the read operation of the semiconductor memory device 1 will be described. First, prior to the read operation, the bit line BL
A low-level potential is applied to B1 and BLB2. Then, by applying a high-level potential to the word line WLB1, the MOS transistor T51 is turned on, and the bit line BLB1 and the memory cell capacitor C1 are connected. At this time, the voltage applied to the memory cell capacitor C1 is zero, and the polarization state of the memory cell capacitor C1 is the preset state S2 or S in FIG.
It is held at 4. Next, by changing the potential applied to the cell plate line CPB to a high level, a negative voltage is applied to the memory cell capacitor C1, and the polarization state of the memory cell capacitor C1 is the state S2 or S in FIG.
The state changes from 4 to state S3. At this time, the bit line BLB
The potential appearing at 1 depends on the data written in the memory cell 2 in advance, and the data "1" appears at the memory cell 2.
Is written, the memory cell capacitor C
The polarization state of 1 transits from the state S2 of FIG. 8 to the state S3,
The amount of charge discharged from the memory cell capacitor C1 is relatively large, and the potential of the bit line BLB1 becomes a high read potential L1 as shown in FIG. On the other hand, when the data “0” is written in the memory cell 2, the polarization state of the memory cell capacitor C1 changes from the state S4 to the state S in FIG.
3, the amount of charge released from the memory cell capacitor C2 is smaller than that in the case where data "1" is written, and the potential of the bit line BLB1 becomes a low read potential L2 as shown in FIG. . And the sense amplifier 6
Receives the read potential L1 or L2 and determines whether the data is "1" or "0".

In the above conventional example, one memory cell is formed by one transistor and one ferroelectric capacitor (hereinafter referred to as 1T1C type memory cell).

FIG. 10 shows an example in which one memory cell is formed by two transistors and two ferroelectric capacitors (US Pat. No. 4,873,66).
No. 4 specification). Hereinafter, this memory cell is referred to as a 2T2C type memory cell. FIG. 10 shows a memory cell 10 that stores 1-bit data, a sense amplifier 11, and bit lines 12 and 1 that write and read data to and from the memory cell 10.
3 and the word line 14 for selecting the memory cell 10,
The cell plate line 15 is shown. The memory cell 10 has capacitors 16 and 17 having ferroelectric films and MOS transistors 18 and 19. The operation of the word line and the cell plate line at the time of writing and reading data to and from the memory cell is the same as that of the conventional 1T1C type memory cell described above, but by having two bit lines, high level and low level The difference is that the complementary data of is written in one memory cell. For example, when writing "1" data to the memory cell 10, a high level is applied to the bit line BIT,
After applying a low level to the bit line BIT, the word line 14 and the cell plate line 15 are brought into the selected state, whereby the ferroelectric capacitors 16 and 17 are set to the states S2 and S4 in FIG. . This state is 1T1
As in the case of the C-type memory cell, it is retained even when the power supply is removed. In order to read, 1T1 described above from this state
Select word line 14 as in the case of C-type memory cells,
By setting the cell plate line 15 to the high state, the L1 level in FIG. 10 is output to the bit line BIT and the L2 level is output to the bit line BIT. The sense amplifier 11 detects this level difference and data is read.

In the above two conventional examples, a circuit for storing one or two data is shown for the sake of explanation. However, in an actual semiconductor memory device, a large number of data are stored, so that the circuit described above is used. It is necessary to arrange the memory cells in an array. FIG. 11 shows an example of array arrangement. 36a, 3
6b, 36c and 36d respectively represent word lines, and 38
Reference numerals a, 38b, 38c, 38d denote cell plate lines, respectively, and 30a, 32a, 30b, 32b, 30c, 3
2c, 30d, and 32d represent bit line pairs, and 3
Reference numerals 4a, 34b, 34c and 34d denote sense amplifiers, respectively, and 20a, 20b, 20c, 20d, 20f and 2
Each 0g indicates a memory cell. FIG. 12 shows an array arrangement of four rows and four rows, with four word lines each.
Connected to each memory cell, each cell plate line is 4
, And each bit line pair is also connected to four memory cells. Although the cell plate signal can drive all 16 memory cells in the figure at the same time, in the embodiment of FIG. 11, the cell plate line divides the memory array in the same unit as the word line, Four memory cells arranged in the same direction and arranged in the word line direction are simultaneously selected to write and read data.

It is also possible to divide the memory array by arranging the cell plates in a direction perpendicular to the word lines.
2 shows an example in which the memory array is divided in a direction perpendicular to the word lines. Reference numerals 40a, 40b, 40c and 40d denote word lines, 41a, 41b, 41c and 41d denote bit lines or bit line pairs, and 42a and 4a.
Reference numerals 2b, 42c and 42d indicate cell plate lines, 43a, 43b, 43c and 43d indicate memory cells, and 45 indicates a sense amplifier block.

FIG. 12 also shows an array arrangement of four memory cells each in the vertical and horizontal directions. In this example, only the memory cell in which the selected word line and the selected cell plate line intersect is in the selected state, and the data is read / written.

[0014]

By the way, since the cell plate line is arranged in the same unit as the word line in the memory array arrangement of the embodiment of FIG. 11, when one word line is selected, it is connected to the word line. A cell plate is also selected as the memory cell, and data is read from the memory cell. Since the read operation from the memory cell is destructive read, rewriting by the sense amplifier must be performed on these selected memory cells.
Therefore, all sense amplifiers 34a, 34b, 34c, 34d connected to the selected memory cell through the bit line must be activated. This results in an increase in current consumption.

Although the cell plate line drives all memory cells in the word line direction, the capacitance of the ferroelectric capacitor driven by the cell plate is a silicon oxide film used in a normal dynamic semiconductor memory. The load capacitance connected to the cell plate line becomes excessively large compared to the formed capacitor. In order to drive the cell plate signal at an appropriate speed, M, which has a large driving capability,
Since it is necessary to use the OS transistor, there are problems that the current consumption and the layout area increase.

In the example of FIG. 12, since the cell plate signal is arranged orthogonal to the word line to divide the memory array, only the sense amplifier connected to the bit line activated by the selected cell plate line. It only needs to operate, and the increase in current consumption by the sense amplifier is small. However, the cell plate line is similar to the memory array arrangement of FIG. 11 in that it drives all the memory cells in the bit line direction, and the load capacitance connected to the cell plate line is extremely large, and a MOS transistor having a large driving capability is also used. However, there is a problem that the current consumption and the layout area increase.

The present invention has been made in view of the above, and reduces the load capacitance of the cell plate signal,
The purpose is to reduce the layout area.

[0018]

To achieve the above object, a semiconductor memory device according to the present invention has a divided cell plate line in which at least memory cells having a capacitor formed of a ferroelectric film are electrically common. And the divided cell plate line is connected to the cell plate line via a transistor.

Also, a memory cell having a capacitor formed of a ferroelectric film is connected to a word line and a bit line, and between the specific two word lines and the specific two bit lines. The memory cells connected to the memory cells are connected by a divided cell plate line that is electrically common, and the divided cell plate line is connected to the cell plate line through a transistor.

The number of the memory cells connected between the specific two word lines and the specific two bit lines is two.

The number of the memory cells connected between the specific two word lines and the specific two bit lines is four.

Also, a memory cell having a capacitor formed of a ferroelectric film is connected to a word line, and the memory cells connected between two specific word lines are electrically common. The divided cell plate line is connected to the cell plate line through a transistor, and the transistor is connected to
It is connected to a logic circuit that generates the logical sum of the word lines of the book.

[0023]

With the semiconductor memory device having the above-described configuration and operation, the load capacity of the cell plate signal drive circuit can be reduced, the operating current can be reduced, and the semiconductor memory device can operate at high speed.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

First, the configuration of this embodiment will be described. Figure 1
FIG. 3 is a circuit diagram showing a semiconductor memory device 50 of this embodiment.
In FIG. 1, a semiconductor memory device 50 includes memory cells 51, 52, 53, 54 for storing 1-bit data, and bit lines BL1, BL1 for writing data to and reading data from each memory cell. B
L2, BL7, BL8, word lines WL1 and WL2 for selecting each memory cell, and divided cell plate lines DCP1 and DCP2 commonly connected to one electrode of the ferroelectric capacitor of the selected memory cell, A cell plate line CP, transfer transistors T1 and T2 for selectively connecting the cell plate line and each divided cell plate line,
It has a sense amplifier. Memory cells 51, 52,
53 and 54 have memory capacitors C11, C12, C41 and C42 each having a ferroelectric film and MOS transistors T11, T12, T41 and T42. One electrode of each of the memory capacitors C11 and C41 is connected to the divided cell plate line DCP1, and one electrode of each of the memory capacitors C12 and C42 is connected to the divided cell plate line DCP2. The MOS transistors T11, T12, T41, T42 connect the memory cell capacitors C11, C12, C41, C42 and the bit lines BL1, BL2, BL7, BL8 respectively when selected.

Incidentally, in FIG. 1, with respect to the word line WL1,
Divided cell plate line DC controlled by transistor T1
Although an example in which one P1 is arranged is shown, an example of the layout of an actual semiconductor memory device is shown in FIG. In FIG. 2, 11, 1N, K1, and KN respectively represent memory cell groups selected at one time. Each memory cell group includes a memory cell having M ferroelectric capacitors and a divided cell plate line commonly connected to one electrode of the ferroelectric capacitor of each memory cell.
Reference numeral 1 includes M memory cells C111 to C11M and a divided cell plate line DCP11. WL1 to WLN indicate a plurality of N word lines, and BL11 to BL1M and BLK1 to BLKM indicate a plurality of M bit lines, respectively. In this way, a plurality of cell plate lines and a plurality of divided cell plate lines are arranged for one word line, and the cell plate line is decoded by an appropriate signal and selectively activated to select a predetermined memory cell.

Next, the operation of the semiconductor memory device 50 when data "1" is written in the memory cell 51 and data "0" is written in the memory cell 51 will be described. In the following description of the operation, it is assumed that the high level is the Vcc level and the low level is the GND level. Word lines WL1, WL2, bit lines BL1, BL2, BL7, BL8, cell plate line CP, and divided cell plate line DCP
It is assumed that 1, DCP2 are all at the GND level. First, the Vcc level is applied to the bit line BL1 connected to the memory cell 51 for writing "1" data, and the bit line BL7 connected to the memory cell 53 for writing "0" data.
To the GND level. Next, the word line WL1 is set to Vcc to activate the transistors T11, T41 of the memory cells 51, 53, and the bit line BL1,
BL7 and the ferroelectric capacitors C11 and C41 are connected to each other. As a result, an electric field in the positive direction is applied to the capacitor C11, transitioning to the state of S1 in FIG.
No electric field is applied to 41 and there is no state transition. Also,
When the word line WL1 becomes the Vcc level, the transfer transistor T1 connecting the cell plate line CP and the divided cell plate line DCP1 is turned on. Next, the cell plate line CP is set to the Vcc level to raise the divided cell plate line DCP1 to the Vcc level through the transfer transistor. As a result, both electrodes of the memory cell capacitor C11 are set to the Vcc level, as shown in FIG.
Of S2, the reverse electric field is applied to the memory cell capacitor C41, and the state of S3 of FIG. 8 is entered. Next, when the cell plate line is returned to the GND level, the divided cell plate line DCP is passed through the transfer transistor T1.
1 also becomes the GND level, and the memory cell capacitor C11
Is applied with a positive electric field to return to the state of S1 in FIG. At the same time, both electrodes of the memory cell capacitor C41 are GN
The level becomes D level, the electric field between both electrodes becomes zero, and the state transits to the state of S4 in FIG. Next, set the word line WL1 to GND.
Return to the level, bit lines BL1, BL7 and memory cell 5
After releasing the respective connections with 1, 53, bit line B
The write operation is completed by returning L1 and BL7 to the GND level. Immediately after the completion of the write operation, the capacitor C11 of the memory cell 51 is in the state of S1 in FIG.
Since the leak current component exists in the transistor T11, the potential between the capacitor electrodes decreases with time,
It becomes stable in the state of S2 in FIG. Thus, the memory cell 51
8 is set to the state S2 in FIG. 8, and the capacitor C41 of the memory cell 53 is set to the state S4 in FIG. 8 to write data.

Next, a read operation when reading data from the memory cells 51 and 53 will be described. The word lines WL1, WL2 and the bit lines BL1,
BL2, BL7, BL8, cell plate line CP, and divided cell plate lines DCP1, DCP2 are all at the GND level. Further, the capacitor C11 of the memory cell is in the state of S2 in FIG. 8, and the capacitor C41 is S4 in FIG.
It is assumed that

First, by raising the word line WL1 to the Vcc level, the transistor T of the memory cells 51 and 53 is formed.
11 and T41 are connected to the bit lines BL1 and BL7, respectively. At the same time, the transfer transistor T1 connects the cell plate line CP and the divided cell plate line DCP1. Next, when the cell plate line CP is raised to the Vcc level, the divided cell plate line DCP1 is raised to the Vcc level through the transfer transistor T1. An electric field is applied to the capacitors C11 and C41 of the memory cells 51 and 53 in the negative direction.
The state 2 shifts to the state S3, and the capacitor C41 shifts the state S4 to the state S3 in FIG.

Along with this transition, the charge is capacitively divided from the memory cell capacitor into the bit lines, and the bit lines BL1 and B1.
A potential appears at L7. The level of "1" data corresponding to L1 of FIG. 9 appears on the bit line BL1 and the bit line BL7
Shows the level of "0" data corresponding to L2 in FIG. By comparing this with an appropriate reference level in the sense amplifier circuit, it is determined as "1" data or "0" data, and the amplified data is read.

As described above, the transfer transistor T
Since the cell plate signal selectively drives only the memory cell capacitors connected to the divided cell plate line through 1, the load capacity of the cell plate signal becomes significantly smaller than that when the divided cell plate line is not used. It is possible to reduce current consumption for driving the signal. In addition, the cell plate signal can be operated at high speed.

In the above description, the high level of the word line is set to Vc.
Although the level is set to the c level, when the word line level is set to the Vcc level, when the Vcc is applied to the bit line and "1" data is written, the drain and gate of the transfer transistor are set to the same Vcc level, so that the source potential connected to the capacitor is It is applied only to a level lower than Vcc by the threshold voltage (Vth). As a result, the voltage written in the capacitor is effectively reduced, narrowing the operating voltage range. As a countermeasure against this, by using an internally boosted level (referred to as Vpp level) as the word line level, the transistors T11, T41, T1 of the memory cell are used.
2, T42 and the transfer transistors T1 and T2 can be increased in gate potential to write the power supply voltage Vcc to the memory cell capacitor. As a result, the operating power supply voltage range can be expanded. A transistor whose threshold voltage is set lower than other transistors is a transfer transistor T.
1 and T2, the potential drop in the transfer transistor can be reduced and a higher potential can be applied to the memory cell capacitor, and the transistor having a low threshold voltage can be used to divide the cell plate line. Can be driven at higher speed.

A second embodiment of the semiconductor memory device of the present invention will be described. This will be described with reference to FIG. In FIG. 3, a semiconductor memory device 60 includes memory cells 61, 62, 63 and 64 for storing 1-bit data, and bit lines BL1 for writing data to and reading data from each memory cell.
BL8 and word line WL for selecting each memory cell
1T, WL1B, WL2T, WL2B, divided cell plate lines DCP1 and DCP2 commonly connected to one electrode of the ferroelectric capacitor of the selected memory cell, and the cell plate line and the divided cell plate line are selectively connected. It has transfer transistors T1N, T1P, T2N, T2P, a cell plate line CP, and a sense amplifier. The memory cells 61, 62, 63 and 64 are memory capacitors C11, C12, C81 and C having ferroelectric thin films, respectively.
82 and MOS transistors T11N, T11P, T1
2N, T12P, T81N, T81P, T82N, T8
2P, one electrode of each of the memory capacitors C11 and C81 is connected to the divided cell plate line DCP1, and one electrode of the memory capacitors C12 and C82 is connected to the divided cell plate line DCP2. Memory capacitors C11, C81, C12, C82
The other electrode of is connected to the bit line via a transistor. Capacitor C11 and bit line BL1
Is an N-type transistor T11N and a P-type transistor T11
P is connected to the bit line BL1 and is connected to the transistor T1
The gate of 1N is controlled by the word line WL1T, and the gate of the transistor T11P is controlled by the word line WL1B to which a complementary signal is applied to the word line WL1.

Similarly, in the other memory cells, the capacitors and the bit lines are connected to two complementary transistors, and the gates of the respective memory cells are controlled by complementary signals. The cell plate signal CP and the divided cell plate signal line DCP1 are connected by an N-type transistor T1N and a P-type transistor T1P, and the gates of the respective transistors are word lines WL.
Controlled by 1T and WL1B, the cell plate line CP and the divided cell plate line DCP2 have two transistors T2.
They are connected by N and T2P, and the gates of the respective transistors are controlled by word lines WL2T and WL2B.

Next, the operation will be described. A series of write and read operations is the same as in the first embodiment, but the signal of the word line for selecting the memory cell is the complementary signal W.
L1T and WL1B are provided, and an N-type transistor and a P-type transistor for connecting the bit line and the ferroelectric capacitor, and an N-type transistor and a P-type transistor for connecting the cell plate line and the divided cell plate line, respectively, are provided. Control.

When writing "1" data to the memory cell 61, after applying the Vcc level to the bit line BL1,
By setting the word line WL1T to Vcc level and WL1B to GND level, the transfer transistors T11N, T
11P is turned on, and the memory cell capacitor C11
Is applied with the Vcc level. At the same time, T1N and T1P that connect the cell plate line and the divided cell plate line are also turned on, and if the cell plate line CP continues to be Vcc, the divided cell plate line also rises to Vcc as a high level. In this way, the Vcc level can be applied to the memory cell capacitor without boosting the word line signal.

A third embodiment of the semiconductor memory device of the present invention will be described. This will be described with reference to FIG. In FIG. 4, a semiconductor memory device 70 includes memory cells 71, 72, 73 and 74 that store 1-bit data, and bit lines BL1 and BL2 for writing data to and reading data from each memory cell. , BL7,
BL8, word lines WL1 and WL2 for selecting each memory cell, a divided cell plate line DCP commonly connected to one electrode of the ferroelectric capacitor of the selected memory cell, and a cell plate line CP, It is provided with transfer transistors T1 and T2 that selectively connect the cell plate line and each divided cell plate line, and a sense amplifier. The memory cells 71, 72, 73 and 74 are memory capacitors C11, C22 and C1 each having a ferroelectric film.
7, C28 and MOS transistors T11, T22, T1
7 and T28. Memory capacitors C11, C
One electrode of each of 22, C17 and C28 is connected to the divided cell plate line DCP, and the MOS transistors T11, T22, T17 and T28 are connected to the memory cell capacitors C11, C22, C17 and C28 and the bit line BL.
1, BL2, BL7, BL8 are connected when selected. In FIG. 4, one cell plate line and one divided cell plate line are shown, but in the actual semiconductor memory device as in the first embodiment, a plurality of cell plates arranged in an array as shown in FIG. There are lines and multiple split cell plate lines.

The write operation and the read operation are similar to those in the first embodiment, but the memory cell group selected by one word line is selected by another adjacent word cell group. By sharing the divided cell plate on the circuit and in the layout, the layout area can be reduced. When the memory cells 71, 73 are selected by the word line WL1 and the cell plate line CP is raised to the Vcc level for the write operation or the read operation, the selected memory cells 71, 7
In the memory cell capacitors C11 and C17 of No. 3, since the transfer transistors T11 and T17 are in the ON state, the potential between the bit line and the divided cell plate line is applied between the electrodes of the ferroelectric capacitor. The memory cells 72 in the non-selected state,
The memory cell capacitor 74 is a transfer transistor T2.
Since T2 and T28 are in the OFF state, they are not applied between the electrodes of the ferroelectric capacitor regardless of the potential of the divided cell plate line, the polarization state does not change, and the memory state is maintained.

A fourth embodiment of the semiconductor memory device of the present invention will be described. This will be described with reference to FIG. This embodiment is an embodiment in which the memory cell structure is the 2T2C type memory cell structure described above in the circuit structure of the third embodiment shown in FIG.

A fifth embodiment of the semiconductor memory device of the present invention will be described. This will be described with reference to FIG. In the figure, M rows of memory cells 11 to M1 in the horizontal direction and 11 to 1 in the vertical direction
Memory cells in N columns up to N are shown. WL1 to WLN represent a plurality of N word line signals, and BL1 to BLM represent M bit lines. Although not shown in the figure, it is assumed that the circuit blocks shown in FIG. 6 are arranged in an array.
In the above-described third embodiment, the memory cells selected by the two adjacent word lines share the divided cell plate line, and the layout area is reduced. In this embodiment, the memory cell group selected by any of the word lines WL1 to WLN shares one divided cell plate line DCP. The gate 1 calculates the logical sum of the word lines WL1 to WLN, and when any one of these word lines is selected, the transfer transistor T1 becomes conductive and the divided cell plate line DCP is driven.

[0041]

According to the present invention, the driving load capacitance of the cell plate signal wiring is reduced by dividing and driving the cell plate signal line in units required for reading and writing, reducing current consumption, high speed operation, and reducing layout area. Is realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a layout of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a conventional semiconductor memory device.

FIG. 8 is a state transition diagram showing a relationship between a voltage applied to a ferroelectric substance and self-polarization of the ferroelectric substance.

FIG. 9 is a timing chart showing a read operation of the conventional semiconductor memory device.

FIG. 10 is a circuit diagram showing a conventional semiconductor memory device.

FIG. 11 is a diagram showing an array arrangement of the semiconductor memory device.

FIG. 12 is a diagram showing a different array arrangement of a conventional semiconductor memory device.

[Explanation of symbols]

50 semiconductor memory device 51, 52, 53, 54 memory cell BL1, BL2, BL7, BL8 bit line C11, C12, C41, C42 capacitor CP cell plate line T1, T2, T11, T12, T41, T42 transistor WL1, WL2 word Line DCP1, DCP2 Cell plate line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/108 27/10 451 7210-4M

Claims (12)

[Claims] 1. A plurality of memory cells each having a capacitor formed of at least a ferroelectric film are connected to a common divided cell plate line, and the divided cell plate line is connected to a cell plate line via a transistor. A semiconductor memory device characterized by forming a memory cell group. 2. The memory cell group is connected to another memory cell group having a word line as a common line in a row direction, and the memory cell group has a memory cell group having a cell plate line as a common line in a column direction. 2. The semiconductor memory device according to claim 1, wherein the memory cells are connected and formed in a matrix. 3. A first capacitor having one electrode connected to a divided cell plate line, and a memory cell connected to a bit line and a word line via a first transistor at the other of the first capacitors. , A memory cell having the same configuration as the memory cell is connected using the divided cell plate line as a common line, and the divided cell plate line is connected to a second transistor,
A semiconductor memory device, wherein the second transistor is connected to the word line and a cell plate line. 4. The semiconductor memory device according to claim 3, wherein the threshold voltage of the second transistor is set lower than that of the first transistor. 5. The semiconductor memory device according to claim 3, wherein a circuit for boosting the word line potential to a voltage higher than a power supply voltage supplied to the semiconductor memory element is connected. 6. A first complementary transistor connected to a common bit line is connected to at least one electrode of a capacitor formed of a ferroelectric film, and the first complementary transistor has two electrodes. A second complementary transistor connected to a word line, the other electrode of the capacitor being connected to the divided cell plate line, and the divided cell plate line, the two word lines and the cell plate line connected to each other; A semiconductor memory device comprising: 7. The semiconductor memory device according to claim 6, wherein a complementary signal of a signal applied to the other of the word lines is input to one of the word lines. 8. A memory cell having a capacitor formed of a ferroelectric film is connected to a word line, and the memory cells connected between two specific word lines are electrically common. A semiconductor memory device, wherein the divided cell plate line is connected to the divided cell plate line, and the divided cell plate line is connected to the cell plate line through a transistor. 9. A memory cell having a capacitor formed of a ferroelectric film is connected to a word line and a bit line, and is provided between two specific word lines and two specific bit lines. 2. The semiconductor memory device according to claim 1, wherein the memory cells connected to the memory cell are connected by an electrically common divided cell plate line, and the divided cell plate line is connected to the cell plate line through a transistor. 10. Two specific word lines and two specific word lines
10. The semiconductor memory device according to claim 9, wherein the number of the memory cells connected to the bit line of the book is two. 11. A specific two said word lines and a specific two
10. The semiconductor memory device according to claim 9, wherein the number of the memory cells connected between the bit lines of the book is four. 12. A memory cell having a capacitor formed of a ferroelectric film is connected to a word line, and the memory cells connected between two specific word lines are electrically common. The divided cell plate lines are connected to each other, the divided cell plate lines are connected to a cell plate line through a transistor, and the transistor is connected to a logic circuit which generates a logical sum of the two word lines. A semiconductor memory device characterized by the above.