JPH07219721A - Interface device and method - Google Patents

Abstract

PURPOSE:To validate synchronizing signal pulse width at every host or corresponding to an application and to improve noise resistance. CONSTITUTION:A transmission part 51 is constituted of a circuit including a driver for signal output and a pull-up resistance. A reception part 52 receives a signal transmitted from the transmission part 51. A signal width detection block 53 detects only a signal having width larger than a value which is set as an effective signal. In the signal width detection block 53, printer CPU which is not illustrated sets the width of a signal for detection in a signal width setting part 53a as the effective signal through a data bus. A signal detection part 53b detects the signal width of the inputted signal. A comparison part 53c compares a value which is set in the signal width setting part 53a with that detected in the signal detection part 53b. When inputted signal width is larger than the setting value, the input signal is outputted as a significant signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device and method used for data communication.

[0002]

2. Description of the Related Art In a conventional interface device such as a parallel interface which is often used in printers and the like, measures against noise are taken in order to improve the reliability of communication. As a countermeasure against such noise, a so-called low-pass filter of a differentiating circuit including a capacitor, a resistor, etc., or an integrating circuit is used in the signal receiving unit,
The noise is below the time constant of the circuit.

Further, for example, in a transmission system using bidirectional signal property, an element (transmission element or reception element) which becomes active in synchronization with transmission / reception timing is selected by switching a transmission element and a reception element with a control signal. decide. In such an interface device, a Schmitt trigger element is used as a receiving element, and a Hi / Lo level determination at the time of input is provided with a hysteresis characteristic to prevent noise. Further, as a measure against noise, there is also a method of forming a low-pass filter by a differentiation / integration circuit provided with a capacitor and a resistor, an inductance, or the like in the preceding stage of the receiving element, and filtering noise having a time constant equal to or less than that circuit. Furthermore, in the model for high-speed transfer, a so-called "active terminator", which is a termination matching device that outputs a stable output corresponding to a signal input, is provided. The active terminator improves noise resistance against reflection of an input signal and external noise.

[0004]

However, in the above conventional noise countermeasure method, in the configuration in which the low-pass filter is formed in the receiving section, when the time constant changes due to the change of the connecting cable or the change of the connecting host computer. However, there is a problem that the pulse width of the waved noise also changes, and the initial effect cannot be obtained. In addition, there is no effect for noise with a certain width or more, and incorrect data may be input.

Further, in the above-mentioned interface using the bidirectional signal line, if the Schmitt trigger element is used as the receiving element, a sufficient effect as a noise filter cannot be obtained only by the hysteresis difference. or,
In order to deal with this, when a low-pass filter is formed in the preceding stage of the receiving element, there arises a problem that the data transfer rate becomes slow if the time constant is increased to sufficiently take measures against noise. On the other hand, if the time constant of the low-pass filter is reduced in order to realize high-speed data transfer, noise resistance will be reduced. Further, mounting an active terminator on a product increases the number of parts such as driver elements, which leads to an increase in product cost. Further, when connecting to the signal line, a special connector that can be connected in a stack or a spare connector for a terminator is required, which makes setting difficult and increases the total cost.

Therefore, in order to solve the above problems, the present invention provides an interface device and method which make effective the sync signal pulse width corresponding to each host or application and improve the noise resistance. The first purpose is to provide.

A second object of the present invention is to provide an interface device and method capable of validating data corresponding to a predetermined signal during a data reception period and enhancing noise resistance. To do.

A third object of the present invention is to provide an interface device and method for enhancing noise resistance by setting a slice level higher than the Schmitt level of a receiving element when receiving data from a bidirectional signal line. Especially.

Further, another object of the present invention is to make it possible to stabilize the input signal by applying a footback to the input signal when the input slice level is exceeded for a certain time, and to improve resistance to noise. is there.

Still another object of the present invention is to improve noise resistance and speed up signal transfer in various interfaces using a microcomputer, in which signal lines have a bidirectional input / output function. An interface device and method are provided.

[0011]

[Means for Solving the Problems] and

The interface device according to the present invention for achieving the above-mentioned first object is an interface device for transferring data, and is a setting means for setting a set value indicating a pulse width and a signal is inputted from an external device. Input means for determining, and a determining means for determining the signal as a significant signal when the signal width of the signal input by the input means is larger than the pulse width indicated by the set value set by the setting means; And a processing unit that executes a predetermined process using a signal determined to be a significant signal.

Further, an interface method according to the present invention for achieving the above object is an interface method for data transfer, comprising a setting step of setting a set value indicating a pulse width and a signal input from an external method. An input step, a determination step of determining the signal as a significant signal when the signal width of the signal input by the input step is larger than the pulse width indicated by the setting value set by the setting step, and the determining step And a processing step of executing a predetermined process using a signal determined to be a significant signal.

According to the above-mentioned configuration, the pulse width for judging as a significant signal can be set by the setting means, the data transfer is performed in a state suitable for the interface circuit of the other side, and the noise resistance is improved and the data resistance is improved. Transfer rate is maintained.

The interface device of the present invention which achieves the above-mentioned second object is an interface device for transferring data, and is a setting means for setting a set value indicating a pulse width, and an input signal from an external device. Input means for inputting the input signal, determination means for determining the input signal as a significant signal when the signal width of the strobe signal is larger than the pulse width indicated by the set value set by the setting means, and Masking means for performing a masking process on the input signal during a process related to the input signal after it is determined that the input signal is a different signal.

Further, an interface method of the present invention for achieving the above-mentioned other object is an interface method for data transfer, which comprises a setting step of setting a set value indicating a pulse width and an input signal from an external method. An input step of inputting, a determination step of determining the input signal as a significant signal when the signal width of the strobe signal is larger than the pulse width indicated by the set value set by the setting step, and a significant step by the determination step. And a mask step of performing a mask process on the input signal during a process related to the input signal after it is determined to be a signal.

According to the above configuration, it becomes possible to mask the data received during the period other than the period in which the data can be received, and the noise resistance is remarkably improved.

Further, an interface device of the present invention for achieving the third object is an interface device for transferring data by using a bidirectional signal line, and an input element of the bidirectional signal line at the time of signal input. And an input part of the output element, and a connecting means for connecting the output part of the output element and the input part of the input element via a resistance value.

Further, an interface method of the present invention which achieves another object is an interface method for transferring data by using a bidirectional signal line, wherein the output of the input element of the bidirectional signal line is output at the time of signal input. And a connection step of connecting the output section of the output element and the input section of the input element via a resistance value.

With the above structure, in the state of connection by the connecting means or the connecting step, a change in the signal level input through the bidirectional signal line is reverse biased by the output of the output element and the input element is changed. Applied to. Therefore, the threshold level of the input element is changed.

[0020]

【Example】

<Embodiment 1> First, a general parallel interface circuit will be described with reference to FIGS. 1, 2, 3 and 4.

FIG. 1 is a diagram for explaining the circuit configuration of a general data transfer interface. In the figure, reference numeral 1 denotes a host computer, which prints print data and the like on the printer 3
Send to. A cable 2 connects the host computer 1 and the printer 3. A printer 3 receives print data from the host computer 1,
Printing on the recording medium is executed based on the print data.

The signal name XSTB is a synchronizing signal for the data signals from d0 to d7, and indicates that the signals from d0 to d7 are valid. XACK and BSY are a response signal and a status signal from the printer 3, respectively.
That is, the response signal XACK is a data reception response signal from the printer, and BSY is a signal indicating that the printer cannot receive data. The flip-flop (FF1) transmits the input of the XSTB signal to the printer CPU (not shown). In addition, the register (LR1) is a synchronization signal (XSTB).
Holds the data when the data is valid.

The resistor (rh1) is a pull-up resistor of the output driver (drh1) of the host computer 1.
The resistor (rp1) is a pull-up resistor for reception on the printer 3 side. Driver for host computer 1 (drh1)
The synchronization signal (XSTB) sent via the cable reaches the receiving input element (rep1) via the cable 2 and the diving resistor (rd1) on the printer 3 side. The input terminal of the input element (rep1) is grounded by the capacitor (c1).

FIG. 2 is a diagram showing an equivalent circuit of charging / discharging at the time of transition of an input signal in the printer receiving section. The input point vi of the input element (rep1) of the printer 3 is ((rh1 × rp1) / (rh1 + rp1) + rd1) with respect to the rising input waveform of XSTB as shown in (a) and (b) of FIG.
It is charged with a time constant of × (c1). On the other hand, when rising, discharge is performed with a time constant of (rd1) × (c1).

As described above, in a general interface circuit, the time constant for an input / output signal is uniquely determined by the resistance value and capacitance value of each part.

Generally, the pull-up resistors (rh1) in the host computer have different resistance values, so that the charging time varies depending on the host computer. Therefore, it is necessary to set the circuit constant in the printer 3 on the receiving side in order to secure a time constant with which sufficient noise resistance can be obtained for all host computers.

Next, the time constant in the communication circuit will be described. 3 and 4 are diagrams for explaining the input signal waveform to the input element (rep1) and the output waveform from the input element (rep1). FIG. 3 shows the signal waveform when the input signal falls. Represents the signal waveform at the time of rising. Here, in order to remove the noise that bounces beyond the range of the input level as in the period T2, it is necessary to set a long time constant as shown by the broken lines in FIGS. 3 and 4.

As described above, since it is necessary to set the time constant at the receiving printer so that sufficient noise resistance can be obtained for any host computer, the time constant is set too long for a certain computer. This may cause the data transfer rate to be reduced more than necessary. Further, although the time constant is set to be extended to the end time of T2, it is completely invalid for noise having a width exceeding this set value.

Next, an embodiment of the interface device of the present invention will be described.

FIG. 5 is a block diagram showing the functional arrangement of the interface circuit of this embodiment. In the figure, 51
Is a transmitter, and is composed of a circuit including a driver for signal output and a pull-up resistor, for example. Reference numeral 52 denotes a receiver, which receives the signal transmitted from the transmitter 51. A signal width detection block 53 detects only a signal having a width equal to or larger than a set value as a valid signal. In the signal width detection block, 53a is a signal width setting unit, and the printer CPU (not shown) sets the width of the signal for detection as a valid signal via the data bus. 5
A signal detector 3b detects the signal width of the input signal. The comparison unit 53c compares the value set in the signal width setting unit 53a with the signal width detected by the signal detection unit 53b, and outputs the input signal if the input signal width is equal to or larger than the set value. . A buffer 54 holds the input strobe signal. The data held in the buffer 54 is stored in the printer CP which has detected the strobe signal.
Reset by U.

Next, a specific circuit configuration of the first embodiment will be described.

FIG. 6 is a diagram showing a circuit configuration of the interface device of the first embodiment. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted here. In Fig. 6, diving resistance (rd1)
Are arranged between the capacitor (c1) and the input element (rep1). This is because the (rd1) × (c1) differentiation / integration circuit of the conventional example with respect to the input element (rep1)
The time constants of the impedance components (Z cable) and (c1) (not shown) of the cable 2, which are ignored in the above equation, are obtained. Therefore, compared with the conventional example, harmonic noise of several tens of times or more is obtained. Has only the effect of low bass.
That is, the combination of the diving resistor rd1 and the capacitor c1 in FIG. 6 does not have the meaning of waveform shaping (low-pass filter) until the end time of T2 as shown in FIG. 1, and has the meaning as the time constant of FIG. rare.

In FIG. 6, for the input from the cable 2, all noise and signals are received by the input element (rep1) and input to the signal width detection block 53 at the next stage. The signal width detection block 53 has a two-stage configuration D-type flip-flop. The two-stage D-type FF (DF1.DF
In 2), the Q output of the second stage (DF2) is generated when the FF of the first stage is continuously input with a length corresponding to two pulses of the operating frequency clkn. FIG. 7 is a diagram showing the output timing of the two-stage D-type FF. First, the strobe signal (XST
When the clock (clkn) rises with the B) turned on, the first flip-flop (DF
1) turns on the Q output. Then, at the next rising edge of the clock pulse, the flip-flop (DF
The output of 2) shifts to ON.

Clkn is set in the latch register (LR2) from the data bus of the printer CPU (not shown),
The output of the latch register (LR2) controls an analog switch (equivalently, it is composed of the drivers dr0 to dr3 and the switches S0 to S3, and the output of the driver opens and closes the switch). , Frequency division counter (COU
Since the output (Q0 to Q3) of NT1) is selected to be multiplied by the frequency division of clk0, only a signal having a signal width of two or more pulses of clkn is multiplied is detected as a strobe signal. In addition, since those below that are not detected as signals, they can be removed as noise.

As described above, the signal width detection block 53 can almost completely remove noise having a pulse width equal to or smaller than the set value. Next, a countermeasure against noise having a pulse width equal to or larger than the set value will be described.

FIG. 8 is a timing chart showing the data transfer procedure of the first embodiment. After receiving the data as shown in the timing chart of FIG. 8, the host receives XA of the received signal.
During the [next data reception prohibition period] until CK is returned, the next data cannot be input due to the handshake in the normal data reception protocol. Therefore, by multiplying the data input signal gate (G1) of FIG. 6 by [mask] during this period, the output from the data input signal gate (G1) is prohibited and the normal input is prohibited. However, when data having a width of XSTB equal to or larger than the specified value (signal width set in the latch register (LR2)) is input, a signal output is generated from the data input signal gate (G2) to cause the printer CP
Cause U to generate an interrupt. Then, in the interrupt process, the printer CPU starts collation of the data input from the data bus.

FIG. 9 is a diagram for explaining the data transfer procedure (handshake) of the first embodiment. As shown in the figure, after the data is set on the signal line from the host computer, the strobe signal (XSTB) is input.
Upon receiving this strobe, the printer takes in data and executes a predetermined process. After that, the printer outputs an acknowledge (XACK) to the host computer. The host computer receives this acknowledge,
The process moves to the next data transmission process. In the printer, the strobe signal is masked during the period from the reception of the strobe to the return of the acknowledge to prevent the operation due to external noise. However, a strobe corresponding to a special instruction or the like is detected, and a dedicated interrupt signal is generated for the strobe generated during the mask period.

The data signal input gate (G
The mask signals 1) and (G2) may be generated by the printer CPU as software, or may be generated as hardware by an appropriate logic circuit.

The above-mentioned interrupt does not occur in a normal data reception protocol, but in the case of a special code such as a data cancel command, which can be transmitted regardless of the confirmation of reception of the XACK signal on the host side, the interrupt is not generated. Occurs. Then, when the received data verified by the occurrence of the interrupt is such a special command, the operation corresponding to the command is executed. On the other hand, if it is not special data, the received data is simply ignored as noise having a long pulse width. In this way, it is possible to prevent the influence of long-width noise and prevent the input of erroneous data.

As described above, according to the interface device of the first embodiment, an effective signal is generated according to a change in noise or signal waveform caused by circuit constants or the like of the connected host computer and communication cable. It is possible to appropriately set the confirmation time for determining that
Therefore, there is an effect that the reliability of data transfer can be maintained without lowering the data transfer speed more than necessary. Further, according to the first embodiment, since the time interval for determining whether the arm is a valid signal output arm can be set by the printer CPU, the confirmation time can be easily switched.

Further, by masking the next data reception prohibition period during the transmission of the BSY signal, the reliability of data transfer is further improved, and the XSTB in the mask is also received by the generation of the special instruction. It is possible.
In general, in the data reception handshake, the time for fixing the data by the synchronization signal is about 1%, and 99% is spent for the processing after the data acquisition. Therefore, by masking the next data after receiving the data until the data can be received, the reliability is increased 99 times even with respect to external noise having a signal width equal to or larger than the set value. Further, since the noise pulse width confirmation circuit allows normal impulse noise to be almost completely ignored, the input of erroneous data due to noise is significantly reduced.

<Embodiment 2> In the first embodiment, whether or not the input XSTB signal is significant is confirmed by changing the clock width, but the present invention is not limited to this. In the second embodiment, an example of the modification will be described.
That is, in the second embodiment, the signal width of the input strobe signal is determined by the count number using a clock signal having a constant cycle.

FIG. 10 is a diagram showing a circuit configuration example of the interface device according to the second embodiment. In the figure, elements having the same functions as the elements in the circuit configuration of the first embodiment are designated by the same reference numerals, and description thereof will be omitted here.

The signal width detection block 53 'checks the signal width of the strobe signal (XSTB) by the counter (COUNT) and the latch register (LR2') to determine whether or not the signal is significant. The printer CP is connected to the latch register (LR2) via the data bus.
A predetermined value is set by U. Counter (COUNT2)
Counts the pulse of the clock (CLK) while the pulse input from the signal line of XSTB is on.
The ON state of the input pulse indicates that the clock (CL
When the number of pulses of (K) continues for a predetermined number of pulses, it is regarded as a significant signal, and the signal is output to the buffer FF1.

That is, the input signal input via the receiving element rep1 is connected to the enable terminal of the counter (COUNT2) and the gate (Gr). Therefore, when the input shifts from the on state to the off state due to noise or the like, a signal is input to the counter setting terminal of the counter (COUNT2) and the count value is reset. When the noiseless input continues for a predetermined time or longer, it is output as a strobe signal to the buffer (FF1), and the gate (G1) with data input is activated.

The masking process in the next data input prohibition period and the process for the abnormal interrupt during masking are the same as those in the first embodiment, and the description thereof is omitted here.

As described above, the same effect as that of the first embodiment can be obtained even with the configuration of the second embodiment.

As described above, according to the first and second embodiments, in the parallel interface often used for printers and the like, selection is made according to the type of the host computer or the printer driver used by the application program. With the printer control program, the recognition width of the pulse width for the data reception synchronization signal (strobe signal) can be changed. Also,
For input other than when data is received, an interrupt is generated to check the validity of the input data, and the input of data due to noise is blocked to improve the reliability of data reception.

<Third Embodiment> In the third embodiment, an interface device using bidirectional signal lines will be described.

First, a general interface device will be described.

FIG. 11 is a diagram showing a general interface circuit. In FIG. 11, the bidirectional signal line includes an output terminal of the transmission driver (drv) and a reception element (re).
The input terminal of c) is connected. The output control line of the transmission driver (drv) is controlled by a CPU (not shown).
It is performed on / off by a control signal from the above. For example, in order to avoid a collision with an output signal from a host device (external device) at the time of signal input and an influence on the own input signal, the transmission driver (drv) is controlled to be in a cutoff state.

Here, the input level of the input element is [Lo ·
max], the maximum level of Lo input becomes [Hi · min]
The minimum level of Hi input is specified in [Lo ・ mi
The level between [n] and [Hi · min] is an undefined area, and its output state is not guaranteed.

At the time of receiving a signal in the above circuit, [reflected wave] due to the mismatch between the impedance of the signal line line and the received impedance, or [noise] as shown in FIG. 3 due to inductive coupling, electrostatic coupling or the like is included. [Hi] to [L
The operation when there is a transition input signal to the [o] signal will be described.

The input signal is [Lo ·
max] level (U1 in Fig. 3) [T1]
The signal input within the time of is recognized as [Lo].
However, since the signal within the time [T2] that exceeds the reference level reaches the indefinite region, it may be input as the [Hi] input. Further, the input signal in the time after [T2] is less than U1, and is input again as [Lo]. As a result, the output of the receiving element (rec) may become unstable as shown in the output waveform of FIG.

Further, FIG. 4 described above is a diagram when the input signal transits from [Lo] to [Hi]. As above
The input signal level becomes [Hi ・ mi
n] (that is, U2), the output waveform of the input element (rec) is unstable in the waveform when it vibrates.

In FIG. 11, a Schmitt trigger element is used as the input element (rec) in order to avoid the above-mentioned problems, but in general, sufficient reliability cannot be obtained. Therefore, as shown in FIG. 12, there is known a method of providing a differentiating / integrating circuit (commonly called a low-pass filter) composed of a capacitor (c) and a resistor (r) in the input part. In this method, the time constant established by the capacitor (c) and the resistor (r) is delayed until the end of [T2] in the waveform diagrams shown in FIGS. 3 and 4, so that the output of the receiving unit is stable. You can get the output. However, when the vibration cycle for raising and lowering the level is long or the number of vibrations is large, it is necessary to lengthen the time constant of the filter to a length that stabilizes the delay time. Therefore, it takes time to recognize the data reception. Furthermore, when a response is required to the input data, the response time is also delayed, resulting in a decrease in communication speed.

Further, FIGS. 13A and 13B show an inductor (L) inserted in the above-mentioned differentiating circuit.
The function of the low-pass filter configured in this way is similar to that described above, and detailed description thereof will be omitted.

Further, as a measure against noise as described above, there is a method using an active terminator. FIG. 14 is an example of a known [bus latch] basic circuit, and FIG. 15 is an example of a known [bus latch compatible with extended noise time width] application circuit. [Termination element unit] or built-in circuit It is used as a circuit.

Next, an embodiment of the present invention is shown in FIG. 3 and Table 1, and the configuration and operation of the [bus latch] used as the termination element of the circuit will be described.

FIG. 16 is a diagram showing a configuration example of the interface circuit of the third embodiment. In addition, FIG. 17 is a diagram showing a switch state of the analog switch in the third embodiment. In both figures, when data is input, only the analog switch (sw3) is turned on and the others are turned off. Therefore, when inputting a signal, the input element (rec) corresponding to the input signal
Is connected to the output driver (drv) input terminal (i) through the analog switch (sw3), and the output of the output driver (drv) is input to the input (rec) via the resistor (r). Connect to (i). In this way, a configuration equivalent to that of the [bus latch] circuit shown in FIG. 14 is obtained. When outputting data, analog switch (sw
1) and (sw2) are turned on and (sw3) is turned off. Therefore, a signal is input to the output driver (drv) from the output signal line, and the output from the output driver (drv) is directly connected to the cable.

Next, the operation of the above-mentioned circuit of FIG. 16 at the time of reception (effect on noise resistance by forming an active terminator) will be described.

FIG. 18 shows an extracted circuit formed when the interface circuit of FIG. 17 receives data. As shown in the figure, for example, immediately after the input signal shifts from Hi to Lo, Hi (= Vcc) is output from the output driver (drv). A voltage of Lo + (Vcc-i) is applied to the input terminal of the input receiver (rec) where the current flowing out by the output of the output driver (drv) is i. Therefore, in order for the input receiver (rec) to detect the Lo signal, Lo + (Vcc-i × r) ≦ Lo ·
It must be max, the threshold level is expanded, and noise resistance is improved. Also, the input receiver (re
Once c) detects Lo, the output driver (dr
v) output is stable at Lo, input receiver (rec)
The voltage value of the input terminal of is also stabilized at the Lo level.

The above operation will be further described using an equivalent circuit. FIG. 19A is a diagram showing an equivalent circuit when the signal level changes from Hi to Lo in the interface circuit of the third embodiment. As can be seen from the figure, the input voltage Vi to the input receiver (rec) is the output signal voltage Vo from the host and the output driver (dr) of the receiving unit.
v) output voltage VH (as described above, the output of the output driver (drv) is Hi at the time of transition from the input signal level Hi to Lo), the connection resistance r
And the signal cable impedance Zo (= r.lin
e). (B) is a rewrite of the equivalent circuit shown in (a) in a more understandable manner, and the input voltage vi is represented by Vi = ((VH−Vo) / (Zo + r)) × Zo + Vo.

When the potential Vi applied to the input receiver (rec) becomes lower than [Lo · max], the output from the input receiver (rec) is inverted.

Similarly, FIG. 20A is a diagram showing an equivalent circuit when the signal level changes from Lo to Hi in the interface circuit of the third embodiment. In addition, in (b) of the same drawing, the equivalent circuit of (a) is further rewritten in order to make the voltage Vi applied to the input receiver (rec) easy to understand. Similar to the above, the input voltage V
i is the output signal voltage Vo from the host and the output voltage VL from the output driver (drv) of the reception unit (in the figure, when the input signal level shifts from Lo to Hi, the output driver (drv) ) Output is Lo), connection resistance r, and signal cable impedance Zo
It is determined by (= r · line). That is, the input voltage Vi to the input receiver (rec) is represented by Vi = ((Vo−VL) / (Zo + r)) × r + VL.

When the voltage Vi applied to the input receiver (rec) becomes higher than [Hi · min], the output from the input receiver (rec) is inverted.

As described above, when the voltage of the input signal changes, a reverse voltage is applied to the resistor r by the transmission driver with respect to the changed input signal, and the reverse voltage to the voltage level at point Vi is applied. You will be biased. Therefore, as a result, the threshold level is increased, and the reliability of noise can be increased. Furthermore, the input receiver outputs L output according to the input signal.
When changing from o to Hi or from Hi to Lo, the output of the output driver also changes in response to this, and plays a role of stabilizing the input voltage of the input receiver (rec).
Noise resistance is further enhanced.

In the above circuit, when a bidirectional signal is used as an output line, analog switches (swl), (s)
By turning on w2) and turning off (sw3),
Both ends of the resistance [r] are short-circuited, and the output of the output element is (sw
output via l). At this time, analog switch (s
Although the resistance component of w1) is intervening, it can be ignored because it is sufficiently smaller than the signal line impedance and the output impedance.

As described above, according to the third embodiment,
In an interface circuit using a bidirectional signal line, it becomes possible to form an active terminator using an output driver, which improves reliability against noise, simplifies the circuit, and reduces the cost.

Also, by inserting a delay element or a delay circuit between the input receiver (rec) and the output driver (drv) and setting the time width of [T1] shown in FIG. 3, "H" → It becomes possible to limit the pulse width of "L", "L" → "H", and the nozzle resistance is further improved. This constitutes the "bus latch with delay" circuit shown in FIG.

FIG. 21 is a diagram showing a change in the input / output state of each element with respect to a change in the input signal in the bus latch with delay described above. FIG. 21 (a) shows a case where the input signal changes from Hi to Lo, b) shows the case where the input signal changes from Lo to Hi. As is clear from the figure, the delay time until signal detection when the input signal changes from Hi to Lo is td1, and the delay time when the input signal changes from Lo to Hi is td2.

Regarding the circuit configuration of the third embodiment,
It goes without saying that various modifications are possible. Hereinafter, an example thereof will be described.

FIG. 22 is a diagram showing a modification of the interface circuit of the third embodiment. In the figure, two diodes and a resistor are connected, and it becomes possible to give different amounts of change in the threshold level when the input signal rises and falls. Therefore, the threshold level can be changed more appropriately, and the noise resistance is improved.

As another modified example, FIGS.
As shown in, a circuit using a relay instead of the analog switch is shown. FIG. 23 shows the analog switch portion of the circuit configuration of FIG. 21 realized by a relay.
4 is the one in which the analog switch portion of the circuit configuration of FIG. 16 is realized by a relay. Also in this case, the same operation and effect as described above can be obtained.

As described above, according to the third embodiment and the various modifications, the noise resistance is improved in the various interfaces using the microcomputer and the like, in which the signal line has a bidirectional input / output function. Thus, it is possible to speed up the signal transfer. Further, since the active filter for improving noise resistance is composed of the input element and the output element of the signal line, the circuit configuration is simplified.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0077]

As described above, according to the present invention,
For example, the synchronizing signal pulse width corresponding to each host computer or application can be treated effectively, and noise resistance can be improved.

Further, according to another configuration of the present invention, it becomes possible to validate the data corresponding to the predetermined signal during the data receiving period, and the fetched signal of the received data outside the data receiving period. Since it is masked, noise resistance is enhanced.

Further, according to another structure of the present invention, it is possible to separately generate a signal for activating a process corresponding to an input signal corresponding to a special command or the like during the mask period. .

According to another structure of the present invention, when data is received from the bidirectional signal line, a slice level higher than the Schmitt level of the receiving element can be set, and noise resistance is enhanced.

Further, according to another structure of the present invention, when the input slice level is exceeded for a certain time, the input signal can be stabilized by applying a feedback to the input signal, so that the resistance to noise is improved. Be improved.

[0082]

[Brief description of drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a general data transfer interface.

FIG. 2 is a diagram showing an equivalent circuit of charging / discharging at a transition of an input signal in a printer receiving unit.

FIG. 3 is a waveform of an input signal to an input element (rep1) and
It is a figure explaining the output waveform from an input element (rep1).

FIG. 4 is an input signal waveform to an input element (rep1) and
It is a figure explaining the output waveform from an input element (rep1).

FIG. 5 is a block diagram illustrating a functional configuration of an interface circuit according to the first exemplary embodiment.

FIG. 6 is a diagram illustrating a circuit configuration of the interface device according to the first exemplary embodiment.

FIG. 7 is a diagram showing output timing of a two-stage D-type FF.

FIG. 8 is a timing chart showing a data transfer procedure of the first embodiment.

FIG. 9 is a diagram illustrating a data transfer procedure (handshake) according to the first embodiment.

FIG. 10 is a diagram illustrating a circuit configuration example of an interface device according to a second embodiment.

FIG. 11 is a diagram illustrating an interface circuit for a general bidirectional signal line.

12 is a diagram showing a state in which a low pass filter is provided in the interface circuit of FIG.

13 is a diagram showing a state where an inductor (L) is inserted in the low pass filter of FIG.

FIG. 14 is a diagram showing a basic circuit configuration of a bus latch.

FIG. 15 is a diagram showing a circuit example of a bus latch compatible with extension of noise time width.

FIG. 16 is a diagram illustrating a configuration example of an interface circuit according to a third embodiment.

FIG. 17 is a diagram showing a switch state of an analog switch in the third embodiment.

FIG. 18 is a diagram showing an extracted circuit formed when the interface circuit of FIG. 17 receives data.

FIG. 19 is a diagram showing an equivalent circuit when the signal level changes from Hi to Lo in the interface circuit of the third example.

FIG. 20 is a diagram showing an equivalent circuit when the signal level changes from Lo to Hi in the interface circuit of the third embodiment.

FIG. 21 is a diagram showing a change in the input / output state of each element with respect to a change in an input signal in the bus latch with delay.

FIG. 22 is a diagram illustrating a modified example of the interface circuit according to the third embodiment.

FIG. 23 is a diagram showing a modification of the third embodiment.

FIG. 24 is a diagram showing a modification of the third embodiment.

[Explanation of symbols]

 51 transmitter 52 receiver 53 signal width detection block 53a signal width setting unit 53b signal detector 53c comparison unit 54 buffer

Claims (16)

[Claims] 1. An interface device for data transfer, comprising setting means for setting a set value indicating a pulse width, input means for inputting a signal from an external device, and signal width of the signal input by the input means. When the is larger than the pulse width indicated by the set value set by the setting means, the determination means for determining the signal as a significant signal, and a predetermined process using the signal determined to be a significant signal by the determination means An interface device comprising: a processing unit that executes the interface device. 2. The interface device according to claim 1, wherein the setting means sets a set value indicating a pulse width from a CPU of a device having the interface device. 3. The setting means sets a clock cycle, and the judging means judges a signal having a signal width larger than the clock cycle set by the setting means as a significant signal. The interface device according to claim 1, wherein the interface device is provided. 4. The setting means sets a count value of the number of clocks in a predetermined cycle, and the judging means counts the clocks while a signal is being input from the input means, and is set by the setting means. 2. The signal is determined to be a significant signal when it is counted beyond the count value.
The interface device according to. 5. An interface device for performing data transfer, comprising: setting means for setting a set value indicating a pulse width; input means for inputting an input signal from an external device; and the signal width of the strobe signal being the setting. Between the determination unit that determines the input signal as a significant signal when it is larger than the pulse width indicated by the setting value set by the unit, and the processing related to the input signal after the determination unit determines that the input signal is a significant signal. An interface device comprising: a masking unit that performs a masking process on the input signal. 6. The interface device according to claim 5, wherein the input signal is a strobe signal for instructing a transfer data fetch timing. 7. The apparatus further comprises generation means for separately generating a signal for activating processing when a signal having a significant signal width is input from the input means during the masking period by the masking means. The interface device according to claim 5, characterized in that 8. An interface device for transferring data using a bidirectional signal line, wherein an output part of an input element and an input part of an output element of the bidirectional signal line are connected at the time of signal input, and A connecting means for connecting the output part of the output element and the input part of the input element via a resistance value is provided, and in the state of connection by the connecting means, a change in the signal level input via the bidirectional signal line is The interface device is reverse-biased by the output of the output element and applied to the input element. 9. A connection switching means for connecting an input section of the output element to an internal output signal line and connecting an output section of the output element to a connection section to an external device at the time of outputting a signal. 9. Further comprising:
Interface device. 10. The resistance value of the resistor arranged between the input element and the output element is switched depending on whether the signal level changes from 1 to 0 or 0 to 1. 9. The interface device according to claim 8, further comprising switching means. 11. The interface device according to claim 9, wherein the connection in the connection unit and the connection switching unit is realized by applying an analog switch. 12. The interface device according to claim 9, wherein the connection in the connection unit and the connection switching unit is realized by applying a relay. 13. The connection between the output section of the input element and the input section of the output element in the connection means is connected via a delay section that delays and transmits a signal for a predetermined time. The interface device according to claim 8. 14. An interface method for data transfer, comprising a setting step of setting a set value indicating a pulse width, an input step of inputting a signal from an external method, and a signal width of the signal input by the input step. A determination step of determining the signal as a significant signal when the pulse width is larger than the pulse width indicated by the setting value set by the setting step, and performing a predetermined process using the signal determined to be a significant signal by the determination step. An interface method comprising: performing a processing step. 15. An interface method for performing data transfer, comprising a setting step of setting a set value indicating a pulse width, an input step of inputting an input signal from an external method, and a signal width of the strobe signal being the setting value. Between the determination step of determining the input signal as a significant signal when it is larger than the pulse width indicated by the set value set by the step, and the processing related to the input signal after being determined as the significant signal by the determination step. And a mask step of performing mask processing on the input signal. 16. An interface method for transferring data using a bidirectional signal line, comprising: connecting an output part of an input element and an input part of an output element of the bidirectional signal line at the time of signal input; A connecting step of connecting the output part of the output element and the input part of the input element via a resistance value is provided, and in the state of connection by the connecting step, a change in the signal level input via the bidirectional signal line is An interface method in which the output of the output element is reverse-biased and applied to the input element.