JPH07212718A - Video signal processor - Google Patents

Abstract

PURPOSE:To adopt proper configuration for various decoders coping with interlace scanning, sequential scanning and the number of valid scanning lines by reducing the number of vertical filters and of line memories required for 3 to 4 conversion processing so as to reduce a hardware scale. CONSTITUTION:A video signal of a center screen of a letter box system is subjected to filtering processing in two systems being a direct system and an interpolation system at a VLPF 301 in the interlace scanning state. A video signal on upper and low non-picture parts is subjected to filtering processing in the same two systems being the direct system and the interpolation system at a V-HPF 302. The signals in the direct system and the interpolation system are added respectively by adders 303, 304 and expanded to be a multiple of 4/3 at a 3 to 4 converter 305 and the signals of the direct system and the interpolation system are added by a sequential scanning converter 306, in which the signals are converted into sequential scanning signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit.

[0002]

2. Description of the Related Art Although the aspect ratio of a television screen is 4: 3 in current television broadcasting, high definition television (HDTV) as a new standard is used not only in Japan but also in other countries. An aspect ratio of 16: 9 is adopted. It is known that when viewing a horizontally long screen at a large viewing angle, the sense of presence is significantly improved. However, HD
Since the system itself is a new standard for TV, current receivers cannot receive it as it is. Therefore, the letterbox method is known as a means for easily transmitting a landscape image while maintaining compatibility with the current method.

This system is based on the current NT as shown in FIG.
The central portion 360 of the screen having an aspect ratio of 4: 3 having an effective scanning line 480 [lines / frame] defined by the SC system
This is a method of transmitting a horizontally long screen image with an aspect ratio of 16: 9 in [book / frame]. In this case, since the main screen section can only transmit image information using only 3/4 of the effective scanning lines defined by the original NTSC, the vertical resolution is 3 as well.
There is no choice but to deteriorate to / 4. On the other hand, in the television signal of the late box system, there are 60 [lines / frames] each of which is a non-image part at the top and bottom of the screen. Therefore, a method has been proposed in which the upper and lower non-image portions are used to multiplex-transmit an additional signal for compensating for the deterioration of the image on the main screen portion.

Next, as a letterbox system, a system for transmitting the difference between lines in the upper and lower non-image portions (hereinafter referred to as L
Method D) will be described below. In the LD method, a difference signal between a scanning line that is removed when a progressive scanning signal is converted to an interlaced scanning signal and an original scanning line before and after is multiplexed on the upper and lower non-image parts, and the difference signal is used on the receiver side. Then, a compensation signal for the scanning line removed on the sending side is generated and the original progressive scanning signal is reproduced.

FIG. 22 shows an embodiment of an LD type encoder. 525 scanning lines, frame frequency 6
The R, G, and B signals which are 0 (Hz) and the sequential scanning signals having the aspect ratio of 16: 9 are input terminals 101 and 10, respectively.
It is input to the matrix circuit 104 via 2, 103. The matrix circuit 104 performs a matrix operation on the R, G, B signals to obtain a luminance signal (hereinafter referred to as Y signal), 2
Two color difference signals (denoted as I and Q signals) are generated.

The Y signal is a vertical low pass filter (VL).
In the PE) 105, the band is vertically limited so that aliasing does not occur when converting from 480 effective scanning lines to 360 effective lines in the letterbox format. The output of the vertical low-pass filter 105 is input to the 4 → 3 converter 106 for converting the number of scanning lines and converted from 480 effective scanning lines to 360. The output of the 4 → 3 converter 106 is input to a vertical low pass filter (V-LPF) 107 and a vertical high pass filter (V-HPE) 108.

The output of the vertical low pass filter 107 is input to the interlaced scanning converter 109 and becomes the main screen portion signal of the encoded output. In addition, the vertical high-pass filter 108
Is output to the interlaced scanning converter 110 and converted into an interlaced scanning signal. The interlaced scanning signal is band-limited by the horizontal low-pass filter (H-LPE) 111 so that the band after time compression does not exceed the transmission band of the current broadcast. The output of the horizontal low-pass filter 111 is input to the time compression circuit 112 and time-compressed to 1/3. The output of the time compression circuit 112 is input to the buffer memory 114. When the signal of the buffer memory 114 is output, three of the 360 time-compressed signals are arranged on one scanning line to be transmitted, and are allocated to 120 scanning lines in the upper and lower non-image areas. Is output.

On the other hand, the I and Q signals are input to vertical low pass filters (V-LPE) 117 and 118, respectively,
The band is limited so as not to be folded back in the vertical direction when performing the interlaced scanning conversion and the 4 → 3 conversion. The outputs of the vertical low-pass filters 117 and 118 are input to the interlaced scanning converters 119 and 120, respectively, converted into interlaced scanning signals, and then input to the 4 → 3 converters 121 and 122, where the fields are input. The number of effective scan lines is 36
Converted to 0 interlaced scanning signals. 4 to 3 converter 12
The output of 1,122 is a horizontal low-pass filter (H-LP
F) 123 and 124 are band-limited to the band of the current broadcasting format, and then input to multipliers 125 and 126, respectively, and carrier frequency fsc (455 / 2fh: fh
Is modulated at the horizontal scanning frequency). Multipliers 125 and 12
The output of 6 becomes the color signal C which is added by the adder 127 and is multiplexed with the main screen signal.

Output of interlaced scan converter 109 and adder 1
The 27 outputs are input to the buffer memories 113 and 128, respectively, and subjected to delay adjustment. Buffer memory 11
The outputs of 3,128 are input to the adder 115 and output as a composite signal of the main screen section. Adder 115
Output (main screen portion signal) and buffer memory 114 output (upper and lower non-image portion signals) are selectively derived by the selector 116 at the timing of the main screen portion and upper and lower non-image portion, and the scanning line number 525
It is output as an interlaced scanning signal of a book. This encoder output is a letterbox format signal.

Also, separated from the preceding sequential scanning signal,
The horizontal synchronizing signal H and the vertical synchronizing signal V are supplied to the control signal generator 1
The control signal a, b, c and the select signal d to the sine wave, the cosine wave, and the buffer memories 113, 114, and 128 which are input to 29 and have the carrier frequency fsc are generated.

FIG. 23 shows the structure of the decoder.
The encode signal described above is input to the Y / C separation unit 201 that separates the luminance signal and the color signal via the input terminal 200, and is separated into the luminance signal Y and the color signal C. The separated Y signal is delay-adjusted by the buffer memory 202 and then input to the progressive scan converter 203. The progressive scan converter 203 converts the interlaced scan signal into a progressive scan signal. The output of the progressive scan converter 203 is input to a vertical low-pass filter (V-LPF) 204, and its vertical low-pass component is extracted.

The input encode signal is also input to the buffer memory 205. In the buffer memory 205,
The multiplex signals multiplexed in the upper and lower non-image parts are rearranged into the interlaced scanning signals having the frame frequency of 30 (Hz). The output of the buffer memory 205 is input to the time expansion circuit 206, time-expanded three times and reproduced as the original compensation signal. The output of the time extension circuit 206 is the progressive scan converter 20.
After being inputted to the No. 7 and sequentially converted into the scanning signal, the vertical high-pass filter (V-HPF) 208 reproduces the vertical high-pass component. Here, the outputs of the vertical low-pass filter 204 and the vertical high-pass filter 208 are combined by the adder 209 and reproduced as a broadband signal having 360 effective scanning lines. The output of the adder 209 is 3 for converting the number of scanning lines.
→ 4 The number of effective scanning lines input to the converter 211 is 480
It is reproduced into a progressive scanning signal of a book.

On the other hand, the color signals obtained from the Y / C separation unit 201 are input to multipliers 212 and 213, respectively multiplied by a sine wave and a cosine wave of the carrier frequency fsc, and demodulated as I and Q signals, respectively. To be done.

Next, the I and Q signals output from the multipliers 212 and 213 are respectively fed to the horizontal low pass filter 21.
4, 215, and the high frequencies of each component are removed.
The outputs of the horizontal low-pass filters 214 and 215 are input to the 3 → 4 converters 216 and 217, respectively, and converted into signals of 480 effective scanning lines. 3 → 4 converter 216,
The outputs of 217 are the progressive scan converters 218, 21 respectively.
9 and is converted into a progressive scanning signal having a frame frequency of 60 (Hz). The I and Q signals output from the progressive scan converters 218 and 219 are respectively stored in the buffer memory 22.
0, 221, is delayed and adjusted for time adjustment with the Y signal from the 3 → 4 converter 211, and is output.
The Y, I and Q signals are input to the matrix circuit 222, converted into R, G and B component signals and output.

Here, the sync reproducing circuit 224 reproduces the horizontal and vertical synchronizing signals H and V from the input encode signal,
It also creates a two-frame reference signal. The fsc reproducing unit 225 generates a sine wave and a cosine wave of the previous carrier frequency fsc based on the input encode signal and the 2-frame reference synchronization signal. The control signal generator 226 creates the memory control signals e, f, g, h using the horizontal and vertical synchronization signals, and the buffer memories 202, 205, 220, 2
21 is controlled.

Since the decoder shown in FIG. 23 shows the structure of a progressive scan decoder, the structure of the interlaced scan decoder is shown next. FIG. 24 shows a decoder configuration for interlaced scanning.

Since this is almost the same as the structure of the progressive scan decoder shown in FIG. 23, the same parts are designated by the same reference numerals, and different parts will be described. The difference from FIG. 23 is that the interlaced scanning converter 230 is added,
That is, the progressive scan converters 218 and 219 are eliminated.

The output of the 3 → 4 converter 211 is input to the interlaced scan converter 230. Interlaced scan converter 23
At 0, the progressive scanning signal of 480 effective scanning lines is converted into the interlaced scanning signal. Then, the output of the interlaced scan converter 230 is input to the matrix circuit 222.

The outputs of the 3 → 4 converters 216 and 217 are interlaced scanning signals of 480 effective scanning lines, and therefore are input to the buffer memories 220 and 221 respectively. The buffer memories 220 and 221 perform a delay for time adjustment with the Y signal output from the interlaced scan converter 230. The outputs of the buffer memories 220 and 221 are input to the matrix circuit 222.

According to the above method, it is possible to configure the decoder according to the format of the decoded signal in either the progressive scanning or the interlaced scanning. However, even when trying to obtain the interlaced scanning decode signal, the hardware scale becomes very large because the progressive scanning decode signal is obtained. Also, in the case of decoding of progressive scanning, since the progressive scanning signal is passed through the vertical filter and the 3 → 4 conversion is performed, the hardware scale becomes large.

[0021]

As described above, in the letterbox type decoder compatible with the current method, the processing must be performed by progressive scanning, which increases the hardware scale. Further, even if an attempt is made to obtain a decode signal for interlaced scanning, the decode signal for sequential scanning must be obtained, which causes a problem that the hardware scale becomes large.

Therefore, it is an object of the present invention to provide a video signal processing device in which the hardware scale of a decoder is reduced and it is not necessary to obtain a decode signal for progressive scanning when a decode signal for interlaced scanning is obtained.

[0023]

According to the present invention, a scan line signal generated by progressive scan conversion and an original signal are used.
Processing is performed using the system signal. In the case of a vertical filter, since the taps hit by the two systems of signals are different, the taps are changed according to the phase of each filter. The same applies to the case of the 3 → 4 conversion, and processing is performed according to the conversion phase for signals of two systems. Then, in the case of obtaining the decode signal of the progressive scan, the signals of the two systems are used and finally converted into the signal of the progressive scan.

That is, a means for deriving one video signal and a second video signal, which have the same source but different frequency bands, and the first video signal and the second video signal are input, and these video signals are input. A first signal processing means for outputting a third video signal having the same scanning rate as the above, the first video means and the second video signal are inputted, and a fourth video having the same scanning rate as these video signals. A second signal processing means for outputting a signal, and an output video in which the scanning rate is converted by alternately switching the two signals after compressing each of the third video means and the fourth video signal by 1/2 time. And means for obtaining a signal.

[0025]

According to the above means, since the vertical filter and the 3 → 4 conversion are performed by using the interlaced scanning signals of two systems, the number of line memories required for the processing can be reduced, and the hardware scale can be reduced. Can be made smaller. Further, when an interlaced scanning decode signal is to be obtained, only one required system of the two systems need be performed, so that the hardware scale can be made much smaller than in the conventional case.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. FIG. 23
Since most of the conventional example has the same configuration, the same numbers are given to the same parts, and different parts will be described.

Delay adjusted Y in the buffer memory 202
The signal is input to a V-LPF (vertical low pass filter) 301. The V-LPF 301 performs vertical processing, and outputs signals of two systems, a direct system and an interpolation system.
The internal configuration of this V-LPF 301 will be described later. Further, the direct system is a signal of a scanning line which is necessary when a progressive scanning signal is converted into an interlaced scanning signal, and the interpolating system is an error when a progressive scanning signal is converted into an interlaced scanning signal. It means the necessary scanning line signal.

The reproduced compensation signal output from the time extension circuit 206 is input to a V-HPF (vertical high pass filter) 302. The V-HPF 302 performs vertical processing and outputs signals of two systems, a direct system and an interpolation system. The internal structure of the V-HPF 302 will also be described later.

The signals output from the V-LPF 301 and the V-HPF 302 are added by the adders 303 and 304 to the signals of the direct system and the signals of the interpolation system, respectively. The direct system signal output from the adder 303 and the interpolation system signal output from the adder 304 are both input to the 3 → 4 converter 305.

In the 3 → 4 converter 305, 4 /
3-fold extension is performed. Also in this case, direct system processing and interpolation system processing are performed, and signals of two systems of the direct system and the interpolation system are output. The internal configuration of the 3 → 4 converter 305 will be described later.

The signals of the direct system and the interpolation system output from the 3 → 4 converter 305 are both input to the progressive scan converter 306. The progressive scan converter 306 compresses each of the two input signals for 1/2 time, and alternately selects and outputs them for each line to convert them into progressive scan signals. The progressive scanning signals of 480 effective scanning lines output from the progressive scanning converter 306 are input to the matrix circuit 222.

Next, the structure of the V-LPF 301 will be described. The processing of the V-LPF 301 is basically shown in FIG.
The V-LPF 204 is the same as the V-LPF 204, except that the input signal is not interlaced scanning but interlaced scanning, and two outputs are provided. Before describing the configuration of the V-LPF 301, the configuration of the V-LPF 204 will be described with reference to FIG. Here, the characteristic of the V-LPF 204 is a 3-tap filter with tap coefficients of 1/4 1/2 1/4.

The signal input from the terminal 401 is input to the two line memories 402 and 403 connected in series. Each of the two line memories 402 and 403 is delayed by one horizontal scanning period. Also, the terminal 401
The input signal from the input terminal is input to the coefficient unit 404, the output of the line memory 402 is input to the coefficient unit 405, and the output of the line memory 403 is input to the coefficient unit 406. Coefficient units 404, 40
5, 406, the input signal is 1/2 times,
It is output after being multiplied by 1/2. Here, the multiple is twice the tap coefficient of the set filter. this is,
This is because the DC gain becomes 1/2 because the progressive scanning signal input to the V-LPF 204 becomes 0 every other line, and this is to correct it. Although all the tap coefficients are doubled here, the same effect can be obtained by doubling the signal in the input part or the output part while keeping the tap coefficients unchanged.

The outputs of the coefficient multipliers 404, 405 and 406 are all input to the adder 407. The outputs of the coefficient multipliers 404, 405, and 406 are added by the adder 407, and the result is supplied to the terminal 408 and becomes the output of the V-LPF 204.

This operation will be described in some detail with reference to FIG. FIG. 3A shows an interlaced scanning signal input to the progressive scan converter 203. The circles here indicate lines. FIG. 3B shows the output of the progressive scan converter 203, in which 0s are inserted every other line to provide a progressive scan signal. This signal is V-
The signal is input to the LPF 204 to obtain the signal shown in FIG.

That is, the signal of FIG. 3C is obtained by the following calculation. C _2n = (1/2) × B _2n-1 + 1 × B _2n + (1/2) × B
_{2n + 1} C _{2n + 1} = (1/2) x B _2n +1 x B _{2n + 1} + (1/2) x
B _{2 (n + 1)} Here, B in FIG. 3 (2) is a signal in which 0 is inserted every other line in A in FIG. 3 (1), so that B _2n = A _n B _{2n + 1} = (1/2) × A _n + (1/2) × A _{(n + 1)} . That is, the processing of the V-LPF 204 can be performed by two types of calculation using the interlaced scanning signal.

Therefore, the interlaced scanning signal is input and 2
The V-LPF 301 is a vertical low-pass filter configured to perform various types of calculations. FIG. 2B shows the configuration of this V-LPF 301. Where C
_{The 2n} signal is a direct system signal, and the C _{2n + 1} signal is an interpolation system signal.

The signal input from the terminal 411 is input to the line memory 412 and delayed by one horizontal scanning period. The output of the line memory 412 is input to the terminal 416 and the coefficient multiplier 414. The signal output from the terminal 416 becomes a direct system signal.

The signal input from the terminal 411 is also input to the coefficient multiplier 413. In the coefficient multipliers 413 and 414, the input signals are respectively halved and output. Coefficient unit 4
The outputs of 13, 414 are both input to the adder 415,
They are added and output. The output of the adder 415 is supplied to the terminal 417, which becomes the output of the interpolation system.

The V-LPF 302 (FIG. 1) has the same structure. First, the configuration of the V-HPF 208 (FIG. 23) is shown in FIG. 4 (A), and its operation will be described. here,
The tap coefficient of the filter is -1/8 -2/8 6/8 -2/8 -1
/ 8.

The signals input from the terminal 421 are line memories 422, 423, 424 connected in series with four.
425 are sequentially input. Line memory 422, 42
At 3,424 and 425, a delay of one horizontal scanning period is performed.

The input signal from the terminal 421 is a coefficient multiplier 426.
To the line memories 422, 423, 424, 4
The outputs of 25 are coefficient units 427, 428, and 42, respectively.
8,430 is input. Coefficient multipliers 426, 427, 42
8, 429, 430, the input signal is -1/4, respectively.
It is output after being doubled, -2/4 times, 6/4 times, -2/4 times, and -1/4 times. Here, as in the case of the V-LPF 204, each coefficient multiplication factor is twice the tap coefficient of the set filter. This is also V-LPF208
This is because the DC gain is ½ because the progressive scanning signal input to is 0 every other line, and is for correcting it.

Coefficient units 426, 427, 428, 428,
All the outputs of 430 are input to the adder 431 and added. The output of the adder 431 is supplied to the terminal 432.
This is the output of the V-HPF 208.

Since the progressive scan converter 207 inserts 0s for every other line, the input of the V-HPF 208 can be performed by two kinds of operations as in the case of the V-LPF 204. Here, if the interlaced scan signal before progressive scan conversion is D and the signal after vertical high-pass filtering is E, then E _2n = (-1/4) × D _(n-1) + (6 / 4) × D _n +
_{(-1/4) × C (n +} 1) E 2n + 1 = (- 2/4) × D n + (- 2/4) a × C _{(n + 1).} Therefore, the V-HPF 302 may be configured to perform these processes.

FIG. 4B shows the structure of this V-HPF 302. The signal input from the terminal 441 is sequentially input to the two line memories 422 and 443 connected in series. Each of the lime memories 442 and 443 is delayed by one horizontal scanning period.

The input signal from the terminal 421 is a coefficient multiplier 44.
4, 447, the output of the line memory 442 is input to the coefficient units 445 and 448, and the output of the line memory 443 is input to the coefficient unit 446.

In the coefficient multipliers 444, 445 and 446, the input signals are (-1/4) times, (6/4) times and (-1), respectively.
/ 4) It is multiplied and output. Coefficient multipliers 444, 445, 4
All the outputs of 46 are input to the adder 449 and added. The output of the adder 449 is supplied to the terminal 450, and this becomes the output of the direct system.

In the coefficient multipliers 447 and 448, the input signals are respectively multiplied by (−2/4) and output. Coefficient unit 44
The outputs of 7, 448 are both input to the adder 451 and added. The output of the adder 451 is supplied to the terminal 452, which serves as an indirect output.

In the structure of this V-HPF 302, E
_2n is a direct system and E _{2n + 1} is an interpolation system. However, this relationship may be reversed depending on the interlaced scan conversion configuration of the encoder. That is, in the interlaced scan converter 109 and the interlaced scan converter 110 in FIG. 22, when the scanning lines extracted when converting the sequential scanning signal to the interlaced scanning signal are the same, E _2n becomes the direct system as described above, and E _2n + 1 is the interpolation system. However, when the scanning lines extracted when converting from the sequential scanning signal to the interlaced scanning signal are different, E _{2n + 1} becomes the direct system and E _2n becomes the interpolation system.

As described above, the number of line memories to be used can be reduced by making the structure of the vertical filter such that the interlaced scanning signal is input and the signals of two systems of the direct system and the interpolation system are output. Can be reduced. V-LPF2
04 used two line memories, but V-L
Only one is used for PF301, and V-HPF2
08 used four, but V-HPF302 used 2
It is used individually. Furthermore, since all processing is performed using interlaced scanning signals, the circuit operating speed can be halved compared to the conventional example in which processing is based on progressive scanning signals, so the circuit configuration is easy. become.

Next, the operation of the 3 → 4 converter 305 will be described. Before that, the operation of the 3 → 4 converter 211 (FIGS. 23 and 24) will be described. 3 to 4 converter 2 in FIG.
11 shows the configuration of 11.

The signal input from the terminal 501 is written in the image memory 502. In the memory 502, 4/3 times expansion in the vertical direction is performed by control of writing and reading. This is realized by repeating the operation of sequentially writing all the scanning lines, performing reading for three lines, and stopping one line. These operations are performed by the control signal from the control signal generation circuit 516.

The output of the memory 502 is the line memories 503, 504, 505, 506, 507 connected in series.
Are sequentially input to each line, and delay is performed line by line. Memory 502, line memories 503, 504, 505, 50
The outputs of 6, 507 are coefficient units 508, 509,
It is input to 510, 511, 512 and 513. In the coefficient multipliers 508, 509, 510, 511, 512 and 513, the input signal is multiplied by a coefficient and output. Coefficient units 508, 509, 510, 511, 512,
The outputs of 513 are all input to the adder 514, and all signals are added. The output of the adder 514 is the terminal 515.
Which is the output of the 3 → 4 converter 211.

The horizontal synchronizing signal H and the vertical synchronizing signal V are input to the control signal generating circuit 516. And
Control signal of memory 502 and coefficient multipliers 508, 509, 5
Control signals to 10, 511, 512 and 513 are output. Coefficient units 508, 509, 510, 511, 512,
The coefficient of each line 513 is switched for each line by a control signal.

FIG. 6 shows the principle of the 3 → 4 conversion process. In this figure, each signal indicates a scanning line. Figure 6
The signal of (1) is expanded by 3/4 to obtain the signal of (2) in FIG. The signal of FIG. 6 (2) is obtained by expanding the scanning line interval by 3/4 times, and therefore the signal of FIG. 6 (2) is interpolated so as to have the original scanning line interval, The signal of 3) is used.
Now, it is assumed that the characteristic of this interpolation is represented by the following formula.

G _4n = h ₄ × F _{3 (n-1) +2} + h ₀ × F _3n + h ₄ × F _{3n + 1} G _{4n + 1} = h ₇ × F _{3 (n-1) +2} + h ₃ × F _3n + h ₁ × F _{3n + 1}
+ H ₅ × F _{3n + 2} G _{4n + 2} = h ₆ × F _3n + h ₂ × F _{3n + 1} + h ₂ × F _{3n + 2} + h
₆ x F _{3 (n + 1)} G _{4n + 3} = h ₅ x F _{3n + 1} + h ₁ x F _{3n + 2} + h ₃ x F _{3 (n + 1)}
+ H ₇ × F _{3 (n + 1) +1 In} order to realize these expressions, coefficient units 508, 509,
By setting the coefficients 510, 511, 512, and 513, 4/3 times expansion is realized.

Input signals of the memory 502 are shown in FIGS. 7 (1) and 8 (1), and output signals of the memory 502 and line memories 503, 504, 505, 506, 507 are shown in FIGS. 7 (2) and 8 (2). Show. Again, each signal represents a scan line. Then, the coefficient units 508, 509, 510, 511,
Coefficients 512 and 513 are set for each line as shown in FIGS. 7 (3) and 8 (3). As a result, the signal given by the above equation is output from the adder 514 at the timings shown in FIGS. 7 (4) and 8 (4).

By changing the subscript of the above equation, the following equation is obtained. G _8m = h ₄ × F _{6 (m-1) +5} + h ₀ × F _6m + h ₄ × F _{6m + 1} G _{8m + 1} = h ₇ × F _{6 (m-1) +5} + h ₃ × F _6m + h ₁ x F _{6m + 1}
+ H ₅ × F ^6m ₊₂ G ^8m ₊₂ = h ₆ × F _6m + h ₂ × F _{6m + 1} + h ₂ × F ^6m ₊₂ + h
₆ x F _{6m + 3} G _{8m + 3} = h _{5 xF 6m + 1} + h _{1 xF 6m + 2} + h _{3 xF 6m + 3} +
h _{7 xF 6m + 4} G _{8m + 4} = h _{4 xF 6m + 2} + h _{0 xF 6m + 3} + h _{4 xF 6m + 4} G _{8m + 5} = h _{7 xF 6m + 2} + h _{3 xF 6m +3} + h ₁ × F _{6m + 4} ＋
h ₅ × F _{6m + 5} G _{8m + 6} = h ₆ × F _{6m + 3} + h ₂ × F _{6m + 4} + h ₂ × F _{6m + 5} +
h ₆ × F _{6 (m + 1)} G _{8m + 7} = h ₅ × F _{6m + 4} + h ₁ × F _{6m + 5} + h ₃ × F _{6 (m + 1)}
+ H ₇ × F _{6 (m + 1) +1} These are considered as progressive scanning signals, but when considered as interlaced scanning signals, the input signals are F _6m , F _{6m + 2} , F _{6m + 4} ,
Is a direct system, and F _{6m + 1} , F _{6m + 3} , F _{6m + 5} are interpolation systems.
In the output signal, G _8m , G _{8m + 2} , G _{8m + 4} and G _{8m + 6} are direct systems, and G _{8m + 1} , G _{8m + 3} , G _{8m + 5} and G _{8m + 7} are interpolation systems. Become.

Therefore, the 3 → 4 converter 305 is configured to realize these equations. Input signals are direct system and interpolation system.
It is a system interlaced scanning signal, and the output signal is also a system interlaced scanning signal of two systems.

FIG. 9 shows the configuration of the 3 → 4 converter 305.
A direct system signal is input from the terminal 521, and the terminal 522
The signal of the interpolation system is input from. The input signal from the terminal 521 is input to the memory 525 via the switch 523. The other input terminal of the switch 523 is the terminal 52.
Connected to 2. The input signal from the terminal 522 is input to the memory 526 via the switch 524. The other input terminal of the switch 524 is connected to the terminal 521.

In the memories 523 and 524, 4/3 times expansion in the vertical direction is performed by controlling writing and reading. This is the same as the operation of the image memory 502 (FIG. 5), in which all the scanning lines are sequentially written and read out by 3 times.
This is realized by repeating the operation of going to the line and stopping one line. These operations are controlled by a control signal from the control signal generation circuit 551.

The output of the memory 525 is sequentially input to the line memories 527 and 528 connected in series, and the line memories are delayed by one line. The output of the memory 525 is the coefficient unit 5
32, 539, the output of the line memory 527 is the coefficient unit 53
3, 540, the output of the line memory 528 is the coefficient unit 53
4, 541 is input. The output of the memory 526 is sequentially input to the line memories 529, 530, and 531 connected in series, and delay is performed for each line. Memory 5
The output of 26 is input to the coefficient unit 538, the output of the line memory 529 is input to the coefficient units 535 and 542, the output of the line memory 530 is input to the coefficient units 536 and 543, and the output of the line memory 531 is input to the coefficient units 537 and 544.

Coefficient units 532, 533, 534, 535,
536, 537, 538, 539, 540, 541, 5
At 42, 543 and 544, the input signal is multiplied by a certain coefficient and output. Coefficient multiplier 532, 533, 5
The outputs of 34, 535, 536 and 537 are all adders 54.
It is input to 5 and all signals are added. Coefficient unit 5
38, 539, 540, 541, 542, 543, 54
The outputs of 4 are all input to the adder 546, and all signals are added.

The output of the adder 545 is supplied to the terminal 549 via the switch 547. The other input terminal of the switch 547 is connected to the output of the adder 546. The output of the adder 546 is supplied to the terminal 550 via the switch 548. The other input terminal of the switch 548 is connected to the output of the adder 545. Terminal 5
The output from 49 becomes the output signal of the direct system, and the terminal 550
The output from is the output signal of the interpolation system.

The horizontal synchronizing signal H and the vertical synchronizing signal V are input to the control signal generating circuit 551. And
Control signals of memories 525 and 526 and coefficient multipliers 532 and 5
33, 534, 535, 536, 537, 538, 53
9, 540, 541, 542, 543, 544 control signals, and switches 523, 524, 547, 548
Control signal is output. Coefficient multiplier 532, 533, 53
4,535,536,537,538,539,54
Coefficients of 0, 541, 542, 543 and 544 are switched line by line by a control signal. The switches 523, 524, 547, 548 are controlled so that the input is switched for each field.

FIGS. 10 and 11 are explanatory views showing the operation of the 3 → 4 converter 305. In this figure, circles represent scanning lines. FIG. 10 (1) and FIG. 11 (1)
It shows two input signals of the direct conversion system and the interpolation system of the 3 → 4 converter 305. The outputs of the memories 525 and 526 are shown in FIGS. 10 (2) and 11 (2). Here, at the same time, the line memories 527, 528, 529, 5
The output of 30,531 is also shown. Therefore, the coefficient unit 53
2,533,534,535,536,537,53
8,539,540,541,542,543,544
If the coefficient of is set as shown in FIGS. 10 (3) and 11 (3), the signals shown in FIGS. 10 (4) and 11 (4) are output from the adders 545 and 546.

The output of the adder 545 is: G _8m = h ₄ × F _{6 (m-1) +5} + h ₀ × F _6m + h ₄ × F _{6m + 1} G _{8m + 2} = h ₆ × F _6m + h ₂ × F _{6m + 1} + h ₂ x F _{6m + 2} + h
₆ x F _{6m + 3} G _{8m + 4} = h _{4 xF 6m + 2} + h _{0 xF 6m + 3} + h _{4 xF 6m + 4} G _{8m + 6} = h _{6 xF 6m + 3} + h _{2 xF 6m + 4} + h ₂ × F _{6m + 5} ＋
h ₆ × F _{6 (m + 1)} , and the output of the adder 546 is G _{8m + 1} = h ₇ × F _{6 (m-1) +5} + h ₃ × F _6m + h ₁ × F _{6m + 1}
+ H ₅ × F _{6m + 2} G _{8m + 3} = h ₅ × F _{6m + 1} + h ₁ × F _{6m + 2} + h ₃ × F _{6m + 3} ＋
h ₇ × F _{6m + 4 G 8m + 5} = h ₇ × F _{6m + 2} + h ₃ × F _{6m + 3} + h ₁ × F _{6m + 4} +
h ₅ × F _{6m + 5} G _{8m + 7} = h ₅ × F _{6m + 4} + h ₁ × F _{6m + 5} + h ₃ × F _{6 (m + 1)}
+ H ₇ × F _{6 (m + 1) +1} . Therefore, the output of the adder 545 becomes a direct system signal, and the output of the adder 546 becomes an interpolation system signal.

By the way, in the case of converting a progressive scanning signal into an interlaced scanning signal, when the field changes, the relationship between the direct system and the interpolation system becomes opposite. Therefore, the switch 54
7, 548 is used so that the output of the direct system and the output of the interpolation system are switched for each field. Similarly, with respect to the input signal as well, the phases of the direct system and the interpolation system are reversed for each field, so that the switches 523 and 524 are used to switch the input of the direct system and the input of the interpolation system for each field.

FIG. 12 shows another embodiment. Figure 1
The difference from the above embodiment is that the 3 → 4 conversion is performed after the sequential scanning conversion. Since the configuration is almost the same as that of FIG. 1, only different points will be described.

The direct system signal output from the adder 303 and the interpolation system signal output from the adder 304 are input to the sequential scan converter 306. Progressive scan converter 306
Then, the two input signals are converted into a sequential scanning signal having 360 effective scanning lines and output. The output of the progressive scan converter 306 is input to the 3 → 4 converter 211 and converted into a progressive scan signal having 480 effective scanning lines. 12
With the above configuration, the same result as the configuration of FIG. 1 can be obtained.

In the embodiment shown in FIGS. 1 and 12, the number of effective scanning lines is four.
The configuration of a decoder that outputs 80 progressive scan signals is shown. FIG. 13 shows still another embodiment of a decoder that outputs an interlaced scanning signal having 480 effective scanning lines.
Since the configuration of FIG. 1 is almost the same, only different parts will be described.

The direct system signal output from the adder 303 and the interpolation system signal output from the adder 304 are 3 →
It is input to the 4 converter 311. In the 3 → 4 converter 311, 4/3 times expansion in the vertical direction is performed, and the number of effective scanning lines is 4
Eighty interlaced scanning signals are output. The output of the 3 → 4 converter 311 is input to the matrix circuit 222. The outputs of the 3 → 4 converters 216 and 217 are input to the buffer memories 220 and 221 respectively. With this configuration, it is possible to obtain the output of the interlaced scanning signal of 480 effective scanning lines.

FIG. 14 shows the configuration of the 3 → 4 converter 311. This is because of the configuration of the 3 → 4 converter 305 in FIG.
Only the output of the direct system is used. Therefore, the same parts as those of the 3 → 4 converter 305 in FIG.

FIG. 15 shows another example of the configuration of the 3 → 4 converter 311. This is realized by the configuration of FIG. 14 having two sets of coefficient units and adders, which are switched for each field, and these are set as one set, and the coefficients of the coefficient units are also switched for each field. To do.

Memory 525 and line memories 527 and 52
8, memory 526, line memories 529, 530, 53
The outputs of 1 are respectively assigned to coefficient units 561, 562, 563,
Input to 561, 565, 566, 567. Coefficient unit 5
61, 562, 563, 564, 565, 566, 56
In 7, the input signal is multiplied by a coefficient and output. Coefficient multiplier 561, 562, 563, 564, 56
The outputs of 5,566,567 are input to the adder 568,
The sum of all input signals is required. The output of the adder 568 is supplied to the terminal 569, and this becomes the output of the 3 → 4 converter 311.

Coefficient units 561, 562, 563, 564
The coefficients 565, 566, 567 are switched for each line and each field. 16 and 17 show these coefficients. FIG. 17 is a continuation of FIG. What is shown here represents a scan line. 16 (1),
FIG. 17A shows a memory 525, a line memory 527,
528, memory 526, line memories 529, 530,
The output of 531 is shown. 16 and 17 (2)
And (3) are coefficient units 561, 562, 563, 564,
The coefficients 565, 566 and 567 are shown, and the coefficients shown in (2) and (3) are switched for each field. These coefficient units 561, 562, 563, 564, 565, 5
The control of 66 and 567 is performed by the control signal from the control signal generation circuit 551.

FIG. 18 shows an embodiment of a decoder which outputs a sequential scanning signal having 360 effective scanning lines. Since the configuration is almost the same as that of FIG. 12, only different points will be described.

The progressive scanning signals of 360 effective scanning lines output from the progressive scanning converter 306 are input to the matrix circuit 222. In addition, H-LPF 214, 215
The outputs of the above are input to the progressive scan converters 218 and 219, respectively. With this configuration, it is possible to obtain the output of the sequential scanning signal having 360 effective scanning lines.

FIG. 19 shows an embodiment of a decoder which outputs an interlaced scanning signal having 360 effective scanning lines. FIG.
Since it is almost the same as the configuration of, the differences will be explained.

The output of the buffer memory 202 is V-LPF.
It is input to 321 and processing in the vertical direction is performed. The output of the time extension circuit 206 is input to the V-HPF 322 and processed in the vertical direction. V-LPF321 and V-HP
Both outputs of F322 are input to the adder 323. The output of the adder 323 is input to the matrix circuit 222.

The outputs of the H-LPFs 214 and 215 are input to the buffer memories 220 and 221 respectively. With this configuration, it is possible to obtain the output of the interlaced scanning signal of 360 effective scanning lines.

FIG. 20A shows the V-LPF 321 (see FIG.
The configuration of 9) is shown. This is the V-L shown in FIG.
Of the configuration of the PF 301, only the direct system is output.

FIG. 20B shows the V-HPF 322 (see FIG. 1).
The configuration of 9) is shown. This is the V-H shown in FIG.
Of the configuration of the PF 302, only the direct system is output.

As described above, according to the present invention,
Since the vertical filter and the 3 → 4 conversion process are performed based on the interlaced scanning signals of two systems, the number of line memories required for these processes can be reduced and the hardware scale can be reduced. Further, when an interlaced scanning decode signal is to be obtained, only one required system of the two systems need be performed, so that the hardware scale can be made much smaller than in the conventional case. Further, it is possible to adopt an appropriate structure for interlaced scanning, sequential scanning, and various decoders according to the number of effective scanning lines.

In the description of the embodiment, the configuration of the vertical filter and the 3 → 4 converter has been described as an example, but the present invention is not limited to this configuration and can be applied to other configurations. Further, in the above embodiment, when vertical filtering and 3 → 4 conversion are performed with the interlaced scanning signal in the same state, in order to reduce the scale of hardware as much as possible, those which can be shared between two systems are shared. However, even if the two systems are composed of completely independent circuits, the scale of the hardware is smaller than that of the conventional one.

[0086]

As described above, according to the present invention, the vertical filter and the 3 → 4 conversion process are performed on the basis of the signals of the interlaced scanning of two systems, and the number of line memories required for these processes. Can be reduced and the hardware scale can be reduced. Further, when an interlaced scanning decode signal is to be obtained, only one required system of the two systems need be performed, so that the hardware scale can be made much smaller than in the conventional case. Further, it is possible to adopt an appropriate structure for various decoders according to the interlaced scanning, the sequential scanning, and the number of effective scanning lines.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a vertical low pass filter (V-LPF).

FIG. 3 is an operation explanatory diagram of a V-LPF.

FIG. 4 is an explanatory diagram of a vertical high pass filter (V-HPF).

FIG. 5 is a diagram showing a specific circuit of a 3 → 4 converter.

FIG. 6 is a diagram showing the principle of 3 → 4 conversion processing.

FIG. 7 is an explanatory diagram showing signals and coefficients of each part of the circuit of FIG.

FIG. 8 is an explanatory view showing signals and coefficients of each part of the circuit of FIG.

FIG. 9 is a diagram showing a specific circuit of the 3 → 4 converter of FIG. 1.

10 is an explanatory diagram showing signals and coefficients of respective parts of the circuit of FIG.

FIG. 11 is an explanatory view showing signals and coefficients of each part of the circuit of FIG.

FIG. 12 is a diagram showing another embodiment of the present invention.

FIG. 13 is a diagram showing still another embodiment of the present invention.

FIG. 14 is a diagram showing a specific circuit of the 3 → 4 converter of FIG. 13;

FIG. 15 is a diagram showing another specific circuit of the 3 → 4 converter.

16 is an explanatory diagram showing signals and coefficients of each part of the circuit of FIG.

FIG. 17 is an explanatory diagram showing signals and coefficients of each part of the circuit of FIG.

FIG. 18 is a diagram showing still another embodiment of the present invention.

FIG. 19 is a diagram showing another embodiment of the present invention.

20 is a diagram showing V-LPF and V-HPF of FIG. 19. FIG.

FIG. 21 is an explanatory diagram of a screen of a rater box method.

FIG. 22 is a diagram showing an encoder for transmitting a television signal of a lator box system.

FIG. 23 is a diagram showing a decoder which receives a television signal of a transmitter box system and outputs a progressive scanning signal.

FIG. 24 is a diagram showing a decoder which receives a television signal of a lator box system and outputs an interlaced scanning signal.

[Explanation of symbols]

201 ... Y / C separation unit, 202, 205 ... Buffer memory, 206 ... Time expansion circuit, 212, 213 ... Multiplier,
214, 215 ... Horizontal low-pass filters, 216, 21
7 ... 3 → 4 converter, 218, 219 ... Sequential scan converter,
220, 221 ... Buffer memory, 222 ... Matrix circuit, 301, 321 ... Vertical low-pass filter (V-
LPF), 302, 322 ... Vertical high-pass filter (V
-HPF), 303, 304 ... Adder, 305 ... 3 → 4
Converter, 306 ... Progressive scan converter, 211, 311 ... 3
→ 4 converters.

Claims (9)

[Claims] 1. The same source but different frequency bands 1
An input end to which the video signal and the second video signal are input, and the first video signal and the second video signal are input,
A first signal processing means for outputting a third video signal having the same scanning rate as these video signals, and the first video means and the second video signal are inputted,
Second signal processing means for outputting a fourth video signal having the same scanning rate as these video signals, and the third video means and the fourth video signal
A video signal processing device, comprising: means for outputting an output video signal in which the scanning rate is converted by alternately switching two signals after compressing the time by a factor of 2; 2. An input terminal for inputting a first video signal and a second video signal, which have the same source but different frequency bands, and the first video signal and the second video signal are input.
First signal processing means for outputting a third video signal having the same scanning rate as these video signals; and the first video means and the second video signal are inputted,
Second signal processing means for outputting a fourth video signal having the same scanning rate as these video signals, the third video means and the fourth video signal are inputted,
Third signal processing means for outputting a fifth video signal at the same scanning rate as these video signals, said third video means and said fourth video signal are inputted,
Fourth signal processing means for outputting a sixth video signal having the same scanning rate as those of the video signals, one for the fifth video means and one for the sixth video signal
A video signal processing apparatus comprising: a unit for outputting an output video signal in which the scanning rate is converted by alternately switching two signals after compressing by a time of 2 times. 3. An input terminal for inputting a first video signal and a second video signal, which have the same source but different frequency bands, and the first video signal and the second video signal are input,
First signal processing means for outputting a third video signal having the same scanning rate as these video signals; and the first video means and the second video signal are inputted,
Second signal processing means for outputting a fourth video signal having the same scanning rate as these video signals, the third video means and the fourth video signal are inputted,
Third signal processing means for outputting a fifth video signal having the same scanning rate as these video signals, said third video means and said fourth video signal are inputted,
A video signal processing device comprising: a fourth signal processing means for outputting a sixth video signal having the same scanning rate as these video signals. 4. The video signal processing apparatus according to claim 1, wherein the first signal processing means and the second signal processing means are filtering processing in the vertical direction of the video signal. . 5. The video signal processing device according to claim 2, wherein the third signal processing means and the fourth signal processing means are vertical expansion processing of a video signal. . 6. The first signal processing means and the second signal processing means share a horizontal scanning period delay memory to be used, with each other. 4. The video signal processing device of 4. 7. The video signal processing apparatus according to claim 2, wherein the third signal processing means and the fourth signal processing means share image memories to be used. . 8. A signal which has been converted so that it can be received even by a current receiver by compressing a video signal that is longer than the current broadcast in the vertical direction and arranging it in the center of the screen to create a non-image part above and below Means for outputting, as the first video signal, a video signal in the central portion of the screen of the converted signal; and a signal transmitted by being multiplexed in upper and lower non-image parts of the converted signal, the second video signal. 4. A means for outputting as a video signal, further comprising:
Or 4 or 5 or 6 or 7 video signal processing device. 9. A vertical low-pass filter to which a video signal of a central screen of a video signal by letter-box interlaced scanning is input to obtain a direct low-frequency video signal and an interpolative low-frequency video signal, and the interlace. A vertical high-pass filter to which a video signal obtained by demodulating an auxiliary signal that has been multiplexed in upper and lower non-picture portions of a video signal by scanning is input to obtain a direct high-frequency video signal and an interpolating high-frequency video signal, A first wideband video signal obtained by adding the low-pass and high-pass video signals of the direct system and a second wideband video signal obtained by adding the low-pass and high-pass video signals of the interpolation system are input, and the respective video signals are input. And a converter for vertically extending the video signal.