JPH0721227A - Logic synthesis method for asynchronous logic circuit - Google Patents

Abstract

PURPOSE:To shorten prescribed time for optimizing an asynchronous logic circuit by automatically optimizing a circuit for setting a clock. CONSTITUTION:A clock network connected to the clock input terminal of a logic element in the asynchronous logic circuit is made into a group and it is detached from the asynchronous logic circuit. A part where the clock network of the asynchronous logic circuit is removed is divided for the respective different parts of a clock signal. Then, the asynchronous logic circuit is optimized by using a function simulation result for the respective different parts of the detached clock network and the divided clock signals. Namely, the clock network 20 is detached from the circuit, and the remaining logic circuit is divided into the different parts of the clock signal. The clock network 20 is detached as a module 3, and the remaining circuit is divided into a module 1 including only a flip flop 3 and a module 2 including flip flops 4 and 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application specific integrated circuit (ASIC) design method, and more particularly to an asynchronous logic circuit in which an output of a combinational circuit is input as an asynchronous clock to a clock input terminal of a logic element. The present invention relates to a logic synthesis method of an asynchronous logic circuit for generating a netlist of the above using a logic synthesis device.

[0002]

2. Description of the Related Art FIG. 23 shows an example of an asynchronous logic circuit targeted by the present invention. In the figure, an AND circuit 2 is connected to the clock input terminal of the flip-flop 1, and its output is given as an asynchronous clock.

FIG. 24 shows an example of a logic circuit using an asynchronous multiphase clock. In the figure, a clock net as an output of the AND circuit 6 is connected to the flip-flop 3, and a clock net as an output of the AND circuit 7 is connected to the flip-flops 4 and 5. These clocks are asynchronous clocks as in FIG.

When optimizing such an asynchronous logic circuit, the logic synthesizer side predicts what the waveforms of the two inputs CS and WT to the AND circuit 2 will be, for example, in FIG. However, the timing related to the clock input of the flip-flop 1, that is, the operating frequency cannot be obtained, and it is difficult to obtain an optimum circuit.

FIG. 25 is an explanatory diagram of a conventional method of setting a clock in optimization of such an asynchronous logic circuit. FIG. 1A shows the first conventional method. In this method, the designer manually sets the clock that satisfies the specifications at the output point of the AND circuit.

FIG. 25 (b) shows a second conventional method. In this method, the clock network is manually divided into blocks (hierarchical structure) and separated from the logic circuit, and the designer manually sets the clocks for the clock input terminals of the remaining logic circuits.

[0007]

In the conventional logic synthesis method described above, an optimum circuit cannot be obtained unless an appropriate clock constraint is set for a complicated asynchronous circuit. There is a problem that the circuit does not operate at the required frequency because of the unknown. Further, when the clock constraint is manually set to obtain the optimum circuit, there is a problem that the time required for setting the clock to obtain the optimum circuit becomes very long.

The present invention is to shorten the time required for optimizing an asynchronous logic circuit by utilizing the result of functional simulation for the asynchronous logic circuit.

[0009]

FIG. 1 is a functional block diagram of the present invention. This figure shows the function of the logic synthesis method of an asynchronous logic circuit that optimizes using the results of functional simulation in an asynchronous logic circuit in which the output of the combination circuit is input as an asynchronous clock to the clock input terminal of the logic element. It is a block diagram.

In FIG. 1, first, at 10, the clock networks connected to the clock input terminals of the logic elements in the asynchronous logic circuit are grouped and separated from the asynchronous logic circuit.

In 11, the portion of the asynchronous logic circuit excluding the clock network is divided into different portions of the clock signal, and in 12 the separated clock network and the divided portion of the divided clock signal are optimized for the asynchronous logic circuit. Optimization is performed using the results of functional simulation.

For example, in the logic circuit of FIG. 24, the clock net and the clock net are divided into blocks as a clock network, and the remaining logic circuits are divided for different clocks. In this case, since the clock input to the flip-flop 3 and the clock input to the flip-flops 4 and 5 are different, for example, only the flip-flop 3 is divided as one part, and, for example, the combination circuit 8 between the flip-flops 3 and 4 is divided. , And all other parts are split as other parts.

In the present invention, the functional simulation result used in the optimization performed for each different part of the separated clock network and divided clock signal is, for example, a change in the signal value for the functional block of the asynchronous logic circuit. The minimum change time defined as the minimum time from the occurrence of the change to the change that is the same or different, and the minimum change ratio defined as the ratio of the minimum change time to the basic clock cycle of the asynchronous logic circuit. is there.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows an example of an asynchronous logic circuit using an asynchronous multiphase clock, which is the object of the present invention. This figure is substantially the same as FIG. 24, but a clock network composed of clock nets and clock nets is hierarchized as one group 20.

FIG. 3 shows the result of disconnecting the clock network 20 from the circuit of FIG. 2 and dividing the remaining logic circuit into different parts of the clock signal. In the figure, the clock network is separated as module 3,
The remaining logic circuit is divided into a module 1 including only the flip-flop 3 and a module 2 including the flip-flops 4 and 5.

FIG. 4 shows an example of another logic circuit using an asynchronous multiphase clock. In the figure, the input D2EN to the AND circuit 25 is 4-bit data, and the logical product of these 4 bits and the output D2CK of the flip-flop 21 is output from the AND circuit 25. The same applies to the input D3EN to the AND circuit 26.

FIG. 5 shows the result of hierarchical (grouping) the clock network in the logic circuit of FIG. The clock networks are grouped as block 30.

FIG. 6 shows the result of disconnecting the clock network from the circuits of FIGS. 4 and 5 and dividing the remaining logic circuit into different parts of the clock. FIG. 7 shows a third example of a logic circuit using an asynchronous clock. In the figure, the same clock is input to the two flip-flops 31 and 32, and the clock network is composed of three AND circuits 33 to 35 and an OR circuit 36.

FIG. 8 shows the result of separating the clock network from the circuit of FIG. 7, FIG. 8 (a) shows the remaining logic circuit, and FIG. 8 (b) shows the separated clock network. FIG. 9 shows the result of functional simulation for the logic circuit of FIG. From the results of these functional simulations, the minimum change time and the minimum change ratio used in the optimization of the asynchronous logic circuit according to the present invention will be described below.

FIG. 10 is an explanatory diagram of the minimum change time used for optimization. The minimum change time is defined as the time from the occurrence of a certain change in the value of a signal of a functional block of a logic circuit until the change that is the same as or different from it, and therefore generally, there are multiple types of minimum change times. Although it can be defined, the type of the minimum change time used in the logic synthesis of the circuit is specified by the type of the circuit or the attribute of the pin.

Although many kinds of minimum change times can be defined in FIG. 10, three kinds of minimum change times are used for the clock signal in this embodiment. Figure 1
1 indicates three types of minimum change times defined for the functional simulation result of FIG.
To CK3. Here, the minimum change time is defined as three types of time from the rising edge to the next rising edge, the rising edge to the next falling edge, and the falling edge to the next rising edge. These three types are necessary to define the operating cycle of the clock.

FIG. 12 shows the definition result of the clock timing using the minimum change time of FIG.
, The operation cycle is 3, the operation cycle is 7 for CK2, and the operation cycle is 14 for CK3.

The clock cycle in FIG. 12 corresponds to the minimum operating cycle of the clock, in other words, the fastest operating frequency. FIG. 13 is an explanatory diagram of the minimum operation cycle. In the same figure, the process of obtaining the minimum operation cycle from the waveforms of the two inputs D1EN to the AND circuit 24 and the output CK1 to D1CK in FIG. 4 is shown.

Before describing the optimization of the clock network using the minimum change time and the like, the optimization of the portion of the divided logic circuit other than the clock network will be briefly described. FIG. 14 shows an example of optimization according to the design rule. This figure is an optimization regarding the design rule between the driving capability of the flip-flop 21 and the load coefficient of the input terminal of the AND circuit 25 in the circuit of FIG. That is, if the driving capability of the flip-flop 21 is 10 and the load coefficient of the input terminal D2CK of the AND circuit 25 is 30, then there is a design rule error. 21
The buffer 40 is inserted between the output terminal of the AND circuit and the input terminal D2CK of the AND circuit 25, and the drive capability is increased to 36 as the output of this buffer, whereby the optimization satisfying the design rule is performed.

Next, setting of a clock cycle in the clock network will be described with reference to FIGS. FIG. 15 shows an example of a target circuit for setting a clock using the minimum change time and the minimum change ratio of the entire output OUT. In the figure, the circuit is composed of flip-flops 41 to 43 and an AND circuit 44.

FIG. 16 shows the result of functional simulation for the circuit of FIG. As a result, the minimum change time of the output OUT becomes "3" when the reference clock cycle is "1", and the minimum change ratio as a ratio of the minimum change time to the reference clock cycle is also "3".

This minimum change ratio is a value corresponding to how fast the signal changes with respect to the reference clock. Here, the output X of the AND circuit 44 is 3 at the shortest after all.
AND circuit 4 because it changes due to the clock
It is only necessary to determine the output X within 3 clocks (actually it is necessary to consider the setup time and the hold time) after either one of the two inputs W1 and W2 of 4 changes.

FIG. 17 is an explanatory diagram of the virtual clock set using the result of FIG. A clock having a cycle three times as long as the reference clock is used as the virtual clock. In this way, it is possible to set the clock constraint using the minimum change time and the minimum change ratio. However, in practice, the reference clock operates faster than the timing set by this method, and as shown in FIG. It is necessary to secure a timing mask area in order to prevent the signal value of the output X from changing in this area.

18 to 21 are for explaining the optimization described in FIGS. 15 to 17 in more detail. FIG. 18 shows a simulation result similar to that shown in FIG. 16, but here, in association with the output X of the AND circuit 44, the minimum change time of the signal between the input terminals W1 and X,
The minimum change time of the signal between the inputs W2 and X is shown. This minimum change time is, for example, for a signal between W1 and X, when the output X rises later than in the figure, this minimum change time is extended and when the clock cycle is set to “1”, the minimum change time is It means to exceed "2". Then, based on this minimum change time, the maximum delay time between W1 and X and the maximum delay time between W2 and X can be set on the side of the logic synthesizer.

FIG. 19 shows the relationship between the flip-flop setup time and hold time and the rising edge of the virtual clock when the virtual clock is used with the clock signal for the flip-flop 43 shown in FIG. 15 as CK3. As described above, since it is possible to set a virtual clock that is an integral multiple of the operation cycle of the reference clock, here three times, the data input to the flip-flop 43, that is, the relationship between X and the clock, the setup time and the hold time are Even if it is considered, it can be sufficiently relaxed, and optimization can be performed according to the function of the circuit.

FIG. 20 is an explanatory diagram of the virtual clock. As shown in the figure, the cycle of the virtual clock, '6', is obtained by multiplying the operation cycle of the reference clock by the minimum change ratio '3'.

FIG. 21 is a detailed explanatory diagram of the timing mask area. The timing mask area indicates a time when the signal value of the output X of the AND circuit 44 in FIG. 15 should not change with respect to the reference clock. As aforementioned,
The minimum change time of the signal between the input W1 and the output X of this AND circuit is "2", and the delay time from the change of the signal W1 to the output of X should be "2" or less. become. However, the cycle of the clock that actually operates is "1", and there occurs a time zone in which the signal level of X must not change even within the time of the minimum change time of the signal between W1 and X. The time is a time zone in which the setup time and the hold time are added with reference to an integer multiple of the reference clock. Further, in practice, since the delay time due to the wiring is also included, it is more accurately the time zone in which the setup time, the hold time, and the wiring delay time are added.

As described above, the functional simulation result,
That is, the minimum change time and the minimum change ratio can be used to set the clock cycle in the clock network. However, for example, the maximum delay time can be set for the circuits between the flip-flops. The range of trade-off between the gate area and the speed of the combinational circuit in the mutual data path is expanded, and the optimization result of the logic circuit is improved.

FIG. 22 is an explanatory diagram of gate optimization as a combinational circuit. When the gate circuit in Fig. 6 (a) is optimized and becomes as shown in Fig. 6 (b), the gate area is 12 to 8
In addition, the delay time improves from 0.6ns to 0.4ns.

As described above, each of the clock network separated as one group and the logic circuit divided for each different portion of the clock signal is individually optimized, and the result is finally realized as one circuit. Is connected to and the logic synthesis of the asynchronous circuit is performed.

[0036]

As described in detail above, according to the present invention, in the logic synthesis of the logic circuit using the asynchronous and multi-phase clocks, the optimum circuit operation such as the clock setting which was manually performed It is possible to automatically perform the optimization, and the minimum change time as a result of functional simulation,
The circuit can be optimized by using the minimum change ratio.

[Brief description of drawings]

FIG. 1 is a functional block diagram of the present invention.

FIG. 2 is a diagram showing an example of a circuit using an asynchronous multiphase clock as an object of the present invention.

FIG. 3 is a diagram showing a division result of the circuit of FIG.

FIG. 4 is a second logic circuit using an asynchronous multiphase clock.
It is a figure which shows the example of.

5 is a diagram showing a result of grouping clock networks in the logic circuit of FIG.

6 is a diagram showing a result of division of the logic circuit of FIG.

FIG. 7 is a diagram showing a third example of an asynchronous logic circuit.

FIG. 8 is a diagram showing a division result of the circuit of FIG.

9 is a diagram showing a result of functional simulation of the logic circuit of FIG.

FIG. 10 is a diagram illustrating the definition of the minimum change time.

FIG. 11 is an explanatory diagram of a minimum change time with respect to a clock signal.

FIG. 12 is a diagram illustrating the definition of clock timing using the minimum change time.

FIG. 13 is an explanatory diagram of a minimum operation cycle corresponding to the fastest operation frequency.

FIG. 14 is an explanatory diagram of logic circuit optimization using design rules.

FIG. 15 is a diagram showing an example of a circuit for explaining setting of a clock cycle in a clock network.

16 is a diagram showing simulation results for the logic circuit of FIG.

17 is a diagram illustrating setting of a virtual clock for the circuit of FIG.

FIG. 18 is a diagram showing a result of functional simulation including an output X of an AND circuit 44 for the circuit of FIG. 15.

FIG. 19 is a diagram illustrating a relationship between a virtual clock, a setup time, and a hold time.

FIG. 20 is a diagram illustrating a relationship between periods of a virtual clock and a reference clock.

FIG. 21 is a detailed explanatory diagram of a timing mask area.

FIG. 22 is a diagram for explaining optimization of a gate area and a delay time of a combinational circuit.

FIG. 23 is a diagram showing an example of a logic circuit using an asynchronous clock.

FIG. 24 is a diagram showing an example of a logic circuit using an asynchronous multiphase clock.

FIG. 25 is a diagram illustrating a conventional method of setting a clock of an asynchronous logic circuit.

[Explanation of symbols]

1,3 to 5 Flip-flops 2,6,7 AND circuit 8,9 Combination circuit 20 Hierarchical (grouped) clock network 21-23 Flip-flops 24-26 AND circuit 30 Hierarchical (grouped) clock network

Claims (2)

[Claims] 1. In an asynchronous logic circuit in which an output of a combinational circuit is input as an asynchronous clock to a clock input terminal of a logic element, a group of clock networks connected to clock input terminals of logic elements in the asynchronous logic circuit is grouped. And disconnecting the asynchronous logic circuit from the asynchronous logic circuit (10), dividing a part of the asynchronous logic circuit excluding the clock network into different parts of the clock signal (11), the separated clock network, and the divided clock network. A logic synthesis method for an asynchronous logic circuit, characterized in that optimization is performed for each different portion of the clock signal by utilizing a result of functional simulation of the asynchronous logic circuit (12). 2. The minimum value of the result of the functional simulation used for performing the optimization from the time when a certain change occurs in the signal value of the functional block of the asynchronous logic circuit to the time when the same or different change occurs. A minimum change time defined as time, and a minimum change ratio defined as a ratio of the minimum change time and a basic clock cycle in the asynchronous logic circuit.
A method for synthesizing the described asynchronous logic circuit.