JPH07212276A - System switching synchronizer - Google Patents

Abstract

PURPOSE:To provide a system switching synchronizing system for autonomously and speedily switching a system without fail even at the time of fault generation and for repairing the fault as well. CONSTITUTION:A state deciding part 7 combines a state indicate signal 15 from respective state indicating parts 6 of duplex systems 1 for transiting a system state instruction with a state decision control signal from a state switching part 3 corresponding to the combination of a state instruction control signal 012 from the state switching part 3, which dispatches control information and monitor information to a system supervisory and control part 2 according to the state deciding signal 16 only when control commands 11 from respective system supervisory and control parts 2 of the duplex systems 1, and present system and opposite system fault signals 013 and 014 from present system and opposite system fault processing parts 4 and 5 for detecting present system and opposite system faults, and a synchronizing control part 8 to be synchronized with the timing of an operating state even in the case of setting the system in a non-operating state outputs a timing signal 18 according to the state deciding signal 16 for transiting and outputting system state decision. The input/ output of an inter-system signal is reset by an inter-system signal input/output part 9 for buffering it corresponding to an output reset signal 19 from the state switching part 3, and a buffer fault is detected and reported 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system switching synchronizer for switching between operating and non-operating system states in a dual system such as a digital transmission device and a digital exchange in a highly reliable manner.

[0002]

2. Description of the Related Art A conventional system switching synchronizer disclosed in, for example, Japanese Patent Laid-Open No. 262936/1988, as shown in FIG. 5, has its own system 100a and another system 100b operated as a working system and a standby system, respectively. Switches each inactive system status in synchronization. The external system switching command unit 200 issues a command 110 for switching between the own system 100a and the other system 100b without duplication. The state determination units 70a and 70b are the system switching command unit 200.
The system switching command 110 from is subjected to exclusive OR with the mounting position information designating the system at the voltage level (0 V and 5 V) to determine the system state of operation and non-operation. The synchronization control units 80a and 80b receive the state determination signal 1 from the state determination units 70a and 70b of the own system and the state determination units 70b and 70a of the partner system.
According to 60a and 160b and 160b and 160a, each system state in which one of the two systems is "operating" and the other is "non-operating" is determined. In the operating system state, the synchronizing signals 170a and 170b are generated and output from the own system to the other system. In the non-operating state, it synchronizes with the synchronization signals 170b and 170a from the partner system,
The timing signals 180a and 180b (clock signal, frame signal, etc.) are output.

The conventional system switching synchronization device adopts a system switching synchronization system (single system switching synchronization system) configured to synchronize with a synchronization signal from a partner system without duplicating a system switching command.

[0004]

SUMMARY OF THE INVENTION In the conventional system switching synchronizer as described above, it is suitable for malfunction or inability of system switching when the system switching command unit which is not redundant is broken or when the system switching command is disconnected. Can not be processed. When the input system fails, there is a possibility of misidentifying the operating and non-operating states of each system. When the own system or the partner system fails, the system cannot be switched autonomously and quickly. In addition, there were many problems in terms of reliability, such as the failure location could not be specified.

The problem to be solved by the present invention is to duplicate the system switching system by itself so that the system switching and synchronizing device can switch the system autonomously and quickly without error even when a failure occurs and the failure can be repaired. It is to provide a system switching synchronization system (combined system switching synchronization system) configured to determine each system state of operation and non-operation by the combination of the system and the partner system.

[0006]

The system switching synchronizer of the present invention synchronizes and switches the operating and non-operating system states in each of the dual systems, and is provided with the following means in order to solve the above problems. The system is characterized by adopting a combined system switching synchronization method so that even when a failure occurs, the system can be autonomously and swiftly switched without error and the failure can be repaired.

The system supervisory control unit is duplicated. System monitoring and control is performed based on monitoring / control information with the state switching unit, and control commands are issued.

The state switching section is duplicated. The control information is output from the system monitoring control unit according to the status determination signal from the status determination unit only when the control commands from the system monitoring control unit of the own system and the partner system are compared and match each other, and the system monitoring control unit Outputs monitoring information to.

The own system failure processing section is duplicated. It detects and outputs its own system fault information and notifies it. Alternatively, the self-system failure information is detected by the self-system and output to the partner system, and the self-system failure information detected and output by the partner system is also output to the status indicator, and the self-system failure notification is sent to the status switching unit as monitoring information. To do.

The partner system failure processing section is duplicated. Detects, outputs, and notifies the partner system failure information. Alternatively, the partner system failure information is detected by the own system and output to the partner system, and the partner system failure information detected and output by the partner system is also output to the status indicator, and the partner switching failure notification is sent to the status switching unit as monitoring information. To do.

The status indicating section is duplicated. A combination of the status instruction control signal from the status switching section and the failure signals of the own system and the partner system from the respective failure processing sections of the own system and the partner system transits the status indication of each system of operation and non-operation.

The state determination unit is duplicated. A combination of the state determination control signal from the state switching unit and each state instruction signal from the duplicated state instruction unit makes a transition between the operating and non-operating system state determinations.

The synchronization controller duplicates. According to the state determination signal from the state determination unit, it outputs as a timing signal in synchronization with the timing of the operating state even when the system is in the non-operating state.

The intersystem signal input / output unit is duplicated. The input / output of the intersystem signal is buffered, and the output is reset by the output reset signal from the state switching unit. Alternatively, in addition to the above, an I / O buffer fault is detected and an I / O buffer fault is notified to the state switching unit as monitoring information.

[0015]

With the above-mentioned means, the system switching synchronizer of the present invention firstly compares the control commands of the dual system with each other to prevent system switching due to malfunction of the system supervisory control unit. Next, the state indication of each operation and non-operation is transited by the combination of the state instruction control signal and each fault signal of the own system and the partner system. When the status indicating unit fails, the status indicating signal is reset and the system is forcibly switched. When the system switching error occurs, each fault signal of the own system and the partner system is ignored, the state instruction signal is determined, and the system returns to the normal state. In addition, the state determination control signal for each duplex system and each state designation signal for the duplex system are combined to make a transition between the active and non-active system state determinations. System switching The system is not switched by only a single failure of the system. One of the duplex systems is in the operating state and the other is in the non-operating state, and neither of them is in the operating or non-operating state. In addition, the system input / output unit pulls up the input, and when a power failure, a device is disconnected, or a system disconnection occurs, a fault is detected instantly and the system is switched to recover. Or I / O buffer failure is detected,
Output as monitoring information. In addition, each failure processing unit of the own system and the partner system detects each failure of the dual system and outputs it as monitoring information. When the states of the duplex system are inconsistent, the faulty part is specified.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a system switching synchronizer according to an embodiment of the present invention has its own system 1a and another system 1b, for example, as an active system and a standby system, each of which is operating and inactive. Synchronize and switch. The system supervisory control units 2a and 2b monitor and control the self system 1a and the other system 1b by the monitoring / control information 10a and 10b between the state switching units 3a and 3b, and also issue the control commands 11a and 11b. The state switching units 3a and 3b are control commands 12a, 12b and 12 from the system monitoring control units 2a and 2b of the own system and the system monitoring control units 2b and 2a of the partner system.
Only when b and 12a are collated with each other and coincident with each other, the state instruction control signal 01 is sent from the system supervisory control units 2a and 2b according to the state determination signals 16a and 16b from the state determination units 7a and 7b.
2a and 012b, state determination control signals 12a and 12b, and output reset signals 19a and 19b are output as control information. Further, the system supervisory control units 2a and 2b are notified of their own system faults 015a and 015 from their own system fault processing units 4a and 4b.
b, partner system fault notifications 016a and 016b from partner system fault processing units 5a and 5b, state determination signals 16a and 16b from state determining units 7a and 7b, and input / output buffer faults from intersystem signal input / output units 9a and 9b The notifications 20a and 20b are output as monitoring information. Own system failure processing units 4a and 4b
Detects its own system fault information in its own system 1a and 1b and outputs it as its own system detection signal 13a and 13b of its own system detection, and also detects and outputs its own system fault information in the other system 1b and 1a. Together with the partner system failure signals 14b and 14a for detecting the partner system from the processing units 5a and 5b, they are output as own system and partner system failure signals 013a and 013b for partner system detection. Further, it issues own system fault notifications 015a and 015b. The partner system failure processing units 5a and 5b detect the partner system failure information by the own system 1a and 1b and output it as the partner system failure signals 14a and 14b for detecting the own system, and the partner system failure information. Self-system failure signal 13 detected by the self-system failure processing units 4b and 4a for detection of the partner system
Together with b and 13a, it outputs as partner system fault information 014a and 014b for detecting the own system and the partner system. Also, the partner system failure notifications 016a and 016b are issued. Status indicator 6a and 6
b is the state instruction control signal 0 from the state switching units 3a and 3b.
12a and 012b, own system failure signals 013a and 013b from own system failure processing units 4a and 4b, and partner system failure signals 014a and 014 from partner system failure processing units 5a and 5b.
With the combination of b, transition of each system status indication of operation and non-operation,
It is output as the state instruction signals 15a and 15b. The state deciding units 7a and 7b include the state deciding control signals 12a and 12b from the state switching units 3a and 3b and the state indicating units 6a and 6 of the own system.
state instruction signals 15a and 15b from the terminal b, and state instruction signals 15b and 15a from the state instruction units 6b and 6a of the partner system.
The system state transitions of the operating state and the non-operating state are transited by the combination of and the state determining signals 16a and 16b are output. According to the state determination signals 16a and 16b from the state determination units 7a and 7b, the synchronization control units 8a and 8b synchronize with the timing of the operating state even when the system is in the non-operating state, and the timing signals 18a and 18b.
Output as (clock signal, frame signal, etc.).
The intersystem signal input / output units 9a and 9b are connected to the own system fault processing unit 4a.
And 4b, partner input / output signals of fault processing units 5a and 5b and synchronization control units 8a and 8b, and output signals of status indicator units 6a and 6b of own system and status indicator units 6b and 6a of partner system, respectively. To ring. State switching unit 3a
The output reset signals 19a and 19b from the output signals 3a and 3b reset the output signals. The I / O buffer failure is detected and the I / O buffer failure notifications 20a and 20b are issued.

In the system switching synchronizer of the above embodiment, the system switching system is duplicated so that the system can be switched autonomously and quickly without error even when a failure occurs and the failure can be repaired. The system switching synchronization method (combination system switching synchronization method) configured to determine each system state of operation and non-operation is adopted.

The system supervisory control units 2a and 2b and the state switching units 3a and 3b have their own system 1a and the other system 1b, respectively, not only when the own system 1a and the other system 1b are operating, but also when they are not operating. The system is controlled only when the control commands 11a and 11b and 11b and 11a from the system monitoring control units 2a and 2b of the other system and the system monitoring control units 2b and 2a of the partner system match, and an error signal is output when they do not match. To do. There is an effect that malfunction due to runaway at the time of failure can be avoided, and it can be easily repaired by the procedure of replacing the non-operating system and then the operating system.

In the H / W (hardware) uncontrollable mode in which the state instructing units 6a and 6b are forcibly switched over when the partner system fault is erroneously recognized by the control information from the state switching units 3a and 3b as shown in FIG. The state instruction transitions as in the state instruction control signals 012a and 012b from the state switching units 3a and 3b, and outputs the state instruction signals 15a and 15b. In other normal H / W controllable modes, own system fault signals 013a and 013b from own system fault processing units 4a and 4b.
If the signal logics of the partner system failure signals 014a and 014b from the partner system failure processing units 5a and 5b are "H" and "L" (when the own system and the partner system are "normal"), the state instruction control signal 012a. And 012b, if the signal logic of only the own system fault signals 013a and 013b is "L" (when only the own system is "fault"), the signal logic is fixed to "H"("non-operation" state), the other system If the signal logic of only the fault signals 014a and 014b is "H" (when only the partner system is "fault"), the state logic is fixed to "L"("operation" state), and the state designation signal is changed. It outputs as 15a and 15b.

As shown in FIG. 3, the state decision units 7a and 7b use the control information from the state changeover units 3a and 3b in the H / W uncontrollable mode in which the system is forcibly changed over during the operation test. And state determination control signals 12a and 12b from
The state determination transitions as shown in FIG.
Output as 6b. In other normal H / W controllable modes, the status indicating signals 15a and 1 from the status indicating sections 6a and 6b of the own system and the status indicating sections 6b and 6a of the partner system, respectively.
Signal logic of 5b and 15b and 15a is "L" and "H"
And "H" and "L", the signal logics are "L" and "H"("operating" state and "non-operating" state), and the signal logics of the state indicating signals 15a and 15b and 15b and 15a are "L". , "L" and "H" and "H", the state determination is transited to "maintain previous state" and the state determination signal 1
Output as 6a and 16b. State determination signals 16a and 1
6b does not switch between operating and non-operating system states when one of the own system state instruction signals 16a and 16b and the partner system state instruction signals 16b and 16a malfunctions. Switch when both make state transitions. Both the own system 1a and the other system 1b never enter the operating or non-operating state.

The intersystem signal input / output units 9a and 9b are shown in FIG.
First, the own system fault signals 13a and 13b from the own system fault processing units 4a and 4b, and the partner system fault processing units 5a and 5b.
partner system fault signals 14a and 14b from b, and a state indicator 6
In response to the state instruction signals 15a and 15b from a and 6b and the synchronization signals 17a and 17b from the synchronization control units 8a and 8b, signal input units 91a and 91b and a signal output unit 92a.
And 92b buffer the input and output signals, respectively. Next, the signal input / output units 91 and 92 are shown in FIG.
As shown in (b) and (c), input / output buffers 911 and 92
1 and I / O buffer failure detection buffers 912 and 92
I / O buffer fault detection gate 91 for each output of 2
3 and 923 are exclusive ORed to generate respective I / O buffer fault signals B and C. Resistor 914 of signal input unit 91
The input signal is pulled up by and the output reset signal 19 from the state switching unit 3 resets the output signal of the signal output unit 92. Further, the input / output buffer fault output gates 93a and 93b are connected to the signal input / output units 91 and 9 as shown in FIG.
I / O buffer fault signals B and C from 2 are subjected to exclusive OR, and I / O buffer fault notifications 20a and 20b
do.

For example, when the own system 1a is in the "operating" state and the other system 1b is in the "non-operating" state, when the own system failure information generated by the own system 1a is detected by the own system failure processing unit 4a, the own system 1a is detected. The fault signal 013a becomes "L" and the partner fault signal 014b becomes "H" because the own system fault signal 13a is input to the partner fault processing unit 5b. When the partner system failure processing unit 5b detects the own system failure information generated by the own system 1a,
The partner system failure signal 014b becomes "H" and the partner system failure signal 013b becomes "L" because the partner system failure signal 14b is input to the own system failure processing unit 4a. Therefore, in any case, the combination of the state indication signals 15a and 15a shown in FIG.
b becomes "H" and "L", and the state determination signals 16a and 16b become "H" and "L" in the combination of FIG.
The other system 1b is switched to each system state in which "a" is "non-operation" and the other system 1b is "operation". In addition, it is not the partner, but the failure of the partner system
When detected by b, the system 1a is switched to each system state of "non-operation" and the other system 1b of "operation" in the same manner as above. First, in this state, for example, the own system 1a is replaced. Actually, the fault detection is continued because it is the cause of the partner system fault processing unit 5b itself. Next, in this state, it is judged that there is a failure in the intersystem wiring or the other system 1b, and the intersystem wiring is replaced, for example. At this time
Since the input signal logic of the signal input unit 91 becomes "H" by pulling up as shown in (b), the own system fault signals 013a from the own system fault processing units 4a and 4b and the partner system fault processing units 5a and 5b are output. 013b and partner system failure signal 014
a and 014b are each considered "H". Therefore, in the combination of FIG. 2 and FIG. 3, the state instruction signals 15a and 15b both become "L", and the state determination signal 16b "maintains the previous state".
Therefore, you can continue operating without problems. Further, if the partner system failure processing unit 5b continues to detect a failure, it is determined that the other system 1b has a failure. At this time, in the H / W controllable mode as shown in FIG. 2, the own system fault signals 013a and 013b and the partner system fault signals 014a and 014b are respectively “H”.
The system cannot be switched because it is considered. Therefore, the state instruction control signals 12a and 12b in the H / W control disabled mode are set to [L].
When the power failure occurs in the own system 1a, the input signal logic of the signal input unit 91b from the own system 1a to the other system 1b is "H". Therefore, the own system fault signal 013b and the partner system fault signal 0
Both 14b are considered "H". Therefore, the state determination unit 7
The state instruction signal 15b of the own system to b becomes "L" as in the above, the state instruction signal 15a of the partner system becomes "H" because it is pulled up, and the state determination signal 16b becomes "L". Therefore, the system state of the other system 1b is switched from "non-operation" to "operation". It is very fast because it is determined only by the gate delay time from the time of failure occurrence. Note that the same effect can be obtained when a device in the operating system is accidentally disconnected or the system is disconnected. Further, when the own system fault signal 13a is disconnected between systems, the own system 1a
Is not detected as a fault in its own system, but the other system 1b is detected as a fault in another system.
Both 5a and 15b are set to "L", and the state determination signals 16a and 16b are both set to "maintain previous state". Therefore, the system state is not switched. Since both systems are about to enter the operating state, it is possible to detect a discrepancy between the states of both systems, the system monitoring control units 2a and 2b monitor the states of both systems, and the intersystem signal input / output units 9a and 9b detect a buffer failure. Since a function is provided, if a buffer failure occurs, it can be determined that there is a disconnection between systems.

In the above embodiment, the state determining units 7a and 7b are used.
Is only when both of the status signals 15a and 15b and 15b and 15a from the status indicating units 6a and 6b of the own system and the status indicating units 6b and 6a of the partner system transit the status indication,
Needless to say, if the state determination signals 16a and 16b are defined so as to transit the state determination, the same effect can be obtained even if the signal logic is inverted.

Needless to say, in the above embodiment, the signal input section 91 has the same effect even if the input signal is pulled down instead of being pulled up and the signal logic is inverted.

[0025]

According to the system switching synchronizer of the present invention as described above, the system switching system is duplicated and the system switching system is configured to determine the operating and non-operating system states by the combination of the own system and the other system. Since a synchronous system is adopted, compared to the conventional single system switching synchronous system that is configured to synchronize with the synchronization signal from the other system without duplicating the system switching command, it is autonomous and quicker even when a failure occurs. There is an effect that the system can be switched without error and the failure can be repaired.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a system switching synchronization device of an embodiment showing the present invention.

FIG. 2 is a diagram for explaining the state transition of a state instruction section shown in FIG.

FIG. 3 is a diagram illustrating state transitions of a state determination unit shown in FIG.

FIG. 4 is a functional block diagram of an intersystem signal input / output unit shown in FIG.

FIG. 5 is a functional block diagram of a conventional system switching synchronization device.

[Explanation of symbols]

 1 system 2 system monitoring control unit 3 status switching unit 4 own system failure processing unit 5 partner system failure processing unit 6 status instruction unit 7 status determination unit 8 synchronization control unit 9 intersystem signal input / output unit 10 monitoring / control information 11 control command 12 State indication control signal 012 State determination control signal 13 Self-system fault signal for self-system detection 013 Self-system and partner system fault signal 14 self-system detection partner system fault signal 014 Self-system and partner system partner system Failure signal 015 Self-system failure notification 016 Counterpart system failure notification 15 Status indication signal 16 Status determination signal 17 Synchronization signal 18 Timing signal 19 Output reset signal 20 Input / output buffer failure notification In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04M 3/22 B H04Q 11/04

Claims (3)

[Claims] 1. A system switching synchronizer for synchronizing and switching between operating and non-operating system states in each of the dual systems, wherein system control is performed by monitoring / controlling the system by monitoring / control information with a state switching unit. The redundant system monitoring control unit and the system monitoring control unit according to the status determination signal from the status determination unit only when the respective control commands from the system monitoring control unit of the own system and the partner system mutually collate and match. A redundant status switching unit that outputs control information and outputs monitoring information to the system monitoring control unit; and a redundant own system failure processing unit that detects, outputs, and notifies own system failure information,
Redundant partner system failure processing unit for detecting, outputting and notifying partner system failure information, status indication control signal from the status switching unit, and own system and partner system failure signals from the own system and partner system failure processing units In the combination of, a combination of the duplexed state instruction unit for transitioning each system state instruction of operation and non-operation, and the state determination control signal from the state switching unit and each state instruction signal from the duplexed state instruction unit, According to the status determination signal from the duplex status determination unit that makes a transition between operating and non-operating system status determinations, duplex synchronization that outputs a timing signal in synchronization with the operating status timing even when the system is inactive, according to the status determination signal from the status determining unit. Buffering the input and output of signals between the control unit and the system,
A system switching synchronization device comprising: a duplex intersystem signal input / output unit that resets an output with an output reset signal from the state switching unit. 2. The self-system failure information is detected by the self-system and output to the partner system, and the self-system failure information detected and output by the partner system is also output to the status instructing unit, and the status switching unit itself monitors the information. Duplicated own system failure processing unit that notifies system failure and partner system failure information detected by the own system and output to the partner system, and partner system failure information detected and output by the partner system is also output to the status indication unit, 2. The system switching synchronization device according to claim 1, wherein the status switching unit is provided with a redundant partner system failure processing unit that notifies the partner system failure as monitoring information. 3. The redundant input / output signal input / output unit is provided with a unit for detecting an input / output buffer fault, and the state switching unit is notified of the input / output buffer fault as monitoring information. System switching synchronizer.