JPH07211099A - Semiconductor storage device testing apparatus - Google Patents

Abstract

PURPOSE:To keep input margin for high speed judgment without receiving an influence of process variations of FET by generating a judging current depending on a memory cell current value and then generating a preference current on the basis of such judging current. CONSTITUTION:A multi-input current/OR circuit NCUR1 selects the maximum current among those flowing into the bit lines BL0 to BLn and generate a judging current depending on the selected value to sent it to a current comparator CCMP1. Moreover a reference current which is equal to a half of the judging current is then generated and is then sent to one input of the 2-input current/OR circuit 2CUR1. When a current is not applied to any of the lines BL0 to BLn, two outputs become '0'. NCCUR2 also selects the maximum current among those flowing into the lines BL0 to BLn and then generates a judging current depending on the selected value to send it to CCMP2. Thereby, a reference current which is equal to a half of the judging current is then generated and it is then sent to the other input of 2CUR2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device for testing a semiconductor memory device such as a static random access memory.

[0002]

2. Description of the Related Art FIGS. 7 and 8 are block configuration diagrams showing a configuration example of a conventional semiconductor memory parallel test apparatus, and FIG. 7 shows an operating state when there is no defective memory cell. FIG. 8 shows an operation state in the case where there is a defective memory cell. In the figure, MC0-M
Cn is a memory cell, BL0 to BLn, BL0B to BLn
B is a bit line, WL is a word line, CPG is a column pass gate, LD and LDB are local data lines, T
L and TLB are test lines, AMP ₁ and AMP ₂ are differential current amplifiers, EXR is an exclusive OR gate, and I ₀₁ and I ₀₂ are current sources.

This test apparatus has a pair of local parts (not shown) that take complementary or differential levels via a column pass gate CPG having a plurality of NMOS transistors whose gates are connected to a test control signal supply line TCL. It is connected to the test lines TL and TLB connected to the data line. Specifically, the bit lines BL0 to BLn are connected to the test line TL, and the bit lines BL0B to BLnB
Are connected to the test line TLB. The voltage outputs of the differential current amplifiers AMP ₁ and AMP ₂ are connected to the respective input terminals of the exclusive OR gate EXR. The inverting input of the differential current amplifier AMP ₁ is connected to the current source I ₀₁ , and the non-inverting input is connected to the test line TL. The inverting input of the differential current amplifier AMP ₂ is connected to the current source I ₀₂ , and the non-inverting input is connected to the test line TLB. The current sources I ₀₁ and I ₀₂ are _1/1 of the memory cell current I _cell .
Generate a current equal to 2.

In such a structure, if there is no defect in all the memory cells MC0 to MCn, all the memory cells MC0 to MCn along the word line WL of the memory cell array MCA under test are shown in FIG. like,
The same data, such as a logical "1", is written. Here, when the test control signal supply line TCL is set to a high level, the memory cells MC0 to MC in the entire row are
n is the test line TL via the column pass gate CPG,
Connected to TLB. Specifically, the bit line BL0
~ BLn is connected to the test line TL, and the bit line B
L0B to BLnB are connected to the test line TLB.

In this case, all the memory cells MC0 to MC
Since n correctly stores the data "1", no current flows in the test line TL, and a current equal to the product of the current drawn by a single memory cell and the number of memory cells accessed is Flow to complementary test line TLB.
Since no current flows in the test line TL, the output of the differential current amplifier AMP ₁ becomes low level “0”. On the other hand, since the above-described current flows through the test line TLB, the output of the differential current amplifier AMP ₂ becomes high level “1”. These differential current amplifiers AMP ₁ and AMP
The output of ₂ is subjected to exclusive OR in the exclusive OR gate EXR, and the test output T _OUT of high level “1” is obtained. This indicates that the test results for all the memory cells MC0 to MCn along the word line WL were good.

On the other hand, as shown in FIG. 8, the bit line BL of one or more memory cells, for example, the memory cell MC1.
The data "1" is not stored in the storage node connected to 1, but is inverted and held to the logic "0" which is the opposite data state, and the logic "1" is held in the storage node connected to the bit line BL1B. If so, current flows in both the test line TL and the complementary test line TLB. As a result, current is detected by both the differential current amplifiers AMP ₁ and AMP ₂ , and both outputs become high level. Therefore, the low-level “0” test output T _OUT is obtained as the output of the exclusive OR gate EXR. This is
Data is not correctly stored in one or more memory cells, indicating that defective memory cells are present.

[0007]

However, in the above-mentioned conventional test apparatus, the reference current I _cell / 2 is used.
Depending on the magnitude of (I _cell is a memory cell current), the differential current amplifiers AMP ₁ and AMP as current comparators
There was a problem that the input margin of ₂ could not be taken sufficiently and the judgment time was delayed. That is, the determination time depends on the process variation of the transistor that creates the actual reference current, and there is a possibility that the determination cannot be made.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device test apparatus capable of ensuring an input margin without being affected by a process variation of a transistor and realizing high-speed determination. To provide.

[0009]

In order to achieve the above object, according to the present invention, two storage nodes for storing complementary data are connected to a first bit line and a second bit line, respectively. A test device for a semiconductor memory device in which a plurality of memory cells for inducing a memory cell current in any one of the bit lines according to the above are arranged in parallel, and the test device includes two bit lines connected to each memory cell. , A first current generating circuit in which first bit lines are connected in parallel, and which generates a first determination current having a value corresponding to the maximum memory cell current value flowing in these first bit lines; Of the two bit lines connected to the memory cell, the second bit line is connected in parallel, and the value corresponding to the maximum memory cell current value flowing in these second bit lines is changed. A second current generation circuit that generates a second determination current, and a reference current having a substantially intermediate value of the determination current based on at least one of the first determination current and the second determination current. A reference current generation circuit for generating, comparing the first determination current and the second determination current with the reference current,
And a determination circuit for determining the presence / absence of a defective memory cell.

Further, in the present invention, the two storage nodes for storing complementary data are the first bit line and the second storage node.
Is a semiconductor memory device testing device in which a plurality of memory cells, each of which is connected to each of the bit lines and induces a memory cell current in one of the bit lines in accordance with stored data, is arranged in parallel. Connected 2
Among the bit lines of the present invention, the first bit lines are connected in parallel to generate a first determination current having a value corresponding to the maximum memory cell current value flowing through the first bit lines, and A first current generation circuit that generates a reference current having a substantially intermediate value of the determination current based on the determination current of 1 and a second bit line of the two bit lines connected to each memory cell are The second judgment current having a value corresponding to the maximum memory cell current value which is connected in parallel and flows in the second bit lines is generated, and substantially the middle of the judgment current is generated based on the second judgment current. A second current generating circuit that generates a reference current having a value, and a reference current having a larger value among the reference currents generated by the first current generating circuit and the second current generating circuit. A current selection circuit for selecting, said first
And the second judgment current and the reference current selected by the current selection circuit to judge the presence / absence of a defective memory cell.

Further, in the present invention, the above-mentioned determination circuit is the first
Comparing the judgment current with the reference current, and comparing the second judgment current with the reference current with the first current comparison circuit that outputs a signal of a voltage level according to the magnitude of both.
An exclusive OR which takes an exclusive OR of the output of the second current comparison circuit and the output of the second current comparison circuit, which outputs a signal of a voltage level according to the magnitude of both. OR gate.

Further, according to the present invention, at least one of the first and second current generating circuits includes an input transistor connected to the bit line, and a plurality of gate voltage generating gate voltages are generated. An input unit and a first output transistor and a second output transistor whose gates are connected to the gates of the input transistors of the respective input units are provided, and the transistor sizes of the first output transistor and the second output transistor are And an output unit set with a predetermined ratio. In addition, the first of the output section
The transistor size ratio between the output transistor and the second output transistor is set to 2: 1, the determination current is output from the first output transistor, and the reference current is output from the second output transistor.

Further, in the present invention, the current selection circuit is
A first input unit that includes an input transistor connected to the reference current output line of the first current generation circuit, generates a gate voltage according to the amount of input current, and a reference current output line of the second current generation circuit. A second input section that includes a connected input transistor and that generates a gate voltage according to the amount of input current; a first output transistor and a second input transistor whose gates are connected to the gates of the input transistors of the input sections; And an output unit having an output transistor.

Further, according to the present invention, a plurality of bit lines are wired and connected to at least one of the first current generating circuit and the second current generating circuit.

[0015]

According to the test apparatus of the present invention, for example, when the same data such as logic "0" is written in all the memory cells and no defective memory cell exists, all the memory cells are Since the data “0” is stored, the memory cell currents flow through the first bit lines connected to the storage node storing the data “0”, and are input to the first current generation circuit. It
On the other hand, no current flows through the second bit line connected to the storage node in which the data “0” and the data “1” whose logical level is inverted are stored. Therefore, the inputs of the second current generation circuit are all zero. The first current generation circuit generates a first determination current having a value corresponding to the maximum memory cell current value flowing through the first bit line, and outputs the first determination current to the reference current generation circuit and the determination circuit.
On the other hand, in the second current generation circuit, since the input current is all zero, the output also becomes zero, and this zero output is input to the reference current generation circuit and the determination circuit. In the reference current generation circuit, a reference current having a substantially intermediate value of the determination current is generated based on the determination current generated by the first current generation circuit and output to the determination circuit. In the determination circuit, the first determination current and the reference current, and the second
The zero output of the current generation circuit and the reference current are compared. In this case, the first determination current is larger than the reference current, and the zero output of the second current generation circuit is smaller than the reference current. Therefore, a test result that no defective memory cell exists is obtained.

Further, one or more memory cells are defective, data "0" is not stored in the storage node connected to a certain first bit line, and the logic "1" which is the opposite data state is inverted. If the data of the logic "0" is stored in the storage node connected to the second bit line paired with the first bit line and stored, the data "0" is stored. A memory cell current flows through the second bit line connected to the node and the first bit line connected to another memory cell.
Then, the memory cell current flowing in the first bit line is input to the first current generating circuit, and the memory cell current flowing in the second bit line is input to the second current generating circuit. On the other hand, the data bit "0" is connected to the first bit line connected to the storage node of the defective memory cell storing the data "1" whose logical level is inverted and the other memory cell. No current flows through the existing second bit line. The first current generation circuit generates a first determination current having a value corresponding to the maximum memory cell current value flowing through the first bit line, and outputs the first determination current to the reference current generation circuit and the determination circuit. Similarly, also in the second current generation circuit, the second determination current having a value corresponding to the maximum memory cell current value flowing through the second bit line is generated and output to the reference current generation circuit and the determination circuit. . In the reference current generation circuit, a reference current having a substantially intermediate value of the determination current is generated based on the first determination current by the first current generation circuit or the second determination current by the second current generation circuit. Is output to.
The determination circuit compares the first determination current with the reference current and the second determination current with the reference current. In this case, since the first determination current and the second determination current are both larger than the reference current, a test result that a defective memory cell exists is obtained.

Further, according to the test apparatus of the present invention, the first memory cell current flowing through the first bit line is input.
In the current generation circuit, the first determination current having a value corresponding to the maximum memory cell current value flowing in the first bit line is generated and output to the determination circuit, and the first determination current is generated.
A reference current having a substantially intermediate value of the determination current is generated based on the determination current and output to the current selection circuit. Similarly, in the second current generation circuit to which the memory cell current flowing in the second bit line is input, the second determination current having a value corresponding to the maximum memory cell current value flowing in the second bit line is generated. While being generated and output to the determination circuit, a reference current having a substantially intermediate value of the determination current is generated based on the second determination current and output to the current selection circuit. The current selection circuit selects a reference current having a larger value from the reference currents generated by the first current generation circuit and the second current generation circuit, and outputs the selected reference current to the determination circuit. Then, the determination circuit compares the first determination current and the second determination current with the reference current selected by the current selection circuit to determine the presence / absence of a defective memory cell.

Further, according to the present invention, in the determination circuit, the first determination current and the reference current are compared by the first current comparison circuit, and the signal of the voltage level according to the magnitude of both is generated. , Is output to one input of the exclusive OR gate. Similarly, the second current comparison circuit compares the second determination current with the reference current, generates a signal having a voltage level according to the magnitude of the two, and outputs the signal to the other input of the exclusive OR gate. It Then, in the exclusive OR gate, the exclusive OR of the output of the first current comparison circuit and the output of the second current comparison circuit is obtained, and the result determines the presence or absence of a defective memory cell.

Further, according to the present invention, the input transistors of the respective input parts of the current generating circuit are connected to the bit lines, respectively, and a gate voltage corresponding to the amount of current flowing through the bit lines is generated. The gates of the input transistors of these input sections are connected to the gates of the first output transistor and the second output transistor of the output section, and the transistor size of the first output transistor and the second output transistor is a predetermined ratio, For example, since it is set to 2: 1, the first output transistor outputs the judgment current having a value corresponding to the value of the current flowing in the bit line, and the second output transistor outputs the reference current which is half the judgment current. Current is output.

Further, according to the present invention, the input transistors of the respective input parts of the current selection circuit are respectively connected to the reference current output lines of the first and second current generation circuits, and the amount of current flowing in the reference current output line is increased. A corresponding gate voltage is generated. The gate of the input transistor of the input section is connected to the first output transistor and the second output transistor of the output section.
Connected to the gate of the first output transistor and the transistor sizes of the first output transistor and the second output transistor are set to the same size.
A reference current is output from each of the output transistor and the second output transistor.

Further, according to the test apparatus of the present invention, a plurality of bit lines are wired to each other and connected to the first current generating circuit and the second current generating circuit, so that a plurality of memory cells can be obtained. The memory cell current for each block unit including is input to the first current generation circuit and the second current generation circuit.

[0022]

1 is a block diagram showing an embodiment of a parallel test apparatus according to the present invention applied to a multi-bit test (MBT) of a semiconductor memory device. FIG. 7 and FIG. The same components as 8 are designated by the same reference numerals. That is, MCA is a memory cell array, MC0 to M
Cn is a memory cell, BL0 to BLn, BL0B to BLn
B is a bit line, NCUR ₁ and NCUR ₂ are multi-input current / OR circuits, 2CUR ₁ is a 2-input current / OR circuit, CCMP ₁ and CCMP ₂ are current comparators, EXR is an exclusive OR gate, and T _OUT is a test output. Are shown respectively.

The multi-input current / or circuit NCUR ₁ is
It has (n + 1) input sections, and these input sections are respectively connected to the bit lines BL0 to BLn. The maximum value of the currents flowing through the bit lines BL0 to BLn is selected, and the maximum current value is selected. Judgment current I with a value according to
_{A UNIT} is generated and output to the current comparator CCMP ₁ , and a reference current I _UNIT / 2 having a half value relative to the judgment current I _UNIT is generated to generate a 2-input current /
Output to one input of the OR circuit 2CUR ₁ . Further, when no current flows in any of the bit lines BL0 to BLn, both outputs become low level “0”.

Multi-input current / or circuit NCUR₂Is
It has (n + 1) input parts, and these input parts are bit
It is connected to IN BL0B to BLnB respectively, and
Maximum of the currents flowing in the input lines BL0B to BLnB
Select a value, and judge the value according to this maximum current value.
Current I_UNITTo generate the current comparator CCMP ₂
To the judgment current I_UNITRelative to half
Value reference current I_UNITGenerate // 2 and carry out 2 input call
Input / OR circuit 2CUR₁Output to the other input of. Well
In addition, current is applied to any of the bit lines BL0B to BLnB.
Is not flowing, both outputs are low level "0".
Become.

FIG. 2 shows a multi-input current / OR circuit NCU.
Configuration Example of R _1, NCUR ₂ is a circuit diagram showing an. The multi-input current / OR circuits NCUR ₁ and NCUR ₂ are composed of (n + 1) input units IN ₀ , IN ₁ ,
, (IN _n ) and an output section OUT for generating and outputting the determination current I _UNIT and the reference current I _UNIT / 2.

As shown in FIG. 2, each of the input sections IN ₀ to (IN _n ) has an NMOS transistor NT _IN1 connected between the input terminals T _IN0 to (T _INn ) and the ground, and a power supply voltage V.
_It is connected between the supply line of _CC and the gate of the NMOS transistor NT _IN1 , the gate of which is the input terminal T _IN0 ~
NMOS transistor NT _IN2 connected to (T _INn ).
It is composed by. Then, each input unit IN ₀ to (I
The gates of N _n ) NMOS transistors NT _IN1 are connected to each other, and the midpoints of these connections are connected to the output OUT.

The output section OUT has its gates connected to each other.
The judgment current I_UNITOutput end T_{OU T1}And ground
Continued NMOS transistor NT_OUT1, And Riffa
Lens current I_UNITOutput terminal T of / 2_OUT2And ground
Continued NMOS transistor NT_OUT2And NMOS
Langista NT_OUT1And NT_OUT2Connection between gates
NMOS transistor N connected between the midpoint and ground
T_OUT3 It consists of and. And the NMOS tiger
Register NT_OUT3The gate of the NMOS transistor NT
_OUT1And NT_OUT2Connected to the middle point between the gates of
The middle point of connection between these gates is the input part IN₀~
(IN_n) NMOS transistor NT_IN1The gate of
It is connected to the midpoint of the connection of the master. In addition, the output section OUT
NMOS transistors NT arranged in parallel_OUT1And NM
OS transistor NT_OUT2And transistor size (W
/ L) is set to 2: 1 and the judgment current I_UNITRelative to
Half reference current I_UNITTo output / 2
Is made. However, the drain of the output transistor
Assume that the potential at the edge is a potential that satisfies saturated region operation
To do. With this configuration, the reference current
Since an absolute value is used as
The input margin relative to the reference current for
Can be secured, and is insensitive to transistor process variations,
The influence on the fixed time can be suppressed.

A multi-input current / having such a configuration
The OR circuits NCUR ₁ and NCUR ₂ perform the maximum value operation from an analog point of view, and as described above, output the maximum value from the plurality of input currents. The input sections IN ₀ to (IN _n ) generate a gate voltage according to the amount of input current. Then, each input unit IN _0-
Since the gate end of the (IN _n ) NMOS transistor NT _IN1 is wired, the potential at the gate end rises to the potential at the gate end of the input section where the input current is maximum. Therefore, the output current is a multiple of the maximum input current (the coefficient is determined by the W / L ratio of the transistors on the input side and the output side that form the current mirror circuit in a pseudo manner).

As described above, by multiplying the output current by several times the input current, it is possible to secure a sufficient input margin for the determination, and it is possible to increase the driving capability of the next stage. For example, in the case of (n + 1) input, the judgment current I
_UNIT is _calculated by the following formula. I _UNIT = a × max (I ₀ , I ₁ , ..., I _n ) ... (1) where a is a coefficient, max () is a maximum value calculation, and I _n is an input current.

From a digital point of view, the multi-input current / OR circuits NCUR ₁ and NCUR ₂ are not affected by the variations in the input current I _n due to process variations, and can be operated by the logical operation as shown in the following equation. Performs a logical sum (OR) operation. I _UNIT = a × (I ₀ ∪I ₁ ∪ ... ∪I _n ) ... (2) where ∪ is a logical sum operator.

The multi-input current / OR circuit shown in FIG. 2 is composed of NMOS transistors.
Although the pull-in current is the input and the pull-in current is the output, the configuration of the multi-input current / OR circuit is not limited to this. In the case of the reverse pull-in current, by using the PMOS transistor. 2 can be realized by the same configuration as that shown in FIG.

2-input current / OR circuit 2CUR₁Is
Multi-input current / OR circuit NCUR ₁, NCUR₂From
Input the output reference current, and
Value, i.e._UNIT/ 2 current to generate current controller
Parator CCMP₁, CCMP₂Output to each.

This 2-input current / OR circuit 2CUR ₁
Is a multi-input current / or circuit NCUR ₁ , shown in FIG.
It has the same configuration as NCUR ₂ . The difference is that there are two inputs, IN ₀ and IN ₁ , and that the NMOS transistors NT _OUT1 and NT of the output OUT are
To use the same size _OUT2 , output the same current from the output terminals T _OUT1 and T _OUT2 , and make the input side and output side transistors the same size so that the output current is not multiplied by the input current coefficient. is there.

The current comparator CCMP ₁ compares the judgment current I _UNIT output from the multi-input current / OR circuit NCUR ₁ with the reference current I _UNIT / 2 output from the 2-input current / OR circuit 2CUR ₁ to make a judgment. current I _UNIT is the high level "1" at a voltage level greater than the reference current I _UNIT / 2, determining the current I _{UN iT}
Is smaller than the reference current I _UNIT / 2, the low level “0” is set at the voltage level, and the exclusive OR gate EXR
Output to one input.

The current comparator CCMP ₂ compares the judgment current I _UNIT output from the multi-input current / OR circuit NCUR ₂ with the reference current I _UNIT / 2 output from the 2-input current / OR circuit 2CUR ₂ and judges the result. current I _UNIT is the high level "1" at a voltage level greater than the reference current I _UNIT / 2, determining the current I _{UN iT}
Is smaller than the reference current I _UNIT / 2, the low level “0” is set at the voltage level, and the exclusive OR gate EXR
Output to the other input of.

FIG. 3 shows the current comparator CCM.
P₁, CCMP₂3 is a circuit diagram showing a configuration example of FIG. This power
The rent comparator is an NMOS transistor NT₁₁~
NT₁₄And PMOS transistor PT₁₁, PT₁₂By
It is composed of Power supply voltage V_CCBetween ground and ground
S transistor PT₁₁And NMOS transistor NT
₁₁, And PMOS transistor PT₁₂And NMOS
Transistor NT₁₂Are connected in series.
And the PMOS transistor PT ₁₁And PT₁₂Ge of
The gates are connected, and the midpoint of this gate connection is PM
OS transistor PT₁₁And NMOS transistor NT₁₁
It is connected to the midpoint of connection with. Also, the PMOS transistor
Dista PT₁₂And NMOS transistor NT₁₂Connecting with
Output end T by point₁₁Is configured. NMOS transistor
Dista NT₁₃Is the judgment current I_UNIT(I in FIG. 3_DShow with
Input end T_INDIs connected between the
S transistor NT₁₄Is the reference current I_UNIT/ 2
(I in FIG. 3_RInput terminal T_INRAnd ground
Connected between. And NMOS transistor
NT₁₁And NT₁₃The gates of the
The middle point is the NMOS transistor NT₁₃And input end T_INDWith
It is connected to the connection midpoint. Similarly, the NMOS transistor
Star NT₁₂And NT₁₄The gates of the
The middle point of connection is the NMOS transistor NT₁₄And input end T_INR
It is connected to the midpoint of connection with.

This circuit is an application of a so-called current mirror circuit. The two input currents I _D and I _R are compared, and if the input current I _D is larger than the input current I _{R, the} voltage level is high. Output "1" and input current I
_{When D} is smaller than the input current I _R , a low level “0” is output at the voltage level.

If the input is an extraction current, PM
It can be realized by replacing the OS transistor and the NMOS transistor. Further, the current comparator may use a normal current sense amplifier circuit.

Next, the operation of the above configuration will be described in order of the case where the memory cell has no defect and the case where the memory cell has a defect, with reference to FIGS. Here, a case where the same data such as logic "0" is written in all the memory cells MC0 to MCn will be described as an example.

First, the operation when there is no defect in the memory cell will be described with reference to FIG. If there is no defect in the memory cell, the data "0" is stored in all the memory cells MC0 to MCn. Therefore, the bit line BL connected to the storage node storing the data "0".
The memory cell current I _cell flows through 0 to BLn,
It is input to the multi-input current / OR circuit NCUR ₁ . On the other hand, no current flows through the bit lines BL0B to BLnB connected to the storage node storing the data "1" having the logic level inverted from that of the data "0". Therefore, the inputs of the multi-input current / OR circuit NCUR ₂ are all zero.

In the multi-input current / OR circuit NCUR ₁ , the maximum value of the memory cell currents I _cell flowing through the bit lines BL0 to BLn is selected, and the judgment current I _UNIT corresponding to the maximum memory cell current value is selected. Generated and output to the current comparator CCMP ₁ ,
A reference current I _UNIT / 2 having a half value relative to the determination current I _UNIT is generated, and the 2-input current / OR circuit 2C is generated.
It is output to one input of UR ₁ . On the other hand, in the multi-input current / or circuit NCUR ₂ , since the inputs are all zero, the zero output is the current comparator CCMP 2.
Output to ₂ and 2-input current / OR circuit 2
It is output to the other input of CUR ₁ .

[0042] In multiple-input current / OR circuit NCUR ₁ reference current output from the I _UNIT / 2 and multi-input current / OR circuit 2 inputs the current / OR circuit receiving the zero output of NCUR ₂ 2CUR _1, of the two inputs largest ones, i.e. is selected reference current I _UNIT / 2, the current comparator CCMP ₁ and CCMP
Output to ₂ respectively.

Current comparator CCMP₁Then many
Input current / OR circuit NCUR₁Judgment output from
Current I_UNITAnd 2 input current / or circuit 2CUR₁From
Output reference current I_UNITCompared with / 2
Be done. In this case, the judgment current I _UNITIs the reference power
Flow I_UNITSince it is larger than / 2, the high level "1"
A signal is obtained and one input of the exclusive OR gate EXR
Is output to. Current comparator CCMP₂Then
Multi-input current / OR circuit NCUR₂Zero output and 2 inputs
Current / OR circuit 2CUR₁Referred output from
Current I_UNITA comparison with / 2 is made. In this case,
Reference current I_UNIT/ 2 is larger, so Lore
The signal of bell "0" is obtained, and the exclusive OR gate EXR
Is output to the other input of.

In the exclusive OR gate EXR, the exclusive OR of the outputs of the current comparators CCMP ₁ and CCMP ₂ is taken, and the test output T showing the value of "1" is output.
_OUT is obtained. This means that all memory cells MC0
~ Indicates that the test results for MCn were good.

Next, the operation when the memory cell has a defect will be described with reference to FIG. As shown in FIG.
One or more memory cells, for example, memory cell MC1 is defective and data "0" is not stored in the storage node connected to bit line BL1, and the data is inverted and held to logic "1" which is the opposite data state. When the data of logic "0" is stored in the storage node connected to the line BL1B, the bit lines BL0, BL1B, BL2 connected to the storage node in which the data "0" is stored.
A memory cell current I _cell flows through BLn. The memory cell current I _cell flowing through the bit lines BL0, BL2 to BLn is the multi-input current / OR circuit NCU.
The memory cell current I _{cell that} is input to R ₁ and flows to the bit line BL1B is the multi-input current / OR circuit NCUR ₂
Entered in. On the other hand, the bit lines BL0B, BL1, BL2B connected to the storage node storing the data "1" whose logical level is inverted from that of the data "0"
No current flows to BLnB.

Therefore, the multi-input current / OR circuit N
The memory cell current I _cell is input to the n input parts IN ₀ , IN _{2 to} IN _n of the CUR ₁ , and the input of one input part IN ₁ becomes zero input. The inputs of the n input sections IN ₀ , IN _{2 to} IN _n of the multi-input current / OR circuit NCUR ₂ are zero inputs, and the memory cell current I _cell is input to one input section IN ₁ .

Multi-input current / OR circuit NCUR₁so
Is the maximum current flowing through the bit lines BL0 to BLn.
A large value is selected and the value is judged according to the maximum current value.
Current I _UNITIs generated and the current comparator CCMP
₁Is output to the judgment current I_UNITRelatively half
Reference current I in minutes_UNIT/ 2 is generated and 2
Force current / OR circuit 2CUR₁Output on one input
Be done. Similarly, a multi-input current / or circuit NCUR₂To
In addition, the current flowing through the bit lines BL0B to BLnB is
The maximum value of the current is selected and the maximum current value is selected.
Judgment current I_UNITIs generated and current comparator
CCMP₂Is output to the judgment current I_UNITWhen
Reference current I of half the value_UNIT/ 2 is generated
2 input current / or circuit 2CUR₂The other input
Output to force.

Multi-input current / or circuit NCUR₁And
And multi-input current / OR circuit NCUR₂Output from
Reference current I_UNIT2 input current that received / 2
OR circuit 2CUR₁Then the largest of the two inputs,
That is, the reference current I _UNIT/ 2 is selected and the
Rent comparator CCMP₁And CCMP₂To it
It is output respectively.

Current comparator CCMP₁Then many
Input current / OR circuit NCUR₁Judgment output from
Current I_UNITAnd 2 input current / or circuit 2CUR₁From
Output reference current I_UNITCompared with / 2
Be done. In this case, the judgment current I _UNITIs the reference power
Flow I_UNITSince it is larger than / 2, the high level "1"
A signal is obtained and one input of the exclusive OR gate EXR
Is output to. Similarly, the current comparator CCMP
₂Also, multi-input current / or circuit NCUR₂Or
Judgment current I output from_UNITAnd 2 input current / or times
Road 2 CUR₁Reference current I output from_UNIT/
A comparison with 2 is made. Also in this case, the determination current I_UNITof
The reference current I_UNITSince it is larger than / 2,
High-level "1" signal is obtained, exclusive OR gate
It is output to the other input of EXR.

In the exclusive OR gate EXR, the exclusive OR of the outputs of the current comparators CCMP ₁ and CCMP ₂ is taken, and the test output T indicating the value of "0" is obtained.
_OUT is obtained. This indicates that the data is not correctly stored in one or more memory cells and there are defective memory cells.

As described above, according to this embodiment,
A multi-input current / OR circuit is used to determine whether or not a memory cell current is flowing, and a reference current and a reference current that is half the size of the reference current are generated to determine the reference current and the reference current. By comparing with the current, the memory cell MC0 of the memory cell array MCA
Since it is determined whether or not ~ MCn is defective, variations in individual memory cell currents can be absorbed,
It is possible to secure an input margin between the determination current and the reference current for determination. Therefore, the magnitude of the reference current does not affect the determination time. In addition, because it is a left-right symmetrical configuration, write all "1",
It can support both test patterns of all "0" writing. Further, the output current of the current / OR circuit can be multiplied by the coefficient of the memory cell current by adjusting W / L of the output side transistor, and high-speed determination can be performed with a sufficient input margin.

In this embodiment, the multi-input current / OR circuit NCUR ₁ or NCUR _{2 is used} as shown in FIG.
As shown in, the multi-input current / OR circuit NCUR can be realized in a multi-stage configuration using a plurality of multi-input current / OR circuits NCUR in consideration of positive / negative directions (pull-in / pull-out) of the input current and the output current. In this case, it is preferable that the input / output of the same-direction current is an even number stage and the input / output of the reverse-direction current is an odd number stage. In the case of the example of FIG. 6, since the same-direction current is input / output, each of the plurality of multi-input current / or circuits NCUR arranged in parallel in the upper stage has, for example, BL0 to BLn or BL0B to. A plurality of bit lines of (n + 1) bit lines of BLnB are connected in parallel, and the outputs of these multi-input current / OR circuits NCUR are connected to the inputs of the multi-input current / OR circuit NCUR in the lower stage. It is configured. With such a configuration, expansion of multiple inputs becomes easy and high-speed operation can be realized.

In this embodiment, all the bit lines BL0 to BLn and BL0B to BLnB are connected in parallel to the multi-input current / OR circuits NCUR ₁ and NCUR _2, but the present invention is not limited to this. It is not something that will be done. For example, a memory cell is divided into a plurality of blocks, and a plurality of bit lines BL0, BL in each block are divided.
It is also possible to configure a plurality of wired connections of 0B to 0B to be connected to the multi-input current / OR circuits NCUR ₁ and NCUR ₂ , respectively. in this case,
In addition to the effects described above, a multi-input current / or circuit NC
Since the number of input units of UR ₁ and NCUR ₂ can be reduced, the number of transistors can be reduced, and the circuit area can be reduced, and the device can be downsized.

[0054]

As described above, according to the present invention,
Since the reference current is relatively 1/2 of the output current, the input margin can be secured without being affected by the process variation of the transistor. Also, the output current of the current generation circuit is W of the output side transistor.
By adjusting / L, the coefficient can be multiplied by the memory cell current,
High-speed judgment is possible with sufficient input margin. further,
By connecting a plurality of bit lines to each current generating circuit by wired connection, the number of input units of the current generating circuit can be reduced. As a result, there is an advantage that the number of input transistors can be reduced, the circuit area can be reduced, and the device can be downsized.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a parallel test apparatus according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a multi-input current / OR circuit according to the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a current comparator circuit according to the present invention.

FIG. 4 is a diagram for explaining an operation when there is no defect in a memory cell in the test apparatus of FIG.

5 is a diagram for explaining an operation when the test device of FIG. 1 has a defect in a memory cell.

FIG. 6 is a circuit diagram showing another configuration example of the multi-input current / OR circuit according to the present invention.

FIG. 7 is a diagram for explaining an operation when a memory cell has no defect in the conventional test apparatus.

FIG. 8 is a diagram for explaining an operation when a memory cell has a defect in a conventional test apparatus.

[Explanation of symbols]

MCA ... memory cell array MC0-MCn ... memory cells BL0~BLn, BL0B~BLnB ... bitline NCUR _1, NCUR ₂ ... multiple input current / OR circuit 2CUR ₁ ... 2 Input Current / OR circuit CCMP _1, CCMP ₂ ... Current Comparator EXR … Exclusive OR gate T _OUT … Test output

Claims (7)

[Claims] 1. Two storage nodes for storing complementary data are respectively connected to a first bit line and a second bit line, and a memory cell current is induced in either bit line according to the stored data. A testing device for a semiconductor memory device in which a plurality of memory cells are arranged in parallel, wherein a first bit line of two bit lines connected to each memory cell is connected in parallel. A first current generation circuit that generates a first determination current having a value corresponding to the maximum memory cell current value flowing through one bit line; and a second current line that is connected to each of the memory cells. A second current generating circuit in which two bit lines are connected in parallel, and which generates a second determination current having a value corresponding to the maximum memory cell current value flowing in these second bit lines; A reference current generation circuit that generates a reference current having a substantially intermediate value of the determination current based on at least one of the first determination current and the second determination current; A semiconductor memory device testing device comprising: a judgment circuit for comparing the judgment current of No. 2 with the reference current to judge the presence or absence of a defective memory cell. 2. Two storage nodes for storing complementary data are respectively connected to a first bit line and a second bit line, and a memory cell current is induced in either bit line according to the stored data. A testing device for a semiconductor memory device in which a plurality of memory cells are arranged in parallel, wherein a first bit line of two bit lines connected to each memory cell is connected in parallel. The first determination current having a value corresponding to the maximum memory cell current value flowing through the first bit line is generated, and the first determination current is generated.
A first current generation circuit that generates a reference current having a substantially intermediate value of the determination current based on the determination current of 1. and a second bit line of the two bit lines connected to the memory cells Are connected to each other and generate a second determination current having a value corresponding to the maximum memory cell current value flowing through these second bit lines, and
Of the reference currents generated by the first current generation circuit and the second current generation circuit, the second current generation circuit generating a reference current having a substantially intermediate value of the determination current based on A current selection circuit that selects a reference current having a large value is compared with the first determination current and the second determination current and the reference current selected by the current selection circuit to determine the presence or absence of a defective memory cell. Device for testing a semiconductor memory device having a determination circuit for performing the operation. 3. The determination circuit compares a first determination current and a reference current, and outputs a signal of a voltage level according to the magnitude of both, a second determination current and a first current comparison circuit. A second current comparison circuit that compares the reference current and outputs a signal of a voltage level according to the magnitude of both;
3. The semiconductor memory device testing apparatus according to claim 1, further comprising an exclusive OR gate that takes an exclusive OR of the output of the first current comparison circuit and the output of the second current comparison circuit. . 4. A plurality of input units, wherein at least one of the first and second current generation circuits includes an input transistor connected to a bit line, and generates a gate voltage according to the amount of input current. A first output transistor and a second output transistor, the gates of which are connected to the gates of the input transistors of each of the input units, and the first output transistor and the second output transistor;
4. An apparatus for testing a semiconductor memory device according to claim 2, further comprising an output section in which the transistor size of the output transistor is set to a predetermined ratio. 5. The transistor size ratio of the first output transistor and the second output transistor of the output section is set to 2: 1 and the first output transistor outputs a determination current, and the second output transistor The semiconductor memory device testing device according to claim 4, wherein the reference current is output from the device. 6. The first selection section, wherein the current selection circuit includes an input transistor connected to a reference current output line of the first current generation circuit, the first input section generating a gate voltage according to an input current amount, and The second input section, which includes an input transistor connected to the reference current output line of the second current generation circuit, generates a gate voltage according to the amount of input current, and the gate is connected to the gate of the input transistor of each of the input sections 6. The semiconductor memory device testing device according to claim 2, 3, 4, or 5, further comprising: an output unit including the first output transistor and the second output transistor that are configured to operate. 7. A plurality of bit lines are wired and connected to at least one of the first current generation circuit and the second current generation circuit by wired connection. 3. A semiconductor memory device testing device according to 3, 4, 5 or 6.