JPH07210995A - Optical disk device - Google Patents

Abstract

PURPOSE:To accurately read data even when resolution is degraded due to increasing integration density or variation of recording conditions, or even when variation of transient and an envelope exist. CONSTITUTION:A clamp circuit 104 clamps a peak of a reproduced signal RDS, an amplitude comparing section 108 compares amplitude of a clamp signal outputted from the clamp circuit 104 with the reference voltage, an AGC control section 102 generates a control voltage signal Vcnt in accordance with a difference of amplitude and controls gain of a gain variable amplifier 101. A gate signal generating section 105 compares a clamp signal CLP outputted from the clamp circuit 104 with the prescribed signal and generates a gate signal GTS, a data pulse outputting section 107 outputs a data pulse DT when a differential zero cross signal ZCS of a reproduced signal is generated at the time of generation of the gate signal GTS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk device, and more particularly to an optical disk device capable of reading data from an optical disk accurately even when the resolution is lowered due to a higher density or a change in recording conditions.

[0002]

2. Description of the Related Art In recent years, an optical disk device has been developed and put into practical use as an external storage device of a computer. The optical disc device records the data on the medium by narrowing down the semiconductor laser as a minute spot up to about the wavelength, and has a great feature of large-capacity recording and interchangeability. Especially, 5 inches standardized by ISO standard,
The 3.5-inch optical disk device is expected to be widely used from high-performance workstations to individual user levels.

Of the optical disks, a writable magneto-optical disk is one in which an amorphous magnetic thin film such as TbFeCo is deposited on a substrate, and the coercive force required for reversing the magnetization of the magnetic film becomes smaller as the temperature rises. The property (coercive force at compensation point temperature is zero) is used. That is, by applying a weak magnetic field in a state of weakened coercivity by increasing the temperature of the disk medium to the vicinity of 200 ⁰ C by controlling the magnetization direction is irradiated with a laser beam, recording is for erasing. Therefore, FIG.
As shown in (a), in the state where the magnetization direction on the magnetic film 5 is downward, an upward magnetic field is applied by the write coil 6, and the laser beam is applied to the portion where the magnetization direction is to be reversed as shown in FIG. 11 (b). When LB is irradiated through the objective lens OL, the magnetization direction of the portion is reversed and becomes upward, and information can be recorded. In addition, when reading information, FIG.
When the magnetic film 5 is irradiated with the laser beam LB having a plane of polarization in the y-axis direction as shown in (c) and (d), the plane of polarization is θ _{K in the} clockwise direction at the portion where the magnetization direction is downward due to the magnetic Kerr effect.
The rotated reflected light LB0 is obtained, and the reflected light LB1 whose polarization plane is rotated in the counterclockwise direction by θ _K is obtained in the portion where the magnetization direction is upward.
Is obtained. Therefore, the magnetization direction, in other words, information can be read by detecting the polarization state of the reflected light. In such a magneto-optical disk, a full RAM disk in which the entire surface is writable and a writable area (R
There are a partial ROM disk having an AM area) and a read-only area (ROM area), and a full ROM disk having the entire ROM area.

Structure of Magneto-Optical Disk FIG. 12 is an explanatory view of the structure of, for example, a 3.5-inch magneto-optical disk. FIG. 12 (a) is a schematic plan view and FIG. 12 (b) is a partial sectional view. is there. The magneto-optical disk 11 has concentric or spiral tracks, and all tracks are fan-shaped and divided into 25 sectors. Each sector ST is, for example, 72
It consists of 5 bytes, with the address field A at the beginning.
F (ID area) is provided, and after that data field D
F (MO area: magneto-optical area) is provided. Address information including a sector mark, a track address, a sector address, and a preamble for reproducing a synchronization signal is recorded in the address field AF, and a VFO pattern for clock extraction and a sync byte SYNC and data for phase alignment are recorded in a data field DF. It stores data such as DATA. The magneto-optical disk 11 has a transparent plastic layer (substrate) as shown in FIG. 12 (b).
The recording layer (recording film) MGF is deposited on the PLS, and the protective layer PRF is further formed on the recording layer (recording film) MGF. The address field AF (ID area) is pre-formatted by pits PT (unevenness) by stamping. ing.

System Configuration Utilizing Magneto-Optical Disk Medium FIG. 13 is a configuration diagram of a system utilizing a magneto-optical disk medium, 11 is a magneto-optical disk, 21 is a magneto-optical disk drive, and 31 is a host system (computer. Main body), 41 is a data input unit (operation unit), which is a keyboard
It has a driver 41a and a mouse 41b. Reference numeral 51 is a display device such as a CRT or liquid crystal display, and 61 is a printer. A hard disk device and a floppy disk device are appropriately provided.

FIG. 14 is an electrical configuration diagram of the system.
The same parts as those in FIG. 13 are designated by the same reference numerals. Reference numeral 21 is a magneto-optical disk drive, 22 is a hard disk drive, 31 is a host system, 71a-71b are I / O controllers, and 72 is a SCSI (Small Computer System).
Interface: SCSI) bus. SCSI is an interface that connects the computer to an external storage device.
Standards are defined by NSI (American National Standard Institute). The SCSI bus is composed of, for example, a data bus consisting of 8 bits and parity bits and 9 control buses. Up to 8 SCSI devices can be used on this SCSI bus.
Devices (host computer, disk drive controller, etc.) can be connected, and each device has an identification number of 0 to 7 called an ID (Identifier). In the figure, I / O controllers 71a-71b
D0 to ID1 are assigned to the host system 31 and I
D7 is assigned. I / O controller 71a
Although one optical disk drive 21 and one hard disk drive 22 are connected to 71b, two or more drives can be connected.

In the host system 31, 31a is a central processing unit, 31b is a memory, 31c is a DMA controller, 31d is a host adapter, and 71c to 71d are I.
Each part is connected to the host bus 31e by the / O controller. 23 is a floppy disk drive,
It is connected to the I / O controller 71c. Reference numeral 41 is an operation unit, 51 is a display device, and 61 is a printer, which are connected to the I / O controller 71d.

The host system 31 and the I / O controllers 71a-71b are connected by a SCSI interface, and the I / O controllers 71a-71b and each drive 2 are connected.
For example, an ESDI interface (Enhanced
Small Device Interface). In this system, the magneto-optical disk drive 21 and the hard disk drive 22 are separated from the host bus 31e, a SCSI bus 72 is provided separately from the host bus, and I / O controllers 71a to 71b for each drive are connected to the SCSI bus, The I / O controllers 71a and 71b control the drives 21 and 22 to reduce the load on the host bus.

Basic structure of magneto-optical head FIG. 15 is used in a magneto-optical disk drive device 21.
It is a basic block diagram of a magneto-optical head. 21₁Is semiconductor
The, 21₂Is a collimating lens, 21₃Is a perfect circle correction pre
Zum, 21_FourTransmits the light from the semiconductor laser and
A beam sp that reflects the light reflected from the disk to the signal detection side.
21 liters_FiveIs a guide that directs light to a disc (not shown)
Shooting mirror, 21₆Is a two-dimensional actuator, not shown
The objective lens and the tracking and
Tracking coil and focus for fine adjustment in the direction of the curve
A coil that applies an external magnetic field when writing data and data.
Equipped with an ear coil. 21₇Data reflected light
Reflection mirror 21 leading to the detection side₈Is a half-wave plate
The polarization plane of the incident light is rotated by 45 degrees,
Function to make the amount of transmitted light and reflected light in the plitter 1: 1
have. 21 ₉Is a converging lens, 21_TenIs a polarized bee
Musplitter, 21₁₁Is a P-wave component detector, 21₁₂Is S
It is a wave component detector.

The principle of reading the MO area information The polarization beam splitter 21 ₁₀ is used for the light (P
It has a property of transmitting light (wave component) and reflecting light (S-wave component) perpendicular to the incident surface. Therefore, the polarization state of the incident light can be detected as a change in the transmitted light amount and the reflected light amount. That is, the polarization plane of the return light is clockwise or counterclockwise as shown in FIG. 16 (a) due to the magnetic Kerr effect according to the magnetization direction (information bits "0", "1") in the reading area of the MO region. rotated theta _K to be rotated 45 degrees the polarization plane by 1/2-wave plate 21 _8. Therefore, as shown in FIG. 16B, the P-wave component (transmitted light) and the S-wave component (reflected light) output from the polarization beam splitter 21 ₁₀ have information "
When 1 ", the P wave component becomes larger than the S wave component, and the information is"
When it is 0 ", the P wave component is smaller than the S wave component. Therefore, the P wave component detector 21 ₁₁ causes the signal R shown in FIG.
DS1 is output, and the S wave component detector 21 ₁₂
A signal RDS2 shown in (c) (the polarity of which is reversed from that of the signal RDS1) is output, and when these signals RDS1 and RDS2 are input to the differential amplifier, a reproduction signal RDS from which noise of the same phase is removed is obtained.

[0011] - a magneto-optical disc drive unit 17 is a diagram showing the construction of a magneto-optical disc drive unit 21, 21a in the magneto-optical head shown in FIG. 15, 21 ₁ semiconductor laser - The -, 21 ₁₁ P-wave component detectors, 21 _{1 2} S-wave component detector, OL is an objective lens. Reference numeral 21b is a control unit having a microcomputer configuration, which controls the entire magneto-optical disk drive device, for example, positioning control of the magneto-optical head and data reading / recording control in accordance with instructions from the system main body 31 (see FIG. 13). Reference numeral 21c is a head access control circuit for positioning the magneto-optical head 21a at a predetermined position according to an instruction from the control unit, 21d is a data recording circuit for recording data on the magneto-optical disk, and 21e is data for recording data on the magneto-optical disk. This is a data reproducing circuit for reproducing.

When the control unit 21b receives a data read command from the host device (system main unit 31), the head access control circuit 21c positions the magneto-optical head 21a at the commanded address, and the magneto-optical head is used for recording. Read the signal. The magneto-optical head 21a inputs the read signal to the data reproducing circuit 21e, and the reproducing circuit reproduces the data from the signal input from the detector to control the controller 2
1b, and the control unit inputs the data to the host device. When the controller 21b receives a data write command from the host device, the head access control circuit 21c positions the magneto-optical head 21a at the commanded address and turns on / off the semiconductor laser 21 ₁ based on the write data. The data is written on the magneto-optical disk.
In addition, 5 inches, which is standardized by ISO, 3.
In the 5-inch recording format, the recording data is encoded by the (2,7) encoding method, and the encoded data is written in the MO area. The (2,7) encoding method is an encoding method in which the number of "0" s between the bit "1" and the bit "1" after encoding changes from 2 to 7. Have the following relationships.

[0013]

Data Reproducing Circuit FIG. 18 is an explanatory diagram of a data reproducing system. The data to be recorded is in a format suitable for the recording characteristics of the optical disc (the above-mentioned R
LL2,7 code). In actual recording, a recording pit (black circle) on the medium is made to correspond to bit "1" of encoded data. The size of the recording pit is about the wavelength of the semiconductor laser, and in the case of the current 3.5-inch ISO standard medium, the bit cell interval of encoded data is the shortest at the inner circumference and is about 0.75 μm.
m.

On the other hand, data reproduction is performed by detecting a change in light amount when the recording pit is scanned by the semiconductor laser. As shown in FIG. 18, the waveform of the actual reproduction signal RDS has a peak when the recording pit exists. Therefore, the data can be reproduced by detecting the peak point of the reproduction signal RDS. Specifically, the reproduced signal is differentiated, and it is detected that the level of the differentiated signal DFS exceeds a certain value, and the gate signal GTS is created.
Further, the differential signal DFS is binarized at a zero level to create a zero-cross signal ZCS that zero-crosses at the peak point of the reproduction signal. Then, when the gate signal GTS is at the high level and the zero-cross signal ZCS falls, the reproduction data signal DT having a predetermined time width is output.

FIG. 19 is a block diagram of the data reproducing circuit 21e. 21e-1 is an amplifier for amplifying the reproduction signal RDS, 21e-2
Is a low-pass filter, 21e-3 is a differentiating circuit for differentiating the reproduction signal, 21e-4 is a comparator which inputs the differential signal DFS and outputs a gate signal GTS by comparing with a set value, 21e-5 is a differential signal A comparator 21e-6 that binarizes DFS at zero level and outputs a zero-cross signal ZCS, 21e-6 is a high-level gate signal GTS, and a zero-cross signal ZCS.
When the data has fallen, the reproduction data signal DT having a predetermined time width W
21e-7 is a delay unit for setting a predetermined time width W, 21e-8 is a PLL circuit for extracting the clock included in the reproduced data, and 21e-9 is for outputting the data in synchronization with the extracted clock. It is a data separator. P
In the LL circuit 21e-8, PHS is reproduction data DT and V
CPMP, which outputs a phase difference signal of FO output, CPMP
Is a charge pump that outputs a voltage according to the phase difference, LP
FL is a low-pass loop filter, and VFO is a voltage frequency oscillator that outputs a signal having a frequency corresponding to the filter output voltage. The reproduction data DT is due to the fluctuation of the rotation of the spindle motor that rotates the disk, the eccentricity of the center of the disk from the center of rotation,
The frequency is different from when recording. Therefore, P
The LL circuit 21e-8 extracts a clock synchronized with the reproduced data from the reproduced data. Based on the extracted clock
The data "1" and "0" are discriminated by the data separator 21e-9.

[0017]

By the way, in the conventional reproducing method, the resolution (see FIG. 18) is changed by the fluctuation of the medium sensitivity or the recording power or by increasing the density.
(Corresponding to V2 / V1) decreases and the gate signal is no longer created. For example, in a 3.5-inch, 128-Mbyte optical disc, the minimum bit interval is 1.5 μm, and V2 / V1 is 5
It is 0% to 60%. When V2 / V1 is about 50% to 60%, it is possible to obtain substantially the same differential signal amplitude regardless of whether the peaks of the reproduction signal RDS are isolated or dense, and the gate signal GTS is correct. Data can be generated and reproduced. However, when the storage capacity becomes, for example, the next-generation ISO standard of 230 Mbytes, the recording density is improved by about 20% compared to the conventional one, so that the reproduction signal RDS becomes as shown in FIG. 20 (a), and the resolution V2 / V1 is descend. As a result, the differential signal DFS becomes as shown in FIG.
Even if the differential signal DFS is sliced at a predetermined level Vs to generate the gate signal GTS, the gate signal GTS cannot be accurately generated in a portion where peaks are dense, and an undetected peak portion occurs. Data reading error occurs (see FIG. 20 (c)).

Therefore, it is conceivable that an equalization circuit is provided, for example, in the latter stage of the low-pass filter 21e-2, and the high-frequency component is emphasized by the circuit to increase the reproduction signal amplitude V2 at the peak dense portion to improve the resolution. . However, if the high-frequency component is emphasized by the equalization circuit, the undershoot US as shown in FIG.
Occurs. Therefore, when the reproduced signal is differentiated,
As shown in (b), the portion corresponding to the undershoot portion becomes higher than the slice level Vs, and the erroneous gate pulse G
TS occurs (see (c)), which causes a problem that an erroneous reproduction data pulse is generated. Further, in the method of improving the resolution by waveform equalization, there is a problem that the high frequency noise is emphasized at the same time, and therefore the S / N ratio which is the signal quality is lowered, and the zero cross signal occurs at the wrong point. .

The meaning of the reproduced signal RDS is
It is a peak point. Therefore, the slice level Vs for detecting the peak level of the reproduction signal by some means and creating the gate signal GTS with the peak level as a reference
Just ask. However, since there is a transient at the start of a sector, which is a data management area of the optical disc, and an envelope fluctuation of a reproduction signal due to a medium reflection fluctuation, a mechanism for detecting a peak envelope is required. Of these, the state of transient occurrence is shown in FIG. This transient occurs because the reproduction system is AC-coupled and the DC component is lost. The band of this AC coupling is the reproduction signal RD.
S is set sufficiently low (1/100 to 1/50 of the signal frequency) to prevent distortion due to sag or the like. From the above, at the fixed slice level, a considerable amount of data is lost from the start of data.

FIG. 23 shows an example of a structure for determining a slice level using a peak hold circuit. Reference numeral 81 is a peak hold circuit composed of a diode and a capacitor, and 82 is a slice level decision circuit. The capacitor C stores the peak value of the reproduction signal RDS. That is,
When the reproduction signal RDS becomes higher than the terminal voltage of the capacitor, the diode turns on to charge the capacitor, and the reproduction signal RD
When S becomes below the peak value, the diode cuts off and the charge is discharged through the resistor R (time constant τ = CR).
As a result, the terminal voltage of the capacitor C changes following the peak value and is input to the slice level determination circuit 82 via the buffer amplifier BA. Slice level determination circuit 8
2 determines the slice level Vs for creating the gate signal based on the peak value of the reproduction signal RDS. By the way, in order for the peak hold circuit 81 to accurately hold the peak value of the reproduction signal RDS, the buffer amplifier needs to have a high speed, and specifically, a follow-up characteristic on the order of ns is required. In addition, the accuracy of the buffer amplifier becomes a problem in order to reduce the leakage of the capacitor C that holds the peak value. Furthermore, the function of canceling the drop in the forward voltage of the diode is also necessary. There are many disadvantages to the application of. Further, a more serious problem is that the peak hold using a diode or a transistor can obtain the peak voltage, but it does not have a function of correcting the waveform itself, and the influence of temperature fluctuation cannot be ignored.

From the above, even if the resolution is lowered due to the high density or the change of the recording condition, the data can be accurately read from the optical disc, and moreover,
There is a demand for an optical disc reproducing apparatus capable of preventing the adverse effects of transients at the start of data and envelope fluctuations due to AC coupling of the reproducing system. Figure 24
Is a block diagram of an information reproducing apparatus proposed in Japanese Patent Laid-Open No. 3-102677, and FIG. 25 is a waveform diagram of each part for explaining the operation. 9
Reference numeral 1 is an amplifier for amplifying the reproduction signal RDS, 92 is a low-pass filter, 93 is a differentiation signal for the reproduction signal, and a differential zero cross detection circuit for generating a zero cross signal ZCS when the differential signal DS crosses the zero level, 94 is a reproduction A clamp circuit that clamps the lower limit level of the signal RDS, 95 is a gate signal generation circuit that outputs a binarized signal obtained by slicing the output signal of the clamp circuit Vout at a predetermined level Ls as a gate signal GTS, and 96 is a gate signal GTS Is inverted when the zero-cross signal ZCS falls during the high level period,
Further, it is a reproduction digital signal generation unit which generates the reproduction digital signal DT so as to be inverted again when the gate signal GTS becomes low level after the generation of the zero-cross signal.

In the clamp circuit 94, the clamp control voltage Vset is supplied to the base terminal and the emitter terminal output is used as the output of the clamp circuit 94.
a, a resistor 94b connected between the emitter and ground,
A capacitor 94c for cutting a direct current component is provided. When the input signal Vin is larger than Vcc, the transistor 94a
Turns off, and the input signal Vin is output as Vout as it is. On the other hand, when the input signal Vin is smaller than Vcc, the transistor 94a is turned on and the bias voltage Vcc is output. That is, the clamp circuit 94 sets the lower limit level to Vcc.
Output the signal clamped at.

According to this clamp circuit, the lower limit level of the reproduction signal RDS corresponding to the modulation data "0" (non-mark) can be clamped to a constant voltage as shown in FIG. That is, even when the resolution of the reproduction signal RDS is small, it is possible to equivalently increase the resolution by passing through the clamp circuit 94, and the peak point of the reproduction signal (differential signal zero cross point) can be surely obtained. The gate signal GTS having a high level can be generated in the range including), and the reproduced digital signal generator 96 can correctly reproduce the data.

However, the transistor (including diode) clamp has a drawback in that the transition time for turning on / off the transistor is large due to the influence of the base accumulated charge. Therefore, as shown in FIG. 26, a time lag of several ns to several ms occurs between the reproduction signal RDS and the clamp output signal Vout, and the gate signal GTS also has the time lag Td. The time lag of the gate signal GTS causes a problem in high density (high speed transfer). Further, since the proposed clamp circuit clamps the lower limit level, when the noise NS is added to the reproduction signal RDS due to the defect of the disk as shown in FIG. 27, the peak value of the noise becomes the slice level. There is a problem in that erroneous reading occurs when the value becomes Ls or more.

From the above, the object of the present invention is to achieve AGC even if the reproduced signal amplitude fluctuates due to the environment of use (especially environmental temperature).
It is an object of the present invention to provide an optical disk device in which the clamp signal amplitude can be automatically set to the optimum amplitude by the operation to increase the device margin. Another object of the present invention is to cope with high-speed transfer by clamping the peak value of the reproduction signal at high speed by the Schottky barrier diode clamp circuit, and to be resistant to defects (not affected by defects).
An optical disk device is provided. Still another object of the present invention is to optimize the signal amplitude after clamping by AGC control even if the characteristic (forward drop voltage) of the Schottky diode corresponding to the slice level varies depending on the ambient temperature or the junction surface temperature. An object of the present invention is to provide an optical disc device that can increase the device margin.

[0026]

FIG. 1 is a diagram for explaining the principle of the present invention. Reference numeral 101 denotes a variable gain amplifier (AGC) for amplifying a reproduction signal RDS read from an optical disk, 10
2 is an AGC control unit, 104 is a clamp circuit that clamps the peak value of the amplifier output signal, 105 is a gate signal generation unit that compares the clamp voltage output from the clamp circuit with a predetermined signal level, and generates a gate signal GTS, 106
Is a differentiation / zero-cross signal generator that differentiates the reproduction signal and outputs a zero-cross signal ZCS when the differential signal crosses the zero level, 107 is a data pulse output section, and 108 is a signal amplitude output from the clamp circuit. It is an amplitude comparison unit that detects a difference from the reference voltage level.

[0027]

The amplitude comparison unit 108 compares the clamp signal amplitude output from the clamp circuit 104 with the reference voltage level, and outputs the amplitude difference. The AGC control unit 102 generates a control voltage signal Vcnt for controlling the gain of the variable gain amplifier 101 based on the amplitude difference. Gate signal generator 105
Is a clamp signal CL output from the clamp circuit 104
P is compared with a predetermined signal level to generate a gate signal GTS, and the data pulse output unit 107 outputs a data pulse when the zero-cross signal ZCS is generated while the gate signal GTS is being generated. In this way, the clamp circuit 104
By clamping the peak of the reproduction signal RDS to a predetermined potential in step 1, even if the peak value of the reproduction signal fluctuates, the peak value is always clamped to a constant potential, and the gate signal GTS can be generated based on the constant peak value. it can. As a result, even if the peak value fluctuates, the gate signal can be generated accurately, and even if the resolution decreases due to higher density or changes in recording conditions, or when there is transient or envelope fluctuation. However, the data can be read accurately. Furthermore, since the peak value is clamped to a constant potential, the slice level for creating the gate signal can be set to a high level, and the noise caused by a defect or the like can be prevented from being erroneously read and the influence of the defect can be eliminated. .

Further, the clamp circuit 104 is constructed by using a Schottky diode, and the reference voltage level in the amplitude comparing section 108 is 1.1 to 1.7 times the forward voltage of the Schottky diode. By doing so, even if the reproduction signal amplitude fluctuates due to variations in medium characteristics and between drives, the amplitude of the clamp signal can be automatically set to be optimum by the AGC operation, and the device margin can be increased. Further, even if the characteristics of the diode (forward drop voltage) change due to the ambient temperature or the junction surface temperature, the amplitude of the clamp signal can be optimized by AGC control, and the device margin can be increased.

[0029]

【Example】

(a) Overall Configuration FIG. 2 is a block diagram of an embodiment of a data reproducing circuit of the present invention in an optical disk drive device. Reference numeral 101 denotes a variable gain differential amplifier that amplifies a reproduction signal read from the optical disc, and has reproduction signals RDS1 and RD having different polarities.
S2 is input and two signals with different polarities are output. The reproduction signals RDS1 and RDS2 are the P wave component detector 21 ₁₁ and the S wave component detector 21 _{12 of FIG.}
These signals correspond to the signals RDS1 and RDS2 (see FIG. 16 (c)) output from the above. 102 is a reproduction signal RDS
1, an AGC control unit for setting the amplitude of RDS2 to a predetermined value, 10
Reference numeral 3 denotes a waveform processing unit to which two signals having different polarities are input from the variable gain amplifier 101, and has a low pass filter and an equalizer. The low-pass filter and the equalizer are inserted to remove noise in the high frequency range, appropriately emphasize the high frequency side of the reproduced signal, prevent deterioration of resolution, and remove peak shift.

Reference numeral 104 denotes a clamp circuit for clamping the peak values of the two reproduction signals RD1 'and RDS2' output from the waveform processing section. For the reproduction signal RDS1 ', the + side peak value is clamped to reproduce the reproduction signal RDS2. For ', the negative peak (bottom) is clamped to a constant value. A gate signal G 105 compares the voltage levels of the clamp signals CLP and CLP ′ output from the clamp circuit.
Gate signal generator (comparator) that generates TS, 1
06 is a reproduction signal RDS1 ′ output from the waveform processing unit,
A differential / zero-cross signal generator that differentiates RDS2 'and outputs a zero-cross signal ZCS when the difference signal of the differential signal crosses the zero level, and 107 is the peak point of the reproduction signal RDS1 (zero-cross point of the differential signal). A data pulse output unit that outputs a data pulse at 108. An amplitude comparison unit 108 that compares the amplitude of the clamp signal CLP output from the clamp circuit with the reference voltage level Vr to AGC the amplitude difference and input the result to the control unit 102. Is a reference voltage generator that generates a reference voltage Vr.

(B) Configuration of Each Section FIG. 3 is a configuration diagram of each section behind the waveform processing section, and FIG. 4 is a waveform diagram of each section. In FIG. 4, ID is an address field (ID area) provided at the head of the sector, D
F is a data field DF provided after the ID area
(MO area), and V for clock extraction is included in the MO area.
The FO, the sync byte SYNC for phase matching, and the user data DATA are written.

Clamp circuit Clamp circuit 104 reproduces reproduced signals RDS1 'and RDS.
Two capacitors C ₀ for cutting off the DC component of 2 ′, two current limiting resistors R ₁ connected in series to the capacitors C ₀ , bias resistors R ₀ and R ₂ , and the vice resistor in order. Directionally biased Schottky diode D ₁
The anode side of the Schottky diode is connected to the + terminal of the comparator CMP that constitutes the gate signal generator 105, and the cathode side is connected to the-terminal of the comparator CMP. Schottky diode D ₁
In principle, there is no influence of accumulated charge, so there is no signal delay compared to a clamp circuit using a transistor or other diode. Further, since the Schottky diode can take a constant value without depending on the applied voltage, it can always be clamped to a constant potential.

Now, when there is no input signal, the potential of the non-inverting terminal (+) of the comparator CMP is the potential (V) obtained by adding the forward voltage V _F of the Schottky diode D ₁ to the potential of the inverting terminal (-). _T = I ₁ · R ₂ + V _F ). In this state, when the signal RDS1 'having the transient shown in FIG. 4 is input, the rising potential at the start of the transient is held at a constant voltage because the Schottky diode D ₁ is turned on. Clamped to V _T as indicated by the clamp signal CLP of. Here, the current limiting resistor R ₁ connected in series with the capacitor C ₀ acts to reduce the load on the driver that drives the clamp system. That is, the rising potential point during transient start is to work the diode clamp, there is a possibility that flows a large current is not a current limiting resistor R _1, the current is limited resistor current by R ₁ is limited, the driver of the load It will be reduced. However, the current limiting resistor R ₁
If you make too large, the clamp circuit will not work, so
Several tens of Ω is sufficient.

Next, when the input signal RDS1 'drops, a current path is formed in the direction of Vcc → R ₀ → R ₁ → C ₀ → input signal terminal, and the non-inverting terminal voltage (clamp signal CLP) of the comparator CMP. Is the input signal R as shown in FIG.
It changes following DS1 '. At this time, the capacitor C
_Although the electric charge is charged to ₀ , it is discharged through the resistor R ₁ and the Schottky diode D ₁ when the input signal RDS1 'rises. From the above, the peak value of the transient and envelope variation due to reflectivity variation is absorbed by the reproduction signal at the time of start of data is clamped to V _T, the input signal R in the following V _T
The signal waveform follows DS1 '. The above is the input signal R
In the case of paying attention to DS1 ', the input signal RDS2'
Focusing on, as indicated by a dotted line in FIG. 4, the clamp signal CLP 'is clamped bottom within V _R, in the above V _R input signal RDS2' becomes a signal waveform following the.

In the clamp circuit 104, the time constant τ (= C ₀ · R) determined by the capacitor C ₀ and the diode bias resistors R ₀ and R ₂ is the longest pattern of the input signal (from the peak point to the next peak point). Pattern with the longest time)
There is a need above. This is because the bottom level cannot be maintained below that. For example, ISO
According to the standard, the (2,7) RLL encoding system is adopted as a recording format of 5 inches and 3.5 inches. According to this (2,7) RLL encoding method, the number of “0” s between encoded bits “1” and “1” varies from 2 to 7, and the longest pattern has a bit interval of T. Then it becomes 8T. Therefore, the time constant τ (= C ₀ · R) needs to be larger than 8T. Further, the upper limit of the time constant is determined by the VFO pattern period provided for extracting the clock component from the data at the start of the data. This is within the VFO period in which the peak clamp operates when a transient opposite to that shown in FIG. 4 (a transient in the opposite direction may occur depending on the influence of the immediately preceding ID crosstalk etc.) at the start of data. This is because the transient needs to be established.

Gate Signal Generating Unit The gate signal generating unit 105 is composed of a comparator CMP. The clamp signal CLP is input to the non-inverting terminal (+) and the clamp signal CLP ′ is input to the inverting terminal (−) of the comparator CMP. When the terminal potential is higher than the inverting terminal potential, the high level gate signal GTS is output. Differentiating / zero-crossing signal generating section Differentiating / zero-crossing signal generating section 106 reproduces the reproduction signal RDS.
1 ', RDS2' respectively differentiated signal DFS,
The differential circuit 106a having a CR structure for outputting DFS 'and a comparator 106c for outputting a high-level zero-cross signal ZCS when the difference signal between the differential signals DFS and DFS' are below the zero level.

Data pulse output section The data pulse output section 107 outputs a data pulse (reproduction data) DT when the zero cross signal ZCS is generated while the gate signal GTS is generated, that is, at the peak point of the reproduction signal RDS1. It is supposed to do. 107a is a flip-flop, and 107b is a delay unit that sets a predetermined delay time. When the zero cross signal ZCS is generated while the gate signal GTS is at the high level, the flip-flop 107a is set and reset after the delay time has elapsed. As a result, the data pulse DT having a width corresponding to the delay time is output. In addition, the data pulse output unit 107 is configured by an AND gate, and the gate signal GT is formed by the AND gate.
It is also possible to output the data pulse DT by calculating the logical relationship between S and the zero-cross signal ZCS.

Configuration of Feedback System FIG. 5 is a configuration diagram of an amplitude feedback system for feeding back the clamp signal amplitude to the variable gain amplifier 101, FIG.
FIG. 7 is a waveform diagram for explaining the operation of the amplitude feedback system. 1
08 is a clamp signal CLP output from the clamp circuit
Of the control voltage signal Vcnt corresponding to the amplitude difference, the amplitude comparison unit outputting an amplitude difference between the amplitude of the reference voltage Vr and the reference voltage level Vr.
, 109 is a reference voltage generator, and n (= 1.1-1..1) of the forward voltage drop V _F of the Schottky barrier diode D ₁ forming the clamp circuit 104.
7) Generate a doubled reference voltage Vr. In addition, n = 1.1-
The reason for setting 1.7 will be described later. In the amplitude comparison unit 108, 108a is an amplitude comparator that compares the amplitude of the reference voltage Vr with the clamp signal CLP input from the clamp circuit, and 108b is a constant current source Iin, Iout and a switch SWi.
A charge pump composed of n and SWout turns on and off the switches SWin and SWout based on the output of the amplitude comparator 108a to suck / exhale. In the AGC control unit 102, 102a is a low-pass filter that converts the current output of the charge pump into a voltage, and 102b is a buffer amplifier that outputs the output of the low-pass filter as a control voltage signal Vcnt.

The reference voltage generator 109 is a clamp circuit 10.
Provided in the vicinity of 4, the Schottky barrier diode D ₁ of the Schottky barrier diode D ₁ and the same characteristics of the clamp circuit 104 ', a bias resistor R ₀ of the diode to forward bias Schottky diodes D _1' forward voltage of It has a multiplication unit (for example, an amplifier) MLT that multiplies the drop V _F by n (= 1.1 to 1.7). The forward voltage drop V _F of the Schottky barrier diode D ₁ ′ is determined by the multiplication unit ML.
N (= 1.1 to 1.7) is multiplied by T, and the comparator 10
It is input to the-terminal of 8a. Meanwhile, the clamp signal CLP
Is also input to the + terminal of the comparator 108a.
Comparator 108a compares the amplitude of both input, when the clamp signal amplitude of Vr (= n · V _F) below, and outputs a low level of the drive signal CD, in the case of more than n · V _F is high The level drive signal CD is output. Drive signal C
When D is at low level, the switch SWout is turned on, and the charge stored in the capacitor of the lowpass filter 102a is discharged. Conversely, when the drive signal CD is at high level, the switch SWin is turned on and lowpass. The capacitor of the filter 102a is charged with electric charge. As a result,
As shown in FIG. 6, the low-pass filter 102a causes the control voltage signal V to increase or decrease according to the amplitude of the clamp signal CLP.
cnt is output.

The case where only the capacitor is used as the low-pass filter 102a (transfer function F (s) = 1 / sC) is shown, but a secondary filter (transfer function F (s) = R + 1 /) in which a resistor and a capacitor are connected in series is shown. sC). Two
The operation principle of the second filter is exactly the same as the case of only the capacitor, and which one is selected depends on the system design. In the amplitude comparison unit 108, the charging / discharging currents Iin and Iout increase at the time of pulling in the AGC at the start of data, and then decrease, so that the AGC attack time can be reduced. As a result, the response time of the variable gain amplifier 101 is reduced by the control of the AGC control unit 102, which will be described later, and the adverse effect due to the amplitude variation based on the data pattern is eliminated.

Variable Gain Amplifier FIG. 7 is a block diagram of the variable gain amplifier. The configuration of FIG. 7 is called a Gilbert cell and is already used in many circuits. Variable-gain amplifier 101, a differential amplifier stage 101a, a bias portion 101b for supplying a current to each transistor of the differential amplifier stage with transistors Q _5, Q ₆ of the reproduction signal RDS1, RDS2 of different polarities are input together, Constant current unit 101c, output buffer stage 101
d, a transistor switch section 101e. The transistor switch unit 101e controls two gains of the differential amplifier stage 101a according to the magnitude of the control voltage signal Vcnt output from the AGC control unit 102 and the preset reference voltage Vref.
It has (Q ₁ , Q ₂ ) and SW ₂ (Q ₃ , Q ₄ ). Transistor switch unit 101e compares the control voltage signal Vcnt and the reference voltage Vref, so that the reference voltage and the control voltage is equal to controlling the conductivity of the transistor Q ₁ to Q _4, the gain as a result, the differential amplifier 101a Control and play signal R
The amplitudes of DS1 and RDS2 are set to optimum values.

The operation principle will be briefly described. The differential input signals (reproduction signals) RDS1 and RDS2 are the differential amplifier 101.
It is input to the transistors Q ₅ and Q ₆ of a. The load of each transistor, the transistors Q _1, Q ₂ and Q _3, Q transistor switch SW1 is constituted by _4, S
W2 is connected, and the control voltage signal Vcnt is applied to one base of each transistor and the reference voltage signal Vr is applied to the other base.
ef is being applied. Reference voltage Vref> control voltage signal Vc
In the case of nt, the transistors Q ₂ and Q ₄ are turned on, and the transistors Q ₁ and Q ₃ are turned off. Therefore, the reproduction signal RDS
1, RDS2 transistors Q _2, Q ₄ of appearing in the load resistor R _A, the input signal RDS1 of the next waveform processing unit 103 via the transistor Q _7, Q ₈ buffer stage 101d ",
RDS2 a ". In this case is the maximum gain, the voltage gain is R _A / R _B.

Next, reference voltage Vref <control voltage signal Vcnt
In the case of, the transistor Q₁, Q₃Turns on and transition
Star Q₂, Q_FourTurn off. Therefore, the reproduction signal RDS
1, RDS2 is load resistance R_AGay no longer appearing in
Is zero. In practice, the feedback loop
Control is performed so that reference voltage Vref≈control voltage signal Vcnt
As a result, the signal amplitude of the clamp signal CLP is reduced.
Toki Barrier Diode D ₁Forward voltage drop V_FN (=
1.1 to 1.7) times.

(C) Margin In the embodiment of FIG. 3, a slice for creating the gate signal GTS
The level is Schottky diode D₁Forward voltage drop
Lower V_FForward voltage drop V _FAnd Kura
The amplitude of the pump signal is used to generate the gate signal GTS.
It has a lot to do with Jin. Generally Schottky Dio
Forward voltage drop V_FHas a strong temperature dependency
The higher the temperature of_FHave a tendency to decline. Light de
Disk environment temperature (5⁰C ~ 45⁰C) during operation
Considering heat etc., the temperature change of the joint surface is 0⁰C-80⁰C
Above, due to this temperature change, V_FIs twice (1 /
2) Change near. Therefore, to improve the margin
To V_FThe playback signal, that is, the clamp signal
It is necessary to control the amplitude of the signal. On the other hand,
Depending on the emissivity, medium performance and reproduction efficiency, the reproduction signal amplitude
It fluctuates up to nearly twice. Therefore, the reproduced signal amplitude fluctuates.
Then V_FIt is necessary to control the amplitude so that
There is a point.

FIG. 8 shows an example of measuring the margin with respect to the clamp signal amplitude in the configuration of the embodiment shown in FIGS. This diagram is the signal amplitude ratio (signal amplitude / V _F) representing a margin deterioration during creation gate signal. As a result, the clamp signal CLP, which is input to the gate signal generator 105,
It can be seen that the signal amplitude of CLP 'has the best characteristics when it is 1.1 to 1.7 with respect to V _F. In order to clear this target amplitude, the diode forward voltage drop V _F of 1.1 to
The value multiplied by 1.7 is generated as the reference voltage Vr. Then, the difference between the reference voltage Vr and the signal amplitude of the clamp signal CLP is detected by the amplitude comparison unit 108, and the control voltage signal Vcnt corresponding to the difference is output from the AGC control unit 102 to determine the gain of the variable gain amplifier 101. Control. As a result, feedback control is performed so that the signal amplitude of the clamp signal CLP becomes n (= 1.1 to 1.7) times the forward voltage drop V _F of the Schottky barrier diode D ₁ .

(D) Modification In the above, the variable gain amplifier, the waveform processing section, the clamp circuit, and the reproducing signals RDS1 and RDS2 having different polarities are used.
Although the gate signal generator performs a predetermined process, the data pulse DT may be generated by using the reproduction signal RDS obtained by calculating the difference between the reproduction signals RDS1 and RDS2. In such a case, the clamp circuit and thereafter are configured as shown in FIG. Clamp circuit 104
3 requires only one signal as compared with FIG. 3, the clamp signal CLP is input to the non-inverting terminal (+) of the gate signal generator 105, and Vb + V _F / 2 (V _F is a diode) to the inverting terminal (−). Forward voltage drop) is input.

Ideally, the comparison potential of the clamp signal CLP in the gate signal generator 105 is set near the reproduction signal amplitude in the longest pattern, that is, in the vicinity of 50% of the maximum amplitude. Because the S / N ratio of the reproduced signal deteriorates,
This is because the so-called level margin for preventing an erroneous gate signal from opening becomes maximum at the center of the reproduced signal. Therefore, Vb is applied to the inverting terminal of the comparator CMP.
+ V _F / 2 is input. FIG. 10 is a signal waveform diagram of each part in FIG. Although the reproduction of the information in the MO area has been described above, the present invention can also be applied to the reproduction of the information in the preformat section (ID area).
Further, although the case where the Schottky diode is used has been described above, other high speed diodes can be used. Furthermore, although the present invention has been described above with reference to the embodiments, the present invention can be modified in various ways according to the gist of the present invention described in the claims, and the present invention does not exclude these.

[0048]

As described above, according to the present invention, the clamp circuit clamps the peak of the reproduced signal to a predetermined potential and generates the gate signal based on the constant peak value. Therefore, even if the peak value fluctuates. The gate signal can be generated accurately, and the data can be read accurately even if the resolution is lowered due to the high density or changes in the recording conditions, or when there is a transient or envelope fluctuation. You can Further, according to the present invention, since the peak value is clamped to the constant potential, the slice level for creating the gate signal can be set to a high level, and the noise generated due to a defect or the like is not erroneously read, and the defect The effect can be eliminated.

Further, according to the present invention, the clamp circuit is constructed by using the Schottky diode, and the reference voltage level in the amplitude comparison section is 1.1 times to 1.7 times the forward voltage of the Schottky diode. Since the AGC control is performed so that even if the reproduction signal amplitude fluctuates due to variations in medium characteristics or between drives, the AGC operation causes
It is possible to increase the device margin by automatically setting the amplitude of the clamp signal to be optimum. Even if the diode characteristics (forward drop voltage) change due to the ambient temperature or the junction surface temperature, the amplitude of the clamp signal can be optimized by AGC control.
The device margin can be increased. Furthermore, since the Schottky diode is not affected by the accumulated charge, the peak value of the reproduction signal can be clamped at high speed without delay, and high density and high speed transfer can be supported.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of a data reproducing circuit of the present invention.

FIG. 3 is a configuration diagram of each unit behind the waveform processing unit.

FIG. 4 is a waveform diagram of each part.

FIG. 5 is a configuration diagram of an amplitude feedback system.

FIG. 6 is a waveform diagram for explaining the operation of the amplitude feedback system.

FIG. 7 is a configuration diagram of a variable gain amplifier.

FIG. 8 is an explanatory diagram of a margin measurement result with respect to a signal amplitude.

FIG. 9 is a configuration diagram of each part showing a modified example of the present invention.

FIG. 10 is a waveform diagram for explaining the operation of the modified example.

FIG. 11 is an explanatory diagram of writing / reading of a magneto-optical disk.

FIG. 12 is a configuration diagram of a magneto-optical disk medium.

FIG. 13 is a system configuration diagram.

FIG. 14 is an electrical configuration diagram of the system.

FIG. 15 is a basic configuration diagram of a magneto-optical head.

FIG. 16 is an explanatory diagram of the principle of reading MO area information.

FIG. 17 is a configuration diagram of a magneto-optical disk drive device.

FIG. 18 is an explanatory diagram of a data reproduction method.

FIG. 19 is a configuration diagram of a data reproducing circuit.

FIG. 20 is a diagram illustrating a conventional problem.

FIG. 21 is a diagram illustrating another conventional problem.

FIG. 22 is an explanatory diagram of a transient.

FIG. 23 is a configuration diagram using a peak hold circuit.

FIG. 24 is a block diagram of a conventional information reproducing apparatus.

FIG. 25 is a waveform chart of each part.

FIG. 26 is a diagram illustrating a problem of a clamp circuit using a transistor and a diode.

FIG. 27 is a diagram illustrating a problem of the lower limit level clamp.

[Explanation of symbols]

 101..Amplifier with variable gain 102..AGC control unit 104..Clamp circuit 105..Gate signal generation unit 106..Differential / zero cross signal generation unit 107..Data pulse output unit 108..Amplitude comparison unit

Claims (7)

[Claims] 1. A zero-cross signal generator for differentiating a reproduction signal read from an optical disc and outputting a zero-cross signal when the differential signal crosses a zero level, and a gate for generating a gate signal using the reproduction signal. Equipped with a signal generator,
In an optical disk device that outputs a data pulse when a zero-cross signal is generated while a gate signal is being generated, a variable gain amplifier that amplifies a reproduction signal and a clamp circuit that clamps the peak value of the output signal of the amplifier , A reference voltage generation unit that generates a reference voltage level, an amplitude comparison unit that compares the amplitude of the clamp signal output from the clamp circuit with the reference voltage level, and the gain of the variable gain amplifier is controlled based on the comparison result. An optical disc device comprising an AGC control unit for controlling an output signal amplitude of a clamp circuit, wherein the gate signal generation unit compares a clamp signal output from the clamp circuit with a predetermined signal level to generate a gate signal. 2. The clamp circuit includes a capacitor for cutting a direct current component of a reproduction signal, a bias resistor, and a diode forward biased through the bias resistor and having an anode side connected to the capacitor. The optical disk device according to claim 1, wherein the optical disk device is a diode clamp mechanism. 3. The optical disk device according to claim 2, wherein the diode is a Schottky barrier diode. 4. The optical disk device according to claim 2, wherein the reference voltage level is determined in proportion to the forward voltage of the diode. 5. The optical disk device according to claim 4, wherein the reference voltage level is 1.1 to 1.7 times the forward voltage of the diode. 6. The amplitude comparison unit includes a comparator that compares a reference voltage with the amplitude of a clamp signal, and a charge pump that performs suction / discharge according to the output of the comparator.
2. The optical disk device according to claim 1, wherein the AGC control unit has a low-pass filter that converts the current output of the charge pump into a voltage, and uses the low-pass filter output as a control voltage signal. 7. A time constant due to a DC cut capacitor and a bias resistor of the diode clamp mechanism is equal to or longer than a longest bit cell interval (longest interval from a peak point to a next peak point), and The optical disk device according to claim 2, wherein the VFO pattern length at the beginning is equal to or less than the VFO pattern length.