JP3007522B2 - Playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus , and more particularly to a reproducing apparatus capable of reading data accurately from a storage medium such as an optical disk even when the resolution is reduced due to a high density or a change in recording conditions. About.

[0002]

2. Description of the Related Art In recent years, an optical disk device has been developed as an external storage device of a computer and is being put to practical use. An optical disc device is a device in which a semiconductor laser is narrowed down to a minute spot as small as a wavelength and data is recorded on a medium, and has a great feature of large capacity recording and interchangeability. In particular, 5 inches standardized by the ISO standard,
A 3.5-inch optical disk device is expected to be widely used from a sophisticated workstation to an individual user level.

[0003] Of the optical disks, writable magneto-optical disks have a substrate on which an amorphous magnetic thin film such as TbFeCo is deposited, and the coercive force required for reversing the magnetization of the magnetic film becomes smaller as the temperature rises. Utilizing the property (the coercive force is zero at the compensation point temperature). That is, by applying a weak magnetic field in a state of weakened coercivity by increasing the temperature of the disk medium to the vicinity of 200 ⁰ C by controlling the magnetization direction is irradiated with a laser beam, recording is for erasing. Therefore, FIG.
As shown in FIG. 11A, in a state where the magnetization direction on the magnetic film 5 is downward, an upward magnetic field is applied by the write coil 6, and as shown in FIG. When the LB is irradiated through the objective lens OL, the magnetization direction of the portion is reversed to be upward, and information can be recorded. In reading information, FIG.
As shown in (c) and (d), when the magnetic film 5 is irradiated with the laser beam LB having a polarization plane in the y-axis direction, the polarization plane becomes θ _K clockwise in a portion where the magnetization direction is downward due to the magnetic Kerr effect.
Rotated reflected light LB0 is obtained, and reflected light LB1 whose polarization plane is rotated by θ _K counterclockwise in the portion where the magnetization direction is upward.
Is obtained. Therefore, by detecting the polarization state of the reflected light, the direction of magnetization, in other words, information can be read. Such a magneto-optical disk has a full RAM disk on which the entire surface can be written and a writable area (R
There is a partial ROM disk having an AM area) and a read-only area (ROM area), and a full ROM disk having an entire ROM area.

Structure of magneto-optical disk FIG. 12 is an explanatory view of the structure of a magneto-optical disk of, for example, 3.5 inches, FIG. 12 (a) is a schematic plan view, and FIG. 12 (b) is a partial sectional view. is there. The magneto-optical disk 11 has concentric or spiral tracks, and all tracks are divided into 25 sectors in a fan shape. Each sector ST is, for example, 72
It consists of 5 bytes, and the address field A
F (ID area) is provided, and the data field D
F (MO region: magneto-optical region) is provided. In the address field AF, address information including a sector mark, a track address, a sector address, and a preamble for reproducing a synchronizing signal is recorded. In the data field DF, a VFO pattern for clock extraction, a sync byte SYNC for phase matching, and data are stored. DATA and the like are stored. The magneto-optical disk 11 has a transparent plastic layer (substrate) as shown in FIG.
A recording layer (recording film) MGF is deposited on the PLS, and a protective layer PRF is further formed thereon. The address field AF (ID area) is pre-formatted by pits PT (irregularities) by stamping in advance. ing.

FIG. 13 is a configuration diagram of a system using a magneto-optical disk medium, 11 is a magneto-optical disk, 21 is a magneto-optical disk drive, and 31 is a host system (computer). Data input unit (operation unit), and a keyboard 41
And a mouse 41b. 51 is a display device such as a CRT or a liquid crystal display, and 61 is a printer. In addition, a hard disk device and a floppy disk device are provided as appropriate.

FIG. 14 is an electrical configuration diagram of the system.
The same parts as those in FIG. 13 are denoted by the same reference numerals. 21 is a magneto-optical disk drive, 22 is a hard disk drive, 31 is a host system, 71a to 71b are I / O controllers, and 72 is a SCSI (Small Computer System).
Interface: SCSI) bus. SCSI is an interface that connects the computer body and external storage device.
Standards are defined by NSI (American National Standard Institute). The SCSI bus includes, for example, a data bus composed of 8 bits and parity bits and 9 control buses. This SCSI bus has up to eight SCSI
Devices (host computer, disk drive controller, etc.) can be connected, and each device has an identification number from 0 to 7 called an ID (Identifier). In the figure, I / O controllers 71a-71b
D0 to ID1 are assigned, and the host system 31
D7 is assigned. I / O controller 71a
One optical disk drive 21 and one hard disk drive 22 are connected to ７１71b, but two or more drives can be connected.

In the host system 31, 31a is a central processing unit, 31b is a memory, 31c is a DMA controller, 31d is a host adapter, and 71c to 71d are I / Os.
Each section of the / O controller is connected to a host bus 31e. 23 is a floppy disk drive,
It is connected to the I / O controller 71c. 41 is an operation unit, 51 is a display device, and 61 is a printer, each of which is connected to the I / O controller 71d.

The host system 31 and the I / O controllers 71a-71b are connected by a SCSI interface, and the I / O controllers 71a-71b and each drive 2
For example, an ESDI interface (Enhanced
(Small Device Interface). In this system, the magneto-optical disk drive 21 and the hard disk drive 22 are separated from the host bus 31e, a SCSI bus 72 is provided separately from the host bus, and I / O controllers 71a to 71b for each drive are connected to the SCSI bus. The drives 21 and 22 are controlled by the / O controllers 71a and 71b to reduce the load on the host bus.

Basic Structure of Magneto-Optical Head FIG. 15 is used for a magneto-optical disk drive 21.
FIG. 3 is a basic configuration diagram of a magneto-optical head. 21₁Is a semiconductor laser
The, 21_TwoIs a collimating lens, 21_ThreeIs a perfect circle correction pre
Zum, 21_FourTransmits light from a semiconductor laser, and
Beam spatter that reflects the light reflected from the disc to the signal detection side.
Liter, 21_FiveGuides the light to the disc (not shown)
Shooting mirror, 21₆Is a two-dimensional actuator, not shown.
However, tracking and forcing the objective lens and the objective lens
Tracking coil and focus for fine adjustment in the focus direction
A coil for applying an external magnetic field when writing data
It has an ias coil and the like. 21₇Is the reflected light
Reflecting mirror for guiding to the detection side, 21₈Is a half-wave plate
The polarization plane of the incident light is rotated by 45 degrees, and the polarization beam
A function to make the amount of transmitted light and reflected light at the splitter 1: 1
have. 21 ₉Is a convergent lens, 21_TenIs polarized bee
Mussplitter, 21₁₁Is a P-wave component detector, 21₁₂Is S
It is a wave component detector.

[0010] · MO area information reading principle polarization beam splitter 21 ₁₀ parallel to the plane of incidence of light (P
(Wave component) and reflects light (S-wave component) perpendicular to the incident surface. Therefore, the polarization state of the incident light can be detected as a change in the amount of transmitted light and the amount of reflected light. That is, depending on the magnetization direction (“0” or “1” of the information bit) in the reading section in the MO area, the polarization plane of the return light is changed clockwise or counterclockwise as shown in FIG. rotated theta _K to be rotated 45 degrees the polarization plane by 1/2-wave plate 21 _8. Therefore, as shown in FIG. 16 (b), P-wave component output from the polarization beam splitter 21 ₁₀ (transmitted light) and the S-wave component (reflected light) information is "
At 1 ", the P-wave component becomes larger than the S-wave component and the information becomes"
When 0 ", the P-wave component is smaller than the S-wave component. Therefore, the signal indicating a P-wave component detector 21 ₁₁ in FIG. 16 (c) R
DS1 is output from the S-wave component detector 21 _{12 as} shown in FIG.
A signal RDS2 (inverted in polarity with respect to the signal RDS1) shown in (c) is output, and when these signals RDS1 and RDS2 are input to a differential amplifier, a reproduced signal RDS from which in-phase noise has been removed is obtained.

[0011] - a magneto-optical disc drive unit 17 is a diagram showing the construction of a magneto-optical disc drive unit 21, 21a in the magneto-optical head shown in FIG. 15, 21 ₁ semiconductor laser - The -, 21 ₁₁ P-wave component detectors, 21 _{1 2} S-wave component detector, OL is an objective lens. Reference numeral 21b denotes a control unit having a microcomputer configuration, which controls the entire magneto-optical disk drive, for example, controls the positioning of the magneto-optical head, and controls the reading and recording of data, in accordance with instructions from the system main unit 31 (see FIG. 13). 21c is a head access control circuit for positioning the magneto-optical head 21a at a predetermined position in accordance with an instruction from the control unit, 21d is a data recording circuit for recording data on the magneto-optical disk, and 21e is a data recording circuit for recording data recorded on the magneto-optical disk. This is a data reproducing circuit for reproducing.

When receiving a data read command from the host device (system main unit 31), the control unit 21b positions the magneto-optical head 21a at the commanded address by the head access control circuit 21c, and makes the magneto-optical head record. Read the signal. The magneto-optical head 21a inputs the read signal to a data reproducing circuit 21e, which reproduces data from the signal input from the detector and controls
1b, the control unit inputs the data to the host device. The control section 21b receives the data write command from the upper apparatus, by turning on and off the semiconductor laser 21 ₁ based on the write data with attain positions the head access control circuit commanded address magneto-optical head 21a by 21c The data is written to a magneto-optical disk.
It should be noted that 5 inches, 3.
In the 5-inch recording format, recording data is encoded by the (2, 7) encoding method, and the encoded data is written in the MO area. The (2,7) coding method is a coding method in which the number of “0” s between bits “1” and “1” after coding changes from 2 to 7, and the input data and the coded data Has the relationship shown below.

[0013]

Data Reproducing Circuit FIG. 18 is an explanatory diagram of a data reproducing method. The data to be recorded is in a format suitable for the recording characteristics of the optical disc (the R
LL2,7 code). In actual recording, the recording bit (black circle) on the medium is made to correspond to the bit “1” of the encoded data. The size of the recording pit is about the size of the wavelength of the semiconductor laser. In the case of the current 3.5-inch ISO standard medium, the bit cell interval of the encoded data is the shortest on the inner circumference, and is about 0.75 μm.
m.

On the other hand, data reproduction is performed by detecting a change in light amount when a recording pit is scanned by a semiconductor laser. As shown in FIG. 18, the waveform of the actual reproduced signal RDS has a peak at the time when the recording pit exists. Therefore, data can be reproduced by detecting the peak point of the reproduction signal RDS. Specifically, the reproduction signal is differentiated, and it is detected that the level of the differentiated signal DFS has exceeded a certain value, and the gate signal GTS is created.
Further, the differential signal DFS is binarized at a zero level to create a zero-cross signal ZCS that crosses zero at a peak point of the reproduction signal. Then, when the gate signal GTS is at a high level and the zero cross signal ZCS falls, a reproduced data signal DT having a predetermined time width is output.

FIG. 19 is a block diagram of the data reproducing circuit 21e. 21e-1 is an amplifier for amplifying the reproduction signal RDS, 21e-2
Is a low-pass filter, 21e-3 is a differentiating circuit for differentiating the reproduced signal, 21e-4 is a comparator which receives a differential signal DFS and outputs a gate signal GTS by comparing with a set value, and 21e-5 is a differential signal. A comparator for binarizing the DFS at the zero level and outputting the zero cross signal ZCS. The comparator 21e-6 has a zero cross signal ZCS when the gate signal GTS is at the high level.
Falls, the reproduction data signal DT having a predetermined time width W
21e-7 is a delay unit for setting a predetermined time width W, 21e-8 is a PLL circuit for extracting a clock included in the reproduced data, and 21e-9 is a data output in synchronization with the extracted clock. This is the data separator to be used. P
In the LL circuit 21e-8, the PHS outputs the reproduced data DT and V
Phase comparator for outputting phase difference signal of FO output, CPMP
Is a charge pump that outputs a voltage corresponding to the phase difference, LP
FL is a low-pass loop filter, and VFO is a voltage frequency oscillator that outputs a signal having a frequency corresponding to the filter output voltage. The reproduced data DT is generated due to rotation fluctuation of a spindle motor for rotating the disk, eccentricity in which the center of the disk is shifted from the center of rotation, and the like.
The frequency is different from that at the time of recording. Therefore, P
The LL circuit 21e-8 extracts a clock synchronized with the reproduced data from the reproduced data. Based on the extracted clock,
Data "1" and "0" are determined by the data separator 21e-9.

[0017]

By the way, in the conventional reproducing method, the resolution (FIG. 18) is changed by fluctuation of the medium sensitivity or recording power or by increasing the density.
(Corresponding to V2 / V1), and the gate signal is not generated. For example, in a 3.5-inch, 128 Mbyte optical disk, the minimum bit interval is 1.5 μm, and V2 / V1 is 5
0% to 60%. When V2 / V1 is about 50% to 60%, substantially the same differential signal amplitude can be obtained regardless of whether the peak of the reproduction signal RDS is isolated or dense, and the gate signal GTS can be correctly obtained. The generated data can be reproduced. However, when the storage capacity is, for example, 230 Mbytes, which is the next-generation ISO standard, the recording density is improved by about 20% as compared with the conventional one, so that the reproduced signal RDS becomes as shown in FIG. descend. As a result, the differential signal DFS becomes as shown in FIG.
Even if the differential signal DFS is sliced at a predetermined level Vs to generate the gate signal GTS, the gate signal GTS cannot be accurately generated in a portion where the peaks are dense, and an undetected peak portion is generated. As a result, a data reading error occurs (see FIG. 20C).

Therefore, it is conceivable that an equalizing circuit is provided, for example, at the subsequent stage of the low-pass filter 21e-2, and that the high-frequency component is emphasized by the circuit to increase the reproduced signal amplitude V2 in the peak dense portion to improve the resolution. . However, if the high-frequency component is emphasized by the equalizing circuit, the undershoot USR as shown in FIG.
Occurs. Therefore, when the reproduction signal is differentiated, FIG.
As shown in (b), the portion corresponding to the undershoot portion becomes higher than the slice level Vs, and the wrong gate pulse G
A TS occurs (see (c)), which causes a problem that an erroneous reproduced data pulse is generated. In the method of improving the resolution by waveform equalization, high-frequency noise is also emphasized at the same time, so that the S / N ratio, which is the signal quality, is reduced, and a zero cross signal may occur at an erroneous point. .

The meaning of the reproduced signal RDS is as follows.
It is a peak point. Accordingly, the peak level of the reproduced signal is detected by some means, and the slice level Vs for generating the gate signal GTS based on the peak level is determined.
Should be obtained. However, since there is a transient at the start of a sector, which is a data management area of the optical disc, and a fluctuation of the envelope of the reproduction signal due to a fluctuation of the medium reflection, a mechanism for detecting a peak envelope is required. FIG. 22 shows a state of occurrence of a transient. This transient occurs because the reproduction system is AC-coupled and the DC component is lost. The band of this AC coupling is the reproduction signal RD
S is set sufficiently low (1/100 to 1/50 of the signal frequency) to prevent S from being distorted by sag or the like. As described above, at the fixed slice level, a considerable area of data is lost from the start of data.

FIG. 23 shows an example of a configuration for determining a slice level using a peak hold circuit. Reference numeral 81 denotes a peak hold circuit including a diode and a capacitor, and reference numeral 82 denotes a slice level determination circuit. The capacitor C stores the peak value of the reproduction signal RDS. That is,
When the reproduction signal RDS becomes equal to or higher than the terminal voltage of the capacitor, the diode is turned on, the capacitor is charged, and the reproduction signal RD
When S falls below the peak value, the diode is cut off and discharges the charged charge via the resistor R (time constant τ = CR).
As a result, the terminal voltage of the capacitor C changes following the peak value and is input to the slice level determination circuit 82 via the buffer amplifier BA. Slice level determination circuit 8
2 determines a slice level Vs for creating a gate signal based on the peak value of the reproduction signal RDS. Incidentally, in order to accurately hold the peak value of the reproduction signal RDS by the peak hold circuit 81, the buffer amplifier needs to have a high speed, and specifically, a tracking characteristic on the order of ns is required. In addition, the precision of the buffer amplifier becomes a problem in order to reduce the leakage of the capacitor C holding the peak value, and furthermore, a function of canceling the decrease in the forward voltage of the diode is required, and the actual function is required. There are many disadvantages for the application of. Further, a more serious problem is that in a peak hold using a diode or a transistor, even if a peak voltage can be obtained, there is no function to correct the waveform itself, and the influence of temperature fluctuation and the like cannot be ignored.

As described above, even when the resolution is reduced due to the increase in density or the change in recording conditions, data can be read more accurately from the optical disk.
There is a demand for an optical disc reproducing apparatus capable of preventing adverse effects due to transients and envelope fluctuations at the start of data due to AC coupling of the reproducing system. FIG.
Is a block diagram of an information reproducing apparatus proposed in Japanese Patent Laid-Open No. 3-102677, and FIG. 25 is a waveform diagram of each part for explaining the operation. 9
1 is an amplifier for amplifying the reproduction signal RDS, 92 is a low-pass filter, 93 is a differential zero cross detection circuit for differentiating the reproduction signal and generating a zero cross signal ZCS when the differential signal DS crosses a zero level, and 94 is a reproduction circuit. A clamp circuit 95 for clamping the lower limit level of the signal RDS, a gate signal generation circuit 95 for outputting a binary signal obtained by slicing the output signal of the clamp circuit Vout at a predetermined level Ls as a gate signal GTS, and a gate signal GTS 96 Is inverted when the zero cross signal ZCS falls during the high level period,
In addition, when the gate signal GTS becomes a low level after the generation of the zero cross signal, the reproduction digital signal generation unit generates the reproduction digital signal DT so as to be inverted again.

The clamp circuit 94 has an npn transistor 94 whose base terminal is supplied with the clamp control voltage Vset and whose emitter terminal output is the output of the clamp circuit.
a, a resistor 94b connected between the emitter and ground,
It has a capacitor 94c for cutting DC components. When the input signal Vin is larger than Vcc, the transistor 94a
Is turned off, and the input signal Vin is output as it is as Vout. On the other hand, when the input signal Vin is smaller than Vcc, the transistor 94a is turned on, and the bias voltage Vcc is output. That is, the clamp circuit 94 sets the lower limit level to Vcc.
Output the signal clamped to.

According to this clamp circuit, as shown in FIG. 25E, the lower limit level of the reproduction signal RDS corresponding to the modulation data "0" (non-mark) can be clamped to a constant voltage. That is, even when the resolution of the reproduction signal RDS is small, the resolution can be equivalently increased by passing the signal through the clamp circuit 94, and the peak point of the reproduction signal (the differential signal zero crossing point) is surely obtained. ), The gate signal GTS at a high level can be created, and the reproduced digital signal generator 96 can correctly reproduce data.

However, a transistor (including a diode) clamp has a disadvantage that a transition time when the transistor is turned on → off is long due to the influence of the base accumulated charge. Therefore, as shown in FIG. 26, a time lag of several ns to several ms occurs between the reproduction signal RDS and the clamp output signal Vout, and the time lag Td also occurs in the gate signal GTS. The time lag of the gate signal GTS causes a problem when the density is increased (high-speed transfer). Further, since the proposed clamp circuit clamps the lower limit level, as shown in FIG. 27, when the reproduced signal RDS is loaded with noise NS due to a disk defect, the peak value of the noise is reduced to the slice level. There is a problem that erroneous reading may occur at Ls or more.

From the above, it can be seen that the object of the present invention is to provide an AGC system even when the amplitude of a reproduced signal fluctuates due to the use environment (especially the environmental temperature).
An object of the present invention is to provide a reproducing apparatus capable of automatically setting a clamp signal amplitude to an optimum amplitude by an operation to increase a device margin. Another object of the present invention is to provide a reproducing apparatus capable of coping with high-speed transfer by clamping a peak value of a reproduced signal at high speed by a Schottky barrier diode clamp circuit, and being resistant to defects (not affected by defects). />. Still another object of the present invention is to enable the AGC control to optimize the signal amplitude after clamping even if the characteristics (forward drop voltage) of the Schottky diode corresponding to the slice level fluctuate due to the environmental temperature and the junction surface temperature. Another object of the present invention is to provide a reproducing apparatus capable of increasing an apparatus margin.

[0026]

FIG. 1 is a diagram illustrating the principle of the present invention. 101 is a variable gain amplifier (AGC) for amplifying the reproduction signal RDS read from the optical disk;
2 is an AGC control unit, 104 is a clamp circuit that clamps the peak value of the amplifier output signal, 105 is a gate signal generation unit that compares a clamp voltage output from the clamp circuit with a predetermined signal level and generates a gate signal GTS, 106
Is a differential / zero-cross signal generator that outputs a zero-cross signal ZCS when the differentiated signal crosses a zero level, 107 is a data pulse output unit, 108 is a signal amplitude output from the clamp circuit. This is an amplitude comparing unit that detects a difference from a reference voltage level.

[0027]

The amplitude comparing section compares the amplitude of the clamp signal output from the clamp circuit 104 with the reference voltage level and outputs an amplitude difference. The AGC control unit 102 generates a control voltage signal Vcnt for controlling the gain of the variable gain amplifier 101 based on the amplitude difference. Gate signal generator 105
Is a clamp signal CL output from the clamp circuit 104
The gate signal GTS is generated by comparing P with a predetermined signal level, and the data pulse output unit 107 outputs a data pulse when the zero cross signal ZCS is generated while the gate signal GTS is generated. Thus, the clamp circuit 104
By clamping the peak of the reproduction signal RDS to a predetermined potential, the peak value is always clamped to a constant potential even if the peak value of the reproduction signal fluctuates, and the gate signal GTS is generated based on the constant peak value. it can. As a result, even if the peak value fluctuates, the gate signal can be accurately generated, and even if the resolution is reduced due to a high density or a change in recording conditions, or if a transient or envelope fluctuation exists. Even with this, data can be read accurately. Further, since the peak value is clamped at a constant potential, the slice level for generating a gate signal can be set higher, so that noise caused by a defect or the like is not erroneously read and the influence of the defect can be eliminated. .

Further, the clamp circuit 104 is constituted by using a Schottky diode, and the reference voltage level in the amplitude comparing unit 108 is set to 1.1 to 1.7 times the forward voltage of the Schottky diode. In this way, even if the amplitude of the reproduction signal fluctuates due to variations in the medium characteristics or between drives, the amplitude of the clamp signal can be automatically set by the AGC operation so as to be optimal, and the apparatus margin can be increased. Further, even if the characteristics (forward voltage drop) of the diode fluctuate due to the environmental temperature or the junction temperature, the amplitude of the clamp signal can be optimized by AGC control, and the device margin can be increased.

[0029]

【Example】

(a) Overall Configuration FIG. 2 is a block diagram of an embodiment of a data reproducing circuit of the present invention in an optical disk drive. Reference numeral 101 denotes a variable gain differential amplifier for amplifying a reproduction signal read from an optical disk, and reproduction signals RDS1 and RD having different polarities from each other.
S2 is input, and two signals having different polarities are output. The reproduced signals RDS1 and RDS2 are supplied to the P-wave component detector 21 ₁₁ and the S-wave component detector 21 ₁₂ shown in FIG.
This corresponds to the output signals RDS1 and RDS2 (see FIG. 16C). 102 is a reproduction signal RDS
1, an AGC control unit for setting the amplitude of RDS2 to a predetermined value, 10
Reference numeral 3 denotes a waveform processing unit which receives two signals having different polarities from the variable gain amplifier 101, and includes a low-pass filter and an equalizer. The low-pass filter and the equalizer are inserted to remove noise in the high frequency band, appropriately emphasize the high frequency side of the reproduced signal, prevent reduction in resolution, and remove peak shift.

Reference numeral 104 denotes a clamp circuit for clamping the peak values of the two reproduced signals RD1 'and RDS2' output from the waveform processing unit. The clamp circuit 104 clamps the + -side peak value of the reproduced signal RDS1 '. For ', the negative peak (bottom) is clamped to a constant value. A gate signal G 105 compares the voltage levels of the clamp signals CLP and CLP 'output from the clamp circuit.
Gate signal generator (comparator) for generating TS, 1
06 is a reproduced signal RDS1 'output from the waveform processing unit,
A differential / zero-cross signal generator 107 that differentiates RDS2 'and outputs a zero-cross signal ZCS when the differential signal of the differential signal crosses a zero level. Reference numeral 107 denotes a peak point of the reproduction signal RDS1 (a zero-cross point of the differential signal). A data pulse output unit for outputting a data pulse at 108; an amplitude comparing unit 109 for comparing the amplitude of the clamp signal CLP output from the clamp circuit with the reference voltage level Vr to AGC the amplitude difference and inputting the difference to the control unit 102; Is a reference voltage generator for generating a reference voltage Vr.

(B) Configuration of Each Unit FIG. 3 is a configuration diagram of each unit behind the waveform processing unit, and FIG. 4 is a waveform diagram of each unit. In FIG. 4, ID is an address field (ID area) provided at the head of the sector,
F is a data field DF provided after the ID area
(MO area), and the MO area has a V for clock extraction.
The FO, a sync byte SYNC for phase matching, and user data DATA are written.

Clamp circuit Clamp circuit 104 generates reproduced signals RDS1 ', RDS
2 ′, two capacitors C ₀ for cutting the direct current component, two current limiting resistors R ₁ connected in series to the capacitor C ₀ , bias resistors R ₀ and R ₂ , and sequentially via the bias resistors. Schottky diode D ₁ biased in the direction
, The anode side of the Schottky diode is connected to the + terminal of the comparator CMP constituting the gate signal generation unit 105, and the cathode side is connected to the-terminal of the comparator CMP. Schottky diode D ₁
Since there is no influence of accumulated charge in principle, there is no signal delay as compared with a clamp circuit using a transistor or another diode. Further, the Schottky diode can take a constant value without depending on the applied voltage, so that it can always be clamped at a constant potential.

[0033] Now, in a state there is no input signal, the potential of the non-inverting terminal (+) of the comparator CMP, the inverted terminal (-) forward voltage V _F is applied potential potential of the Schottky diode D ₁ of the (V _T = I ₁ · R ₂ + V _F ). In such state, when the signal RDS1 having a transient shown in FIG. 4 "is input, the potential rise at the start of the transient is held at a constant voltage for the Schottky diode D ₁ is turned on, FIG. 4 It is clamped at V _T, as shown in the clamp signal CLP in. Here, the current limiting resistor R ₁ connected in series with the capacitor C ₀ acts to reduce the load on the driver that drives the clamping system. That is, the rising potential point during transient start is to work the diode clamp, there is a possibility that flows a large current is not a current limiting resistor R _1, the current is limited resistor current by R ₁ is limited, the driver of the load It is reduced. However, the current limiting resistor R ₁
Is too large, the clamp circuit will not work.
Several tens of ohms are sufficient.

Next, when the input signal RDS1 'drops, a current path is formed in the direction of Vcc → R ₀ → R ₁ → C ₀ → input signal terminal, and the non-inverting terminal voltage of the comparator CMP (clamp signal CLP) Is the input signal R as shown in FIG.
It changes following DS1 '. At this time, the capacitor C
_The electric charge is charged to ₀ , but is discharged through the resistor R ₁ and the Schottky diode D ₁ when the input signal RDS1 ′ rises. From the above, the peak value of the transient and envelope variation due to reflectivity variation is absorbed by the reproduction signal at the time of start of data is clamped to V _T, the input signal R in the following V _T
The signal waveform follows DS1 '. The above is the input signal R
This is a case where attention is paid to DS1 ', but the input signal RDS2'
Focusing on, as indicated by a dotted line in FIG. 4, the clamp signal CLP 'is clamped bottom within V _R, in the above V _R input signal RDS2' becomes a signal waveform following the.

In the clamp circuit 104, the time constant τ (= C ₀ · R) determined by the capacitor C ₀ and the diode bias resistors R ₀ and R ₂ is the longest pattern of the input signal (from the peak point to the next peak point). Pattern with the longest time)
Need more. This is because below this, the bottom level cannot be maintained. For example, ISO
The standard adopts the (2,7) RLL encoding method as a recording format of 5 inches and 3.5 inches. According to the (2,7) RLL coding method, the number of "0" between the bit "1" and the bit "1" after coding varies from 2 to 7, and the longest pattern has a bit interval of T and Then, it becomes 8T. Therefore, the time constant τ (= C ₀ · R) needs to be larger than 8T. The upper limit of the time constant is determined by a VFO pattern period provided for extracting a clock component from data at the start of data. This is because, when a transient opposite to that of FIG. 4 occurs (a transient in the opposite direction may occur depending on the influence of the immediately preceding ID crosstalk or the like) at the start of data, the VFO period during which peak clamp operates is performed. This is because it is necessary to establish a transient.

The gate signal generator gate signal generator 105 is composed of a comparator CMP, its non-inverting terminal (+) to the clamp signal CLP is input, the inverting terminal (-) clamp signal CLP 'is input to the non-inverting When the terminal potential is higher than the inverted terminal potential, a high-level gate signal GTS is output. Differentiation / zero cross signal generation section Differentiation / zero cross signal generation section 106 generates reproduction signal RDS
1 'and RDS2' are differentiated signals DFS,
A differential circuit 106a having a CR configuration for outputting DFS 'and a comparator 106c for outputting a high-level zero-cross signal ZCS when the difference signal between the differential signals DFS and DFS' becomes equal to or lower than zero level are provided.

Data pulse output unit The data pulse output unit 107 outputs a data pulse (reproduction data) DT when the zero cross signal ZCS is generated while the gate signal GTS is being generated, that is, at the peak point of the reproduction signal RDS1. It is supposed to. 107a is a flip-flop, and 107b is a delay unit for setting a predetermined delay time. When the zero cross signal ZCS is generated while the gate signal GTS is at the high level, the flip-flop 107a is set and reset after the elapse of the delay time. As a result, a data pulse DT having a width corresponding to the delay time is output. The data pulse output unit 107 is formed by an AND gate, and the gate signal GT is output by the AND gate.
By calculating the logical relationship between S and the zero cross signal ZCS, the data pulse DT can be output.

FIG. 5 is a block diagram of an amplitude feedback system for feeding back the amplitude of the clamp signal to the variable gain amplifier 101.
7 is a waveform diagram for explaining the operation of the amplitude feedback system. 1
08 is a clamp signal CLP output from the clamp circuit.
And an amplitude comparator 102 for outputting an amplitude difference between the reference voltage level Vr and the control voltage signal Vcnt according to the amplitude difference.
Is a reference voltage generation unit, and n (= 1.1 to 1.... N) of the forward voltage drop V _F of the Schottky barrier diode D ₁ included in the clamp circuit 104.
7) Generate double reference voltage Vr. In addition, n = 1.1-
The reason for setting to 1.7 will be described later. In the amplitude comparing unit 108, reference numeral 108a denotes an amplitude comparator for comparing the amplitude of the reference voltage Vr with the clamp signal CLP input from the clamp circuit, and 108b denotes constant current sources Iin and Iout and a switch SWi.
A charge pump composed of n and SWout turns on and off the switches SWin and SWout based on the output of the amplitude comparator 108a to perform suction / discharge. In the AGC control unit 102, a low-pass filter 102a converts a current output of the charge pump into a voltage, and a buffer amplifier 102b outputs a low-pass filter output as a control voltage signal Vcnt.

The reference voltage generator 109 is provided with the clamp circuit 10
Provided in the vicinity of 4, the Schottky barrier diode D ₁ of the Schottky barrier diode D ₁ and the same characteristics of the clamp circuit 104 ', a bias resistor R ₀ of the diode to forward bias Schottky diodes D _1' forward voltage of the drop V _F has n (= 1.1 to 1.7) multiplied multiplying unit (e.g. an amplifier) MLT. The forward voltage drop V _F of the Schottky barrier diode D ₁ ′ is calculated by the multiplier ML
T is multiplied by n (= 1.1 to 1.7), and the comparator 10
8a is input to the-terminal. On the other hand, the clamp signal CLP
Is also input to the + terminal of the comparator 108a.
Comparator 108a compares the amplitude of both input, when the clamp signal amplitude of Vr (= n · V _F) below, and outputs a low level of the drive signal CD, in the case of more than n · V _F is high A level drive signal CD is output. Drive signal C
When D is at the low level, the switch SWout is turned on, and the charge stored in the capacitor of the low-pass filter 102a is discharged. Conversely, when the drive signal CD is at the high level, the switch SWin is turned on and the low-pass filter is turned on. The electric charge is charged in the capacitor of the filter 102a. As a result,
As shown in FIG. 6, the control voltage signal V increases or decreases according to the amplitude of the clamp signal CLP from the low-pass filter 102a.
cnt is output.

Although the case where only the capacitor is used as the low-pass filter 102a (transfer function F (s) = 1 / sC) is shown, a secondary filter in which a resistor and a capacitor are connected in series (transfer function F (s) = R + 1 / sC). 2
The operation principle of the next filter is completely the same as that of the case of using only the capacitor, and which one to select depends on the system design. In the amplitude comparison unit 108, the charge / discharge currents Iin and Iout increase at the time of AGC pull-in at the start of data, and thereafter decrease, so that the AGC attack time can be reduced. As a result, the response time of the variable gain amplifier 101 is reduced by the control of the AGC control unit 102, which will be described later, and the adverse effect due to the amplitude fluctuation based on the data pattern is eliminated.

Variable Gain Amplifier FIG. 7 is a block diagram of a variable gain amplifier. The configuration shown in FIG. 7 is called a Gilbert cell and is already used in many circuits. Variable-gain amplifier 101, a differential amplifier stage 101a, a bias portion 101b for supplying a current to each transistor of the differential amplifier stage with transistors Q _5, Q ₆ of the reproduction signal RDS1, RDS2 of different polarities are input together, Constant current section 101c, output buffer stage 101
d, a transistor switch section 101e. The transistor switch unit 101e controls the gain of the differential amplifier stage 101a according to the control voltage signal Vcnt output from the AGC control unit 102 and the preset reference voltage Vref.
(Q ₁ , Q ₂ ) and SW2 (Q ₃ , Q ₄ ). Transistor switch unit 101e compares the control voltage signal Vcnt and the reference voltage Vref, so that the reference voltage and the control voltage is equal to controlling the conductivity of the transistor Q ₁ to Q _4, the gain as a result, the differential amplifier 101a Control the playback signal R
The amplitudes of DS1 and RDS2 are set to optimal values.

The operation principle will be briefly described. The differential input signals (reproduction signals) RDS1 and RDS2 are
Input to the transistors Q ₅ and Q ₆ of FIG. The load of each transistor, the transistors Q _1, Q ₂ and Q _3, Q transistor switch SW1 is constituted by _4, S
W2 is connected, a control voltage signal Vcnt is connected to one base of each transistor, and a reference voltage signal Vr is connected to the other.
ef is applied. Reference voltage Vref> Control voltage signal Vc
In the case of nt, the transistors Q ₂ and Q ₄ are turned on, and the transistors Q ₁ and Q ₃ are turned off. Therefore, the reproduction signal RDS
1 and RDS2 appear in the load resistance _RA of the transistors Q ₂ and Q ₄ , and input signals RDS 1 ″ of the next stage waveform processing unit 103 via the transistors Q ₇ and Q ₈ of the buffer stage 101 d.
RDS2 ″. At this time, the maximum gain is obtained, and the voltage gain is R _A / R _B.

Next, the reference voltage Vref <the control voltage signal Vcnt
, The transistor Q₁, Q_ThreeTurns on and the transi
Star Q_Two, Q_FourTurns off. Therefore, the reproduction signal RDS
1, RDS2 is the load resistance R_ADisappeared at all from gay
Is zero. In fact, due to the feedback loop
Control is performed so that the reference voltage Vref ≒ the control voltage signal Vcnt.
And the signal amplitude of the clamp signal CLP is reduced.
Tokibarrier diode D ₁Forward voltage drop V_FN (=
1.1 to 1.7) times.

(C) Margin In the embodiment of FIG. 3, a slice for creating a gate signal GTS is used.
Level is Schottky diode D₁Forward voltage drop
Lower V_FAnd the forward voltage drop V _FAnd kura
The amplitude of the pump signal is
It has a lot to do with gin. Generally Schottky Dio
Forward voltage drop V_FIs strongly temperature-dependent,
The higher the temperature of V_FHas a tendency to decrease. Light de
Disk operating environment temperature (5⁰C ~ 45⁰C) When operating
Considering heat, etc., the temperature change at the joint surface is 0⁰C-80⁰C
As described above, this temperature change causes V_FIs twice (1 /
2) Change near. Therefore, to improve margin
Has V_FThe reproduction signal, that is, the clamp signal
It is necessary to control the amplitude of the signal. On the other hand,
Depending on the firing rate, the performance of the medium, and the playback efficiency, the playback signal amplitude
It fluctuates up to almost twice. Therefore, the amplitude of the reproduced signal fluctuates.
Then V_FMust be controlled so that the amplitude becomes appropriate according to
It is necessary.

FIG. 8 shows an example of measuring the margin with respect to the amplitude of the clamp signal in the embodiment shown in FIGS. This figure shows a signal amplitude ratio (signal amplitude / V _F ) and a margin deterioration at the time of creating a gate signal. As a result, the clamp signals CLP,
Signal amplitude of CLP 'is most characteristic when 1.1 to 1.7 against the V _F is found to be good. To clear this target amplitude is 1.1 in the forward voltage drop V _F of the diode
A value multiplied by 1.7 is generated as the reference voltage Vr. Then, a difference between the reference voltage Vr and the signal amplitude of the clamp signal CLP is detected by the amplitude comparison unit 108, and a control voltage signal Vcnt corresponding to the difference is output from the AGC control unit 102 to change the gain of the variable gain amplifier 101. Control. Thus, the signal amplitude of the clamp signal CLP is feedback controlled such that n (= 1.1 to 1.7) times the forward voltage drop V _F of the Schottky barrier diode D _1.

(D) Modification In the above, a variable gain amplifier, a waveform processing unit, a clamp circuit, and a reproduction signal RDS1 and RDS2 having different polarities are used.
In the case where predetermined processing is performed in the gate signal generation unit, the data pulse DT may be generated using a reproduction signal RDS obtained by calculating a difference between the reproduction signals RDS1 and RDS2. In such a case, the circuit after the clamp circuit is configured as shown in FIG. Clamp circuit 104
The well is only single signal component compared to FIG. 3, the clamp signal CLP is input to the non-inverting terminal of the gate signal generator 105 (+), an inverting terminal (-) in the _{Vb + V F / 2 (V} F diode Forward drop voltage) is input.

Ideally, the comparison potential of the clamp signal CLP in the gate signal generation section 105 is set to around 50% of the reproduction signal amplitude in the longest pattern, that is, 50% of the maximum amplitude. This is because the S / N ratio of the reproduced signal deteriorates,
This is because a so-called level margin for preventing an erroneous gate signal from opening is maximized at the center of the reproduced signal. Therefore, Vb is applied to the inverting terminal of the comparator CMP.
+ V _F / 2 is input. FIG. 10 is a signal waveform diagram of each part in FIG. Although the reproduction of the information in the MO area has been described above, the present invention is also applicable to the reproduction of the information in the preformat section (ID area).
Further, the case where the Schottky diode is used has been described above, but other high-speed diodes can be used. Furthermore, although the present invention has been described above with reference to the embodiments, the present invention can be variously modified in accordance with the gist of the present invention described in the claims, and the present invention does not exclude these.

[0048]

As described above, according to the present invention, the peak of the reproduced signal is clamped to a predetermined potential in the clamp circuit, and the gate signal is generated based on the constant peak value. Gate signal can be generated accurately, and even if the resolution is reduced due to the increase in density or the change in recording conditions, or even if there is a transient or envelope fluctuation, data can be read accurately. Can be. Furthermore, according to the present invention, since the peak value is clamped at a constant potential, the slice level for creating a gate signal can be set higher, so that noise generated due to a defect or the like is not erroneously read and the defect is not detected. The effect can be eliminated.

Further, according to the present invention, the clamp circuit is constituted by using a Schottky diode, and the reference voltage level in the amplitude comparing section is set to 1.1 to 1.7 times the forward voltage of the Schottky diode. AGC control is performed so that even if the reproduction signal amplitude fluctuates due to variations in the medium characteristics and drives, the AGC operation will
The apparatus margin can be increased by automatically setting the amplitude of the clamp signal to be optimal. Also, even if the diode characteristics (forward voltage drop) fluctuate due to the environmental temperature or junction temperature, the amplitude of the clamp signal can be optimized by AGC control.
The device margin can be increased. Further, since the Schottky diode is not affected by the accumulated charge, it can clamp the peak value of the reproduced signal at high speed without delay, and can cope with high density and high speed transfer.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of a data reproduction circuit of the present invention.

FIG. 3 is a configuration diagram of each unit behind a waveform processing unit.

FIG. 4 is a waveform chart of each part.

FIG. 5 is a configuration diagram of an amplitude feedback system.

FIG. 6 is a waveform chart for explaining the operation of the amplitude feedback system.

FIG. 7 is a configuration diagram of a variable gain amplifier.

FIG. 8 is an explanatory diagram of a margin measurement result with respect to a signal amplitude.

FIG. 9 is a configuration diagram of each section showing a modification of the present invention.

FIG. 10 is a waveform diagram for explaining the operation of the modification.

FIG. 11 is an explanatory diagram of writing / reading of a magneto-optical disk.

FIG. 12 is a configuration diagram of a magneto-optical disk medium.

FIG. 13 is a system configuration diagram.

FIG. 14 is an electrical configuration diagram of the system.

FIG. 15 is a diagram showing a basic configuration of a magneto-optical head.

FIG. 16 is a diagram illustrating the principle of reading MO area information.

FIG. 17 is a configuration diagram of a magneto-optical disk drive device.

FIG. 18 is an explanatory diagram of a data reproducing method.

FIG. 19 is a configuration diagram of a data reproduction circuit.

FIG. 20 is an explanatory diagram of a conventional problem.

FIG. 21 is a diagram for explaining another conventional problem.

FIG. 22 is an explanatory diagram of a transient.

FIG. 23 is a configuration diagram using a peak hold circuit.

FIG. 24 is a configuration diagram of a conventional information reproducing apparatus.

FIG. 25 is a waveform diagram of each part.

FIG. 26 is a diagram illustrating a problem of a clamp circuit using a transistor and a diode.

FIG. 27 is an explanatory diagram of a problem of a lower limit level clamp.

[Explanation of symbols]

 101: Variable gain amplifier 102: AGC control unit 104: Clamp circuit 105: Gate signal generation unit 106: Differentiation / zero cross signal generation unit 107: Data pulse output unit 108: Amplitude comparison unit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/10 321

Claims (7)

(57) [Claims] 1. A zero-cross signal generator for differentiating a reproduced signal read from a storage medium and outputting a zero-cross signal when the differentiated signal crosses a zero level, and generating a gate signal using the reproduced signal. A reproducing apparatus for outputting a data pulse when a zero cross signal is generated while a gate signal is being generated; a variable gain amplifier for amplifying the reproduced signal; A clamp circuit that clamps the peak value, a reference voltage generator that generates the reference voltage level, an amplitude comparator that compares the amplitude of the clamp signal output from the clamp circuit with the reference voltage level, and a gain variable based on the comparison result An AGC control unit that controls the gain of the amplifier and controls the amplitude of the output signal of the clamp circuit; Reproducing device for generating a gate signal by comparing the clamped signal and a predetermined signal level force. 2. A clamp circuit comprising: a capacitor for cutting a direct current component of a reproduction signal; a bias resistor; and a diode biased in a forward direction via the bias resistor and having an anode connected to the capacitor. 2. The reproduction according to claim 1, wherein the reproduction is a diode clamp mechanism.
Equipment . 3. The reproducing apparatus according to claim 2, wherein the diode is a Schottky barrier diode. 4. The device according to claim 2, wherein the reference voltage level is determined in proportion to a forward voltage of the diode.
Playback device . 5. The reproduction according to claim 4, wherein the reference voltage level is 1.1 to 1.7 times the forward voltage of the diode.
Equipment . 6. The amplitude comparing section includes: a comparator for comparing a reference voltage with an amplitude of a clamp signal; and a charge pump for performing suction / discharge based on an output of the comparator.
2. The reproducing apparatus according to claim 1, wherein the AGC control unit has a low-pass filter that converts a current output of the charge pump into a voltage, and uses the low-pass filter output as a control voltage signal. 7. The time constant of the diode clamping mechanism due to a DC cut capacitor and a bias resistor is equal to or longer than the longest bit cell interval (the longest interval from a peak point to the next peak point), and 3. The method according to claim 2, wherein the length is equal to or less than the length of the leading VFO pattern.
Playback device .