JPH0721093A - Abnormality monitor system for direct memory access device - Google Patents

Abstract

PURPOSE:To monitor abnormality without adding a dedicated abnormality detecting device by counting the number of data transmitted from the same monitoring point at every constant period, and discriminating the abnormality of a channel from the result. CONSTITUTION:Data from a power system are collected through each cyclic information transmission equipment 4 in a DMA 5, and stored in a memory area 3. At that time, an address to which an access is performed is stored in an access address area 31. A monitoring mechanism 2-1 clears in zero the access address area (S1), delays in DELTAt time (S2), and adds 1 to a counter when the access address becomes a value except 0 (an access is performed) (S3-S4). Then, this processing is repeated prescribed times, and when the value of the counter is 0, the stop of a channel is judged (S9), and when the value of the counter is more than the prescribed number the runaway of the channel is judged (S8). Then, abnormality notification is operated in the both cases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality monitoring system for a direct memory access device (hereinafter referred to as a DMA device) which inputs / outputs power system status information and power system control information to / from a computer system.

[0002]

2. Description of the Related Art Conventionally, a direct memory access device has been generally used for the purpose of reducing the load on a central processing unit of a computer system. Therefore, whether the abnormality diagnosis itself is performed by the direct memory access device,
Or, almost no abnormality diagnosis itself was performed. In the case where the direct memory access device self-diagnoses, a monitoring device is required for each individual channel, and a new means for notifying the computer system of a response in the event of an abnormality is also required, which has not been implemented.

For example, FIG. 8 shows the contents of the invention of Japanese Patent Application No. 54-29420, the summary of which is as follows. That is, the monitoring mechanism 2 is provided for the memory area 3 inside the computer 1, and the memory area 3 is composed of the present access address data area 31 and the transmission data storage area 32. Then, the data from the power system is collected in the DMA 5 via each cyclic information transmission device CDT (1 to n) 4 and stored in the memory area 3 via the DMA 5. On the other hand, the monitoring mechanism 2 once clears the access address to 0 this time, and examines whether or not it remains to be cleared to 0 after a predetermined time, and if it remains to 0, an alarm is notified as an abnormality. In short, the monitoring computer system performs abnormality diagnosis with the monitoring mechanism 2, but DM
Only the abnormality of the device A was stopped, and no diagnosis was made for an abnormal case such as a runaway, and one-hand drop was performed.

[0004]

As described above, the conventional D
The abnormality detection of the MA device is performed by the monitoring program operating on the central processing unit of the monitoring control computer at every constant cycle, assuming that the access address data is not rewritten this time when the DMA device is stopped. The abnormality diagnosis is carried out by utilizing the action of rewriting the address data to the specific information and returning to the original state by the operation of the DMA device. That is, it is only possible to detect an abnormality in which the operation of the DMA device is stopped, and it is not possible to detect an abnormality such as an abnormally large number of operations or a runaway. Although it is possible to add a dedicated abnormality detecting means to each channel of the DMA device itself, in the case of a system with many monitored points in the supervisory control system and many cyclic information transmission devices, the abnormality to be added is added. The number of detection means increased and the cost performance was poor. The present invention has been made to solve the above-mentioned problems, and the load of a computer for centralized monitoring and control of a power system is set to a conventional level, and an entire power system monitoring and control system is provided without adding a dedicated abnormality detection device. It is an object of the present invention to provide an abnormality monitoring system for a DMA device that can improve the reliability and cost performance.

[0005]

A structure for achieving the above object will be described with reference to FIG. In the present invention, the computer 1
The monitoring mechanism 2, the DMA area 5 for inputting / outputting information to / from the DMA device 5, the cyclic information transmitting device 4 for transmitting the power system state to the monitoring center, and the data transmitted by the cyclic information transmitting device 4. Is directly transferred to the memory of the computer. The memory area 3 accessed by the DMA device 5 includes an area 31 for holding the access address data of this time and a storage area 32 for the transmission data.
Consists of.

[0006]

First, the DMA device 5 directly transfers the state data of the power system, which is transferred from the cyclic information transmission device 4, to the memory area 3 which is the access area of the DMA device 5.
The transfer data is separately transferred to the access address area 31 and the transmission data storage area 32 this time. This data transfer is performed each time the cyclic information transmission device 4 transmits information on the power system. The cyclic information transmission device 4 transmits the data of the same monitoring point every fixed period (T), but the transmission period is different for each channel due to the difference in the specifications of the cyclic information transmission device 4.

Next, the monitoring mechanism 2 which operates asynchronously with the DMA device 5 refers to the access address data storage area 31 this time at every Δt time interval for every set period t, and checks whether the content is other than 0. The count is performed for each channel, and the access address data area 31 is cleared to 0 this time. The counting process for each Δt is performed N times. After performing N times, the count value for each channel is checked, and if the count result is 0, it is determined that the operation is stopped, and the channel whose count value is n times or more has an abnormality such as runaway. As a thing, an abnormality is notified to outside. With this monitoring mechanism, it is possible to reliably monitor an abnormal operation such as a channel stop error or a runaway.

[0008]

Embodiments will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment for explaining an abnormality monitoring system of a DMA device according to the present invention. In FIG. 1, the same parts as those in FIG. 8 are designated by the same reference numerals and the description thereof is omitted. In Fig. 1, the difference from the conventional method is the monitoring mechanism 2-1. Where S1,
Each processing of S2 and S3 is the same as the conventional one. The outline of the monitoring mechanism according to this embodiment is as follows. If the access address is other than 0 in process S3, 1 is added to the counter in process S4, and the process is repeated sequentially until the specified number of times is reached in process S5.

When the number of times reaches the specified number in the processing S5, the processing S
It is determined in 6 whether the counter is not 0, and if the counter remains 0, an abnormality is notified in step S9 (in this case, the counter is determined to be stopped because the counter is 0), and the counter is set to 0 in step S6. If the counter is equal to or larger than the specified value in step S9, an abnormality notification (determined as runaway because it is equal to or larger than the specified value) is issued. That is, the alarm notification is divided into two abnormalities, stop and runaway. Other configurations are similar to those in FIG.

The details of the monitoring mechanism will be described below, but before that, an example of the operation of the DMA device 5 will be described with reference to FIGS. 1 and 2. 2 is a detailed view of the memory area. In FIG. 1, the state of the power system is transmitted to the monitoring center by the cyclic information transmission device 4. It is possible to transmit n pieces of data per one (one channel) 4, cyclic information transmission device. One piece of data is represented by N1 bits. Further, N2 bits are added to the address data indicating the affiliation of the data, and one data is represented by N1 + N2 bits.

For the purpose of improving the reliability of transmission,
Since all the bit data to be transmitted are also transmitted with an inverted value, one data is 2 × (N1 + N2) bits. When this one piece of data is transmitted through a transmission line of 1200 bits / second, the transmission time (T) is

[Equation 1] Becomes That is, at a cycle faster than the transmission time (T) seconds, 1
It would be impossible for a DMA device of one CDT channel to transfer data to the computer memory.

Next, the processing contents of one embodiment of the abnormality detection method for the DMA device according to the present invention will be described with reference to FIG. In FIG. 3, in step S31, when the DMA device 5 transfers the data received from the cyclic information transmission device 4 to the memory 3 of the computer, the current access address data area 31 to be updated is fetched at regular intervals, and this time for each channel. If the access address data is other than 0, 1 is added to the counter for each channel to calculate the number of address updates.

Next, in step S32, the number of address updates for each channel obtained in step S31 is compared with a predetermined upper limit value. When the number of updates exceeds the upper limit value, an abnormality such as runaway occurs. It is determined that Also, when the number of updates is 0, it is determined that an abnormal stop has occurred. Step S33 is a process for determining whether an abnormality is detected in step S32, and is a determination process for executing step S34 when an abnormality is detected. Step S34 is a process for informing the outside of the abnormality detected in step S32.

Next, the detailed operation of step S31 of FIG. 3 will be described with reference to FIG. FIG. 4 shows step S of FIG.
It is a flow chart explaining the details of 31. Step S
311 is a process for initializing the sampling number counter of the operation status data of the DMA device 5. Step S31
2 is a process for forcibly clearing the current access address data of the DMA device 5 for all areas. Step S
Reference numeral 313 is a process of performing a relative delay for a fixed time. If the DMA device 5 is operating during this delay, the present access address data is rewritten by the DMA device 5 into data other than 0. This delay time (T) is set to be twice or more the transmission time of the cyclic information transmission device 4 having the slowest data transmission cycle.

Next, in step S314, a channel counter for initializing the information collecting processes up to step S318 for each channel is initialized. next,
In step S315, the current access address data of the j-th channel is referred to. If it is other than 0, it is determined that the DMA device 5 is operating and the process proceeds to step S316 to add 1 to the operation counter. Step S317 is a process of counting up the processed channel number.

Step S318 is a process for checking whether or not the processes for all the channels have been completed. If not completed, the process proceeds to step S315. When completed, proceed to step S319
Proceed to the current data sampling process. As described above, the presence / absence of the operation of the DMA device 5 within the sampling time can be grasped by the processes of steps S315 to S318. In step S319, the reliability of the data is low due to the timing or the like in one operation confirmation, and therefore the same processing is performed N times to count up the number of times of sampling for averaging the number of operations.

Step S320 is a process for judging whether or not the number of times of sampling has reached the specified value N, and if it is less than the specified value, the process is repeated from step S312. that's all,
By the processes of steps S311 to S320,
The number of operations of the DMA device 5 at the specified sampling number (N) can be recognized for each channel.

Next, the detailed operation of step S32 in FIG. 3 will be described with reference to the flowchart of FIG. Step S321 is initialization processing of the abnormality flag. Step S322 is processing for initializing the channel number being processed. Next, step S323 is a process of determining whether the operation of the DMA device 5 has been performed once or more. When the operation is performed once or more, the process proceeds to step S324, and in step S324, it is a process of determining whether the abnormal operation is performed a specified number of times or more. If it is determined that the number of operations is the specified number of times or more, the process proceeds to step S325, and the abnormality occurrence flag is set to the abnormality occurrence state (runaway etc.).

If it is determined in step S323 that there is no single operation, the flow advances to step S326 to set the abnormality occurrence flag to the abnormality occurrence state (stopped). Then in step S327.
Is a process for updating the channel number to be processed. Step S328 is a process for determining whether the abnormality determination process for all the channels of the DMA device 5 has been completed. If not completed, the process is re-executed from step S323. By the series of processes of the above monitoring mechanism, it is possible to perform the operation stop abnormality monitoring of the individual channels of the direct memory access device and the abnormality detection such as the runaway operation without adding special hardware.

FIG. 6 shows another embodiment. In FIG. 6, each mechanism 1 to 5 is the same as that shown in FIG. In this embodiment, the DMA device management mechanism 6 notifies the DMA device 5 of the state based on the abnormality of the individual channel detected by the DMA device monitoring mechanism 2, and when the channel is stopped, the individual channel is reset. Make a start.
Further, in the case of a channel error such as runaway, a mechanism for forcibly stopping the channel in error is added.

FIG. 7 is a flowchart explaining the method of FIG. According to the method shown in this embodiment, the DMA device 5
The individual channel abnormalities of can be finely separated and detected, and the temporary stop can be automatically restarted. Also, the channel that has been operating abnormally many times and the runaway can be automatically stopped, and the abnormal part can be separated. Therefore, the reliability of the entire system can be significantly improved.

[0022]

As described above, according to the present invention, it is possible to perform fine abnormality monitoring of the DMA device of the supervisory control system of the electric power system without using special hardware. Further, the abnormal range is minimized, and the reliability of the entire system is significantly improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating an abnormality diagnosis method for a DMA device according to the present invention.

2 is a detailed configuration diagram of an access area of a DMA device indicated by reference numeral 3 in FIG.

FIG. 3 is a flowchart illustrating a DMA device abnormality diagnosis method according to the present invention.

FIG. 4 is a flowchart showing in detail the process of collecting DMA device abnormality diagnosis data of FIG.

FIG. 5 is a flowchart showing in detail the abnormality detection determination process of the DMA device abnormality diagnosis of FIG.

FIG. 6 is a configuration diagram for explaining another embodiment.

FIG. 7 is a flowchart for explaining another embodiment.

FIG. 8 is a configuration diagram for explaining a conventional technique.

[Explanation of symbols]

 1 computer 2 monitoring mechanism 3 memory area 31 current access address area 32 transmission data storage area 4 cyclic information transmission device 5 DMA device 6 DMA device management mechanism 6a channel start signal 6b channel stop signal

Claims (1)

[Claims] 1. A direct memory access device for directly inputting and outputting electric power system status data and control information to and from a memory of a computer for monitoring and control, and a transmission data storage area for inputting and outputting information for each channel on the memory of the computer. Direct memory access characterized by having an access address storage area for storing the input / output access address of each channel and monitoring the abnormality of each channel of the direct memory access device based on the transmission cycle information of the power system information Device abnormality monitoring method.