JPH07210495A - Microcomputer system - Google Patents

Abstract

PURPOSE:To eliminate an error in address setting while improving improving access efficiency without making access from a bus master wait in a multiplex bus system for address/data. CONSTITUTION:At the time of transferring DMA data between a memory 2 and plural peripheral devices 4 and 17 including a device, which can be the bus master, through the use of the multiplex bus for address/data by a DMA device 3, 10 codes are arranged to the DMA device and the plural peripheral devices so that an ID decoder 20 obtains a master ID code from the device to be the bus master to select one of address counters 19 with respect to the memory so as to access the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device, and more particularly to a device for DMA data transfer in a multiplex bus system.

[0002]

2. Description of the Related Art In a microcomputer, a memory (2-port
For memory, peripheral devices (disk, ROM)
Etc.) is generally used to transfer the data and execute the program.

These data are not read / written at random, but are transferred from an arbitrary address with a predetermined size. In addition, DMA (direct memory access) data transfer is often used to reduce the load on the CPU.

FIG. 3 shows the structure of DMA data transfer.
Reference numeral 1 is a CPU, 2 is a 2-port memory that can be accessed by both the CPU 1 and peripheral devices, 3 is a DMA device that controls DMA data transfer, and 4 is a peripheral device that is a data transfer target to a memory 2 such as a disk or a ROM. .

Further, 5 is a DMA address bus, 6 is D
MA data bus, 7 is address bus of CPU 1, 8
Is a data bus of CPU1, 9 is a memory write signal,
10 is an I / O read signal, 11 is a memory read signal,
Reference numeral 12 indicates an I / O write signal.

FIG. 4 shows an access sequence when the peripheral device 4 is a disk I / O. First, for the data transfer from the peripheral device 4 to the memory 2, the memory address of the transfer destination (provisionally n) is output from the DMA device 3. At the same time, it outputs an I / O data read signal to the peripheral device 4 and a memory write signal to the memory 2.

When one access is completed by this control,
The memory address is automatically incremented in the DMA device 3. For example, n for 1-byte data transfer
In the case of +1 and 2-byte data transfer, it is incremented to n + 2.

On the contrary, for data transfer from the memory 2 to the peripheral device 4, address data is output from the DMA device 3 and at the same time, an I / O data write signal is given to the peripheral device 4, and the memory 2 is transferred to the memory device 2. Outputs a memory read signal. Similarly, after the access is completed, the address is incremented according to the number of transfer bytes.

By the way, in a recent microcomputer system, as the memory capacity increases, the address,
The data bit width becomes very large, and the address width 32
The number of lines on the bus, such as the bit width and the data width of 32 bits, has increased significantly.

In particular, the DMA device 3 and the peripheral device 4 are CPUs.
When configured on a board (or device) different from 1, a large number of signal lines for the address / data bus and control signals will be drawn to the outside.

For this reason, not only is the device structure complicated due to an increase in the number of signal lines, but also electrical noise such as crosstalk is likely to occur, and a great reliability problem arises.

As a method of avoiding such a problem, there is a method of transferring addresses and data in a time division manner by multiplex. FIG. 5 shows a block diagram of this multiplex bus system, and FIG. 6 shows an access sequence.

In the figure, 13 is an address and data multiplex bus, 14 is an address strobe signal,
Reference numeral 15 indicates a data strobe signal. Reference numeral 21 is an address latch, and 22 is a memory address extracted from the multiplex bus.

According to this method, the address and the data are
Since it can be shared by two buses, the number of bus lines can be significantly reduced. However, since the address and the data are passed to the bus in a time division manner, the access efficiency is reduced.

DM without degrading the above access efficiency
A block transfer method can be considered as a method of transferring the A data. This configuration is shown in FIG. 7 and the access sequence is shown in FIG. In the figure, 16 is a counter with an address latch.

According to this method, a start address is given from the DMA device 3 to the memory 2 and latched in the memory 2, and the address is incremented every time a memory read or memory write signal is given. DMA without giving an address in the subsequent accesses
Data transfer is performed. As a result, the time for giving the second and subsequent addresses is reduced, and the access efficiency is improved.

[0017]

In the conventional configuration of FIG. 7, as shown in FIG. 9, the multiplex bus 13 is used.
In the case where the bus master 17 is installed in the DMA device 3, when the DMA device 3 transfers data in blocks of several kilobytes between the peripheral device 4 and the memory 2, the DMA device 3 operates in the meantime.
Keeps occupying the bus, causing the bus master 17 to wait for access to the memory 2.

This waiting time becomes longer as the amount of DMA data transfer increases, and the bus master 17 cannot secure the bus. Therefore, there is a high possibility that a bus time-out will occur, causing a system down. I will end up.

In order to solve this, if a method is adopted in which the DMA device 3 releases the bus for each data transfer between the peripheral device 4 and the memory 2, a block transfer is performed as shown in FIG. The access from the bus master 17 is inserted during the period, the value of the counter 16 becomes incorrect, and an error occurs in the access address.

Since it is difficult to recognize the bus arbitration by software, it is difficult to give an address again in the subsequent cycle of the DMA device 3.

An object of the present invention is to provide a microcomputer device in an address / data multiplex bus system, which does not wait for an access from a bus master and which improves access efficiency and eliminates an error in address setting. To provide.

[0022]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an address / data multiplex bus between a plurality of peripheral devices including a device that can be a memory and a bus master by a DMA device. In a microcomputer device that performs DMA data transfer using
Means for allocating an ID code to the DMA device and a plurality of peripheral devices connected to the bus to obtain a master ID code from a device serving as a bus master, and the means provided in association with the DMA device and each peripheral device. A plurality of address counters for counting the address of the
And a decoder for selecting one as an address counter of the memory.

[0023]

A DMA device and an address counter associated with each peripheral device are provided, and during the memory access cycle between the memory and one peripheral device, the memory access is performed by the address of the address counter corresponding to the ID code. I do.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, in which parts equivalent to those in FIG. 18 is a master ID code, 19 is a counter address latch group, 2
0 is an ID decoder.

The master ID code 18 is a number assigned to the bus masters connected to the multiplex bus 13. The ID decoder 20 detects the ID code in the memory 2 during an access cycle, determines which master is accessing, and selects the counter address latch corresponding to the master from the counter address latch group 19. Extract and use it as address data.

The operation of this embodiment will be described in detail below with reference to FIG.

When the DMA device 3 executes the DMA data transfer between the memory 2 and the peripheral device 4, the DMA device 3
Generates an address strobe pulse 14 while outputting an address in the first access. At the same time, the ID assigned to itself is output at the same time.

In the memory 2, I of the master ID code 18
Select the D code from the output of the decoder 20,
It latches in the address counter corresponding to the ID code from the address latch group 19 and outputs the address to the memory.

Thereafter, the DMA device 3 executes the data cycle together with the data strobe, and the corresponding address counter counts up at the rising edge of the data strobe. DMA during this data cycle
The device 3 outputs the ID code.

Next, in the second and subsequent cycles, DMA
The device 3 performs the data cycle while outputting the ID code. At this time, the counter / address / latch group 19
Among them, the address counter with the same ID gives the address counted up last time to the memory 2 and data
Run the cycle.

After the end of the data cycle, the address counter is further counted up at the rising edge of the data strobe.

When there is an access request from the bus master 17 to the memory 2, the bus master 17 also executes the memory cycle while outputting the ID code. The address counter does not operate, the address for the DMA device 3 remains held, the address counter assigned to the bus master 17 is selected, and the address is output to the memory 2. Then, the memory cycle is similarly executed.

As a result, the DMA device 3 and the bus master 17 do not conflict with each other, and the block transfer of the DMA device 3 can ensure normal operation without lowering the access efficiency.

In the embodiment, the bus master 17
Even if a DMA device is used instead of the above, the same operational effect can be obtained. Even if there are two or more memories 2, I
It is possible to expand by assigning D and the address counter in the same manner.

[0035]

As described above, according to the present invention, in the address / data multiplex bus system for reducing the number of buses, an address counter associated with the DMA device and each peripheral device is provided. , Memory and 1
During the memory access cycle with one peripheral device, the memory access is performed at the address of the address counter corresponding to the ID code, so the bus can be used for DMA block data transfer or single transfer from multiple peripheral devices. -Effective in address setting without waiting for access from the master and improving access efficiency.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is an example access sequence.

FIG. 3 shows an example of conventional DMA data transfer.

FIG. 4 is an access sequence for DMA data transfer.

FIG. 5 shows an example of a multiplex bus system.

FIG. 6 shows an access sequence of a multiplex bus system.

FIG. 7 is an example of block transfer.

FIG. 8 is a block transfer access sequence.

FIG. 9 shows an example of having a bus master.

FIG. 10 is a cycle-by-cycle bus release access sequence.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... Memory 3 ... DMA device 4 ... Peripheral device 13 ... Address and data multiplex bus 14 ... Address strobe signal 15 ... Data strobe signal 17 ... Bus master 18 ... Master ID code 19 ... Counter Address / latch group 20 ... ID decoder

Claims (1)

[Claims] 1. A microcomputer device for performing DMA data transfer between a memory and a plurality of peripheral devices including a device capable of becoming a bus master by a DMA device, using a multiplex bus for address / data, said bus comprising: Means for allocating an ID code to a DMA device and a plurality of peripheral devices connected to each other and obtaining a master ID code from a device serving as a bus master; and means provided in association with the DMA device and each peripheral device,
A plurality of addresses for counting the addresses of the memory
A microcomputer device comprising: a counter; and a decoder that decodes the master ID code and selects one of the address counters as an address counter of the memory.