JPH07210494A - Periodic communication processor - Google Patents

Abstract

PURPOSE:To reduce the load of CPU accompanying the execution of a periodic processing. CONSTITUTION:A scanning part 107 requires a meditation part 122 to connect a buss in accordance with the periodic processing start-up request of a periodic counter 101. In accordance with request, the meditation part 122 registers the scanning part 107 making the pertient request in a standby list 112. Besides, the meditation part 122 specifies one of the scanning parts registered in the standby list 112, instructs a selector 121 to connect this and a bus communication control part 123, and informs the scanning part 107 of the connection of the bus. In accordance with this bus connection information, the scanning part 107 reads out periodic processing information registered in a cyclic table 111 to transfer to the bus communication control part 123. The bus communication control part executes the periodic processing based on received periodic processing information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a periodic communication processing device for a system which periodically activates a process of transferring data to one or more objects via a bus.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a system in which a process of transferring data to one or more targets is periodically activated. In this system, one or more data transfer targets 3 are connected via a communication bus 2 to a data processing unit 1 having a central processing unit (CPU) 102, and the data processing unit 1 periodically transfers data. Execute the process.

As a method of controlling the bus without going through the CPU, the DMAC shown in "68000 Microcomputer" (edited by Yuzo Kida et al., Published by Maruzen Co., Ltd., pages 120-127).
(Direct Memory Access Controller)
There is a DMA method. The DMA method will be described below. The DMA method is a method of directly transferring data between memories without going through the CPU. During this time, the CPU is in a state of being disconnected from the communication bus, and DMA control I such as DMAC is used.
C has the right to use the bus and controls the data transfer. DM
In the A method, the CPU first sets a memory address to be accessed and a data size to be accessed, and makes a DMA data transfer request to the DMAC, which is a DMA controller. In response to this, the DMAC thereafter has the right to use the bus and transfers the data until the data transfer of the specified data size is completed. During this time, the CPU is disconnected from the communication bus and can perform processing other than data transfer. However, in this DMA method, the CPU resource is only released while a large amount of data is being transferred, and when the data transfer is repeated cyclically, the DMA transfer request is issued from the CPU each time. Must be set to the DMAC. Further, the data after the transfer is processed by the CPU. Further, there are a plurality of periodic processes, and when a plurality of process activation requests are simultaneously generated, the CPU arbitrates.

Here, the periodic processing means a data transfer processing which is repeatedly activated at a predetermined cycle.
The periodic process includes a periodic process that is constantly performed and a periodic process that is occasionally performed, depending on its execution form. As an example of the constant cycle processing, when a plurality of management targets are connected to a bus and the CPUs also connected to the bus manage these, it is prepared in the management target when the CPU monitors the system in real time. There is a process of periodically scanning the generated system management information. An example of the periodic processing performed as needed is a periodic scan of the measurement information in the real-time monitoring processing of the measurement information when the measurement function prepared in the management target is activated. Accompanied by the advanced function and complexity of system management in recent years, it has become necessary to collect a large amount of various kinds of system management information or measurement information in real time at high speed. When trying to realize the function by periodical scanning by the CPU,
Must perform a large amount of various processing within a limited time, and must repeat this periodically.
There is a problem that the addition of U increases.

[0005]

First, in the case of the periodic processing by the DMA method, the CPU executes the program corresponding to the activated periodic processing every time the periodic processing is activated. When there are a plurality of data transfer processes, the ratio of the periodic processing to the processing time of the CPU increases, which hinders the execution of the processing other than the cyclic processing, especially the execution of the processing program close to the application. Further, since it becomes necessary to transfer a large amount of data periodically, the load on the CPU becomes heavy by performing the periodic processing. Furthermore, when performing data transfer, the CPU is
The waiting time until the communication is established with the MA controller and the control time are required. However, when a plurality of data transfer processes are performed between a plurality of data transfers, the sum of these times is , The occupation time in the processing of the CPU is further lengthened. For this reason, the execution of processing other than the periodic processing is stressed.

Secondly, when there is a conflict between the periodic processes activated in a plurality of different cycles, the CPU performs the arbitration process by executing the program, so that the time C required for the periodic process is increased.
The ratio of PU to the entire processing time is further increased, which hinders the execution of processes other than the periodic process.

Thirdly, accompanying the cyclic processing, processing for the response of the cyclic processing result is performed by the CPU at any time when the response arrives. For details of the CPU processing for the response, first, the calculation performed for the response CPU of processing attributes each time
Is executed and an arithmetic program corresponding to the judgment result is executed. For this reason, the ratio of the processing to the response of the periodic processing result in the processing time of the CPU increases, which hinders the execution of other processing.

Therefore, an object of the present invention is to provide a cyclic communication processing device capable of reducing the load on the CPU due to the execution of the cyclic processing and improving the throughput of the CPU.

[0009]

In order to achieve the above object, according to the present invention, an arithmetic unit and a memory are provided, which are connected to at least one periodic processing target via a communication bus, and are connected to the periodic processing target. On the other hand, at a predetermined cycle,
In a cyclic communication processing device that repeatedly executes a predetermined data transfer process, the memory includes at least one cyclic table in which cyclic process information, which is information of the one or more data transfer processes, is registered in advance, and a bus. It has a standby list which is a storage area for registering a connection request, and the arithmetic unit has a bus communication control unit, a cycle counter, a cyclic table scanning unit, a scanning unit selector, and an arbitration unit. The bus communication control unit receives the transfer of the cyclic processing information, and based on the received cyclic processing information, specifies the cyclic processing information for the cyclic processing target specified by the cyclic processing information. Means for executing the data transfer processing, and the cycle counter is required to start the cyclic processing at at least one predetermined cycle. And a means for issuing a bus connection request to the arbitration unit in response to a periodic process activation request of the period counter, and a bus connection from the arbitration unit. In response to the notification, the cyclic processing information registered in the cyclic table is read out, and means for transferring the cyclic processing information to the bus communication control unit is provided, and the arbitration unit registers in the waiting list. A standby list registration unit and a selector control unit for controlling the scanning unit selector are provided, and the standby list registration unit responds to the bus connection request of the cyclic table scanning unit by issuing the cyclic request. The selector control unit includes means for registering a table scanning unit in the standby list, and the selector control unit is configured to scan the cyclic table in the standby list. Of these, a connection target determining unit that determines any one of them as a connection target, a unit for instructing the scanning unit selector to connect the cyclic table scanning unit that is the connection target, and the bus communication control unit, And a scanning unit selector having means for connecting the instructed cyclic table scanning unit and the bus communication control unit in response to an instruction from the selector control unit. A device is provided.

The connection target determining means may have a means for determining, as the connection target, the one having the highest priority among the cyclic table scanning units registered in the waiting list. Further, it is preferable that the cyclic processing information includes an identifier of a data transfer target, a data transfer start address, a processing type indicating whether the data transfer processing is reading or writing, and a size of data to be transferred. .

Further, in the present invention, the arithmetic unit performs a predetermined process on the input data,
The memory further includes at least one individual processing unit and a distribution processing unit that distributes the data read by the data transfer process to the individual processing unit, and the memory distributes the data read by the data transfer process. And a storage area for storing the processing result of the data by the distribution destination and a storage area for the processing result, and the individual processing unit receives the input. The data has a means for performing a predetermined processing and storing the processing result in a position designated by the input of the processing result storage area. The distribution processing unit refers to the individual processing table. A means for determining the individual processing unit for processing the data read by the data transfer processing and transferring the data to the individual processing unit. Periodic communication processing apparatus according to claim is provided.

A plurality of the individual processing tables are provided, and the arithmetic unit further has a table selector having means for connecting a designated one of the plurality of individual processing tables to the distribution processing unit. Then, the selector control unit instructs the table selector to connect an individual processing table determining unit that determines the individual processing table to be connected to the allocation processing unit, and the connection between the determined individual processing table and the allocation processing unit. It is also possible to further have means.

The individual processing table determining means is
A means for determining the individual processing table previously determined as corresponding to the cyclic table scanning unit that is the connection target by the connection target determining unit, as an individual processing table to be connected to the distribution processing unit. Also provided is a periodic communication processing device characterized by:

[0014]

A cyclic communication processing apparatus of the present invention has a cyclic table in which cyclic processing information is registered in advance in a memory and a standby list, and a bus communication control section and a predetermined cycle in an arithmetic section. And a cyclic table scanning unit, a scanning unit selector, and an arbitration unit.

The cyclic table scanning unit issues a bus connection request to the arbitration unit in response to the periodic process activation request from the period counter. In response to this bus connection request, the waiting list registration unit of the arbitration unit registers the cyclic table scanning unit that made the request in the waiting list. Also, the selector control unit of the arbitration unit determines one of those registered in the waiting list, instructs the scanning unit selector to connect this to the bus communication control unit, and cyclically connects the bus. Notify the table scanning unit. At this time, it is desirable to instruct to connect the one having the highest priority according to a predetermined priority. By the function of the arbitration unit, it is possible to perform arbitration in the case where competition of processing requests activated in different cycles occurs. In response to this bus connection notification, the cyclic table scanning unit
The cyclic processing information registered in the cyclic table is read out and transferred to the bus communication control unit. The bus communication control unit
Cycle processing is executed based on the received cycle processing information.

By doing so, the cyclic processing command can be issued autonomously, and the CPU that supervises the bus system needs to periodically repeat the processing for issuing the cyclic processing command. It is eliminated, and the throughput of the CPU is improved.

Further, the arithmetic unit includes at least one individual processing unit for performing predetermined processing on the input data, and a distribution processing unit for distributing the data read by the periodic processing to the individual processing unit. An individual processing table that is provided in the memory and holds a distribution destination of the data read by the data transfer processing and a position in a storage area that stores a processing result of the data by the distribution destination,
A storage area for processing results may be further provided. In this case, the individual processing unit performs a predetermined process on the input data and stores the process result at the designated position. Further, the distribution processing unit refers to the individual processing table, determines the individual processing unit that processes the data read by the data transfer processing, and transfers the data to the individual processing unit.

By doing so, since the cyclic processing and the arithmetic processing of the data read by the cyclic processing can be performed without depending on the CPU, the CPU controlling the bus system reads the data by the cyclic processing. There is no need to perform post-processing of the output data, and the CPU throughput is improved.

According to the periodic communication processing device for autonomously issuing the periodic process provided by the present invention, the data transfer control activated periodically can be realized without depending on the program execution of the CPU. When the CPU performs the data transfer control that is periodically activated, the processes other than the periodic process periodically performed by the CPU are interrupted, and the execution time of the entire process is extended. On the other hand, according to the periodic communication processing device of the present invention,
By removing the periodic data transfer process from the direct control of the CPU, the load on the CPU can be reduced and the speed of the process performed by the CPU can be expected. Further, the periodic communication processing device of the present invention has an arbitration unit, and the arbitration unit, according to the priority order, even when the activation requests for the periodic processing are simultaneously generated.
Since the execution order is determined, arbitration of processing for competition between different cycles can be realized without depending on the program processing of the CPU.

Further, according to the periodic communication processing apparatus for processing the data input by the periodic processing provided by the present invention, the processing contents of the input data and the storage location of the processing result are determined in advance, so that the periodic processing is performed. Can also be executed independently of the CPU. therefore,
Also in the periodic communication processing device for processing the input data, effects such as reduction of the processing load on the CPU and speeding up of the processing can be expected.

Further, in the periodic communication processing device having means for executing both the issuance of the periodic processing and the processing of the input data, the periodic processing, the subsequent processing and the response can be executed independently of the CPU. , The CPU does not need to be aware of the periodic processing and perform the processing. Such a periodic communication processing device can cause the periodic processing unit to notify the CPU only when the processing result changes or when the processing result satisfies a predetermined notification condition. . When the periodic communication processing device as described above is used, the CPU may perform processing such as updating the monitoring database only when receiving this notification. This eliminates the need for the CPU to perform the processing such as interruption and resumption of the periodic processing and other processing accompanying it, which has been performed so far.
In addition, the communication response waiting time or the access control time to the DMA controller, which occurs when communicating,
It is possible to save only the amount associated with the periodic processing, and the CPU is not occupied by the periodic processing, so that the processing capability of the CPU other than the periodic processing is improved.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows the configuration of the periodic communication processing apparatus in the first embodiment. The data processing unit 1 of this embodiment uses the CP
U102 and RAM (random access memory) 103
A ROM (Read Only Memory) 104 and a periodic communication processing device 100. CPU102 and RAM1
03 and the ROM 104 are connected to the periodic communication processing device 100 via the CPU bus 106, and are further connected to the communication bus 2 via the periodic communication processing device 100.

As shown in FIG. 8, the periodic communication processing device 100 of this embodiment comprises a computing unit 109 and a memory 108. The arithmetic unit 109 includes a CPU communication control unit 124, a bus communication control unit 123, an arbitration unit 122, and a selector 12.
It has 1 and 3 cycle counters 101 and 3 cyclic table scanning units 107. Also, the CPU
The bus 106 is connected to the CPU communication control unit 124, and the communication bus 2 is connected to the bus communication control unit 123. Here, the dotted arrows indicate the flow of data signals, and the solid arrows indicate the flow of control signals.

The memory 108 includes three cyclic tables 111 in which cyclic processing is registered, a standby list 112 in which the cyclic table scanning unit 107 or the CPU communication control unit 124 requesting bus connection is registered, and cyclic. The table scanning unit 107 and the CPU communication control unit 124 are provided with a priority order holding unit 113 in which the identifiers are associated with their priorities and registered in advance. Note that the registration and update in the cyclic table 111 are performed by the CPU 102 via the CPU communication control unit 124. The constant periodic process is registered at the initial startup of the system, and the occasional periodic process is registered, updated, or deleted at any time during system operation.

The memory 108 is a periodic communication processing device 100.
It may be provided outside the periodic communication processing device 100 as a bus control RAM connected to the CPU communication control unit 124. In this case, the data in the memory is sent and received by C
This is performed via the PU communication control unit 124. By providing the bus control RAM in this way, the periodic communication processing device 100 can be realized as an LSI (large-scale integrated circuit) regardless of the restrictions on the memory capacity.

In this embodiment, the cycle counter 101
The number of cyclic tables 111 and the number of cyclic tables 111 are each three, but the number is not limited to three. The cycle counter 101 has at least this cycle communication processing device 10
0 is prepared for the number of cycle types of the cycle processing. The cyclic table scanning unit 107 and the cyclic table 111 are used as the cycle counter 101.
Will be prepared. One cycle counter 101 and one cyclic table 111 are connected to each cyclic table scanning unit 107. If the priority order is different in the cycle processing executed in the same cycle, the cyclic table 111 and the cyclic table scanning unit 107 connected to the same cycle counter 101 may be further provided for each priority order. Alternatively, cycle counters having the same cycle may be provided only for the types of priority order, and the cyclic table scanning unit 107 connected to each of them may be provided and the cyclic table 111 connected to the scanning unit 107. Cyclic table 111, which is different for each priority
If it is registered in the above and is read by a different cyclic table scanning unit 107, a process with a high priority can be executed first.

The periodic communication processing device 100 of the present embodiment executes the periodic processing registered in the cyclic table 111 as C
It is a device that executes autonomously without going through the PU. The cyclic table 111, the cycle counter 101, and the cyclic table scanning unit 107 are provided for executing the cyclic processing. Further, the periodic communication processing device 100 is
An arbitration unit 122 and a selector 121 are included in order to autonomously adjust the execution order without going through the CPU 102. Further, the periodic communication processing device 100 includes a communication control unit 123 in order to perform actual data transfer control according to the data transfer target information read from the cyclic table 111.

The cycle counter 101 initializes the counter at a predetermined cycle, and the cycle counter 101
The issuance of the scan activation request 110 to the connected cyclic table scanning unit 107 and the counting of the fixed time are repeated.

The cyclic table 111 has information about cyclic processing that needs to be repeated at a specific cycle (the cycle in which the cycle counter 101 connected via the cyclic table scanning unit issues the scan activation request 110). It is a list registered in advance as a processing menu. The information of each process is registered according to the order in which the process should be executed. In this embodiment, the processing information includes an access target identifier (access target ID), a data transfer start address, a processing type (read / write), and the size of data to be accessed. Further, when the processing type is write, it further has the contents of data to be accessed.

Cyclic table 1 in this embodiment
The configuration of 11 will be described. FIG. 3 shows an example of the structure of the cyclic table 111. In the cyclic table 111, an information group regarding a data transfer target to be executed in each specific cycle is written in order according to the processing execution order. As shown in FIG. 3, the cyclic table 111 includes an access target ID storage area 132, a data transfer start address storage area 133, a processing type (readout).
/ Write) storage area 134, access size storage area 13
5 and access data storage area 136.
The periodic communication processing device 100 including the cyclic table 111 is connected to the communication bus 2, and a plurality of transfer targets 3 are further connected to the communication bus 2.

The cyclic process information registered in the cyclic table 111 is used in the process of the bus communication control unit 123 as follows. First, the identifier of the access target 3 held in the access target ID storage area 132 is used to specify a specific target from the plurality of data transfer targets 3 connected on the bus.
That is, of the plurality of data transfer targets connected on the bus, the one having an ID that matches the access target ID 3a
And the bus communication control unit 123 are established. The address held in the data transfer start address storage area 133 is used as a pointer indicating the beginning of the position 139 in the access target 3a where the data transfer is started. The value held in the access size storage area 134 is
Data area from the data transfer start point (data transfer area)
Used to indicate the range 137 of 138. This value also represents the length of data to be transferred. The code held in the data transfer process type storage area 133 represents read or write, and is used to specify which of the read and write processes the transfer process is.

Next, the cyclic table scanning unit 10
The processing flow of No. 7 will be described with reference to FIG. The cyclic table scanning unit 107 connects the cycle counter 10
It is activated in response to the scan activation request 110 issued by 1. First, the cyclic table scanning unit 107 that receives the scan activation request 110 requests the arbitration unit 122 to connect the bus (step 901) and waits for the bus to be connected by the selector 121 (step 902). . When the bus is connected, the cyclic table scanning unit 107 reads out all the cyclic processing information held in the cyclic table 111, and transfers the information to the bus communication control unit 123 via the selector 121 ( Step 90
3). When all the cyclic processing information held in the cyclic table 111 is read, the cyclic table scanning unit 107 notifies the arbitration unit 122 of the end (step 904) and ends the processing. Step 903
The bus communication control unit 123, which has received the data transfer in step 1, executes the specified process on the specified cyclic process target 3 in accordance with the transferred cyclic process information.

In this embodiment, communication from the CPU 102 is also performed via the bus communication control section 123. C
When there is a communication request from the PU 102, the CPU communication control unit 124 makes a bus connection request to the arbitration unit 122, as with the cyclic table scanning unit 107.
When the connection is notified, the data from the CPU 102 is transferred to the bus communication control unit 123. The bus communication control unit 123 that has received the transfer performs the communication instructed by the CPU 102. If the priority order of the CPU communication control unit 124 is set higher than the priority order of the cyclic table scanning unit 107, the communication of the CPU 102 can be prioritized over the periodic processing, and conversely. If the priority order is set low, the periodic processing can be preferentially performed.

The bus communication control unit 123 communicates with the designated data transfer target 3a using each of the above-mentioned data. That is, according to the code held in the processing type storage area 134, the bus communication control unit 123 stores in the access data storage area 135, which has a data length equal to the data length shown in the access size storage area 134 in the case of writing processing. The held data is stored in the area having the size shown in the access size storage area 134 (data transfer target area 138), which starts from the address held in the data transfer start address storage area 133. In the case of read processing, the bus communication control unit 123
Reads data having a data length equal to the data length indicated in the access size storage area 134 from the data transfer start address (address held in the data transfer start address storage area 133). In the case of read processing, in the present embodiment, the bus communication control unit 123 instructs the selector 121 to connect the bus to the CPU communication control unit 124, and reads the read data from the CPU communication control unit 124.
To the CPU 102, and causes the CPU 102 to generate an interrupt request. C that received the read data
PU 102 performs a predetermined process using the received data in accordance with the interrupt request. In this embodiment, when the bus connection instruction from the arbitration unit 122 and the bus connection instruction from the bus communication control unit 123 occur at the same time, the selector 121 gives priority to the bus connection of the bus communication control unit 123.

The arbitration unit 122 does not depend on the CPU 102,
It is a means for performing arbitration between processes autonomously started in a plurality of different cycles. The configuration of the arbitration unit 122 of this embodiment is shown in FIG. The arbitration unit 122 waits by referring to the standby list registration unit 143 that registers the cyclic table scanning unit 107 and the CPU communication control unit 124 that have issued the bus connection request in the standby list 112 and the priority order holding unit 113. It has a selector control unit 142 for instructing the selector 121 to detect the one having the highest priority among those registered in the list 112 and connect the data bus to the bus communication control unit 123.

FIG. 10 shows the flow of processing of the standby list registration unit 143. The standby list registration unit 143 is activated by the bus connection request 147 by the cyclic table scanning unit 107 or the CPU communication control unit 124. Upon receiving the bus connection request 147, the standby list registration unit 143
The cyclic table scanning unit 1 which issued the request 147
07 or the identifier of the CPU communication control unit 124 is stored in the standby list 112 (step 1001), and the process is terminated.

The processing flow of the selector control unit 142 is as shown in FIG. The selector control unit 142 uses the CP
It is activated by a start instruction of the CPU 102 input to the arbitration unit 122 via the U communication control unit 124. In addition,
In this embodiment, the CPU 102 issues a start instruction to the arbitration unit 122 when the system starts up.

The selector control unit 142 first checks whether the waiting list 112 is empty (step 1101) and waits until the waiting list 112 is not empty. If there is an identifier registered in the waiting list 112, the selector control unit 142 refers to the priority holding unit 113 and refers to the cyclic table scan having the highest priority among those registered in the waiting list 112. The unit 107 or the CPU communication control unit 124 (hereinafter collectively referred to as a communication output unit) is detected (step 1102: connection target determining unit). As shown in FIG. 4, the priority order holding unit 113 has a storage area 145 for the identifier of the connected communication output section and a storage area 146 for the priority order of the communication output section indicated by the corresponding identifier.

Next, the selector control unit 142 sets the detected data bus 141 of the communication output unit to the bus communication control unit 12.
Then, the selector 121 is instructed to connect to No. 3 (step 1103), and a bus connection notification is issued to the detected communication output unit (step 1104). The selector control unit 142 waits for the end notification from the communication output unit that has received the bus connection notification, and when the end notification is received (step 110).
5) The registration of the communication output unit is deleted from the standby list (step 1106), and the selector 121 is instructed to disconnect the bus (1107). When the CPU 102 issues an end instruction via the CPU communication control unit 124, the selector control unit 142 ends the process (step 110).
8) If there is no end instruction, the selector control unit 142
Returning to step 1101, the above processing is repeated.

Three cyclic table scanning units 107
FIG. 5 shows a time chart of the arbitration processing when the bus connection request 147 is issued from the above. Here, it is assumed that the three cyclic table scanning units 107 are cyclic table scanning units A, B, and C, and are connected to the cyclic tables A, B, and C, respectively. The priority of each cyclic table scanning unit is B,
It becomes lower in the order of A and C. In addition, the cyclic tables A, B, and C have periodic processes 151 and 1 respectively.
52 and 153 are registered.

First, each cyclic table scanning unit A,
The processes of B and C are the start interrupts (cycle start requests issued by the cycle counter) 154 to 15 corresponding to the respective cycles.
6 is activated. For example, like T1, a plurality of the periodic activation requests 154 to 156 may occur at the same time. If the cyclic activation requests 154, 155, and 156 are simultaneously generated, the cyclic process 152 of the cyclic table scanning unit B having a higher priority is preferentially executed. During this period, the cyclic tables A and C are kept waiting 157, and after the cyclic process 152 is completed, the cyclic process 151 of the cyclic table scanning unit A having the next highest priority is executed. During this time, cyclic table C
Is further waited 158, and after the processing of the periodic processing 151 is completed, the cyclic table scanning unit C having the lowest priority is
The periodic processing 153 is executed.

(Embodiment 2) By the above processing, the communication output units registered in the standby list execute the data transfer to the bus communication control unit 123 in the order of priority. In the above process, the cyclic table 11
All the cyclic processes registered in No. 1 are collectively transferred to the bus communication control unit 123 and executed.
It is also possible to limit the number of the periodic processes read in (1) to issue the bus connection request 147 for each periodic process. FIG. 12 shows a processing flow of the cyclic table scanning unit 107 in this case. In this case, a transfer pointer storage area is provided in the cyclic table 111 storage area for each cyclic processing information. Here, the value held in the transfer pointer storage area indicates the periodic processing information to be transferred next. In addition, cyclic table 1
The periodic processing information in 11 is transferred in order from the beginning.
First, the cyclic table scanning unit 107 in this case
Requests the bus connection to the arbitration unit 122 (step 901) and waits for the bus to be connected by the selector 121 (step 9), as in the case shown in FIG.
02). When the bus is connected, the cyclic table scanning unit 107 in this case changes the cyclic table 111.
Of the cyclic processing information stored in the transfer pointer storage area, the cyclic processing information indicated by the value stored in the transfer pointer storage area is read out, and the information is transferred via the selector 121 to the bus communication control unit 123.
To the arbitration unit 122 (step 904). If the transferred cycle information is not the last information (information registered in the last part of the cyclic table 111) (step 1202),
The cyclic table scanning unit 107 adds the data length of the cyclic processing information to the transfer pointer storage area so as to point to the next information (step 1203), and the above step 9
The processing from 01 to 1202 is repeated, and if the transferred cycle information is the last information, the address of the first cycle processing information is stored in the transfer pointer storage area (step 14
04) The process ends. By doing this, if there is a bus connection request from the communication output unit with a higher priority while the cyclic processes registered in one cyclic table are executed in the order in which they are registered, the above-mentioned registration will be performed. High-priority processing can be interrupted during the processing in the specified order.

(Third Embodiment) Next, a third embodiment will be described. The second embodiment is an embodiment of the periodic communication processing device 160 for processing the data input from the periodic processing target 3 without the intervention of the CPU 102 in accordance with the periodic processing and storing the data in a predetermined area. .

FIG. 14 shows an example of the configuration of the periodic communication processing device 160 of this embodiment. The data processing unit 1 of this embodiment uses the CP
U102, CPU RAM 103, CPU ROM
And a periodic communication processing device 160. CPU
102, RAM 103, and ROM 104 are a CPU
It is connected to the periodic communication processing device 160 via the bus 106, and is further connected to the communication bus 2 via the periodic communication processing device 160.

The periodic communication processing device 160 of this embodiment comprises an arithmetic unit 166 and a memory 165. Calculation unit 166
Is a CPU communication control unit 164 and a bus communication control unit 163.
And a distribution processing unit 162 and three individual processing units (an individual processing unit A171, an individual processing unit B172, an individual processing unit C1.
73) and. The CPU bus 106 is C
The communication bus 2 is connected to the PU communication control unit 164.
Are connected to the bus communication control unit 163.

The number of individual processing units is not limited to three, and is provided for each individual processing depending on the type of individual processing to be executed on the data read from the periodic processing target 3. In this embodiment, as shown in FIG.
171 is an arithmetic addition process for adding input data to the previous processing result, an individual processing unit B172 is a logical addition process for obtaining a logical sum of the previous processing result and the input data, and an individual processing unit C173 is a previous processing result. It is predetermined to perform a process of obtaining a logical product of the input data and the input data.

The memory 165 holds the input data attribute table 161 in which the distribution destination of the input data and the storage destination of the processing result are registered in advance. The contents of the input data attribute table 161 are registered and updated by the CPU 102 via the CPU communication control unit 164.

The memory 165 may be provided outside the periodic communication processing device 160 as a bus control RAM connected to the periodic communication processing device 160 via the CPU communication control unit 164. In this case, the CPU communication control unit 164 exchanges data in the memory 165 by the arithmetic unit 166.
Through. By providing the bus control RAM in this way, the periodic communication processing device 100 can be realized as an LSI regardless of the restrictions on the memory capacity. The input data attribute table 161 is, as shown in FIG. 6, an input data identifier storage area 1 for holding an identifier of input data.
81, a distribution destination address storage area 182 for holding the address of the individual processing unit of the data distribution destination, and a storage destination address storage area 183 for storing the address of the processing result by the individual processing unit.

Further, the periodic communication processing device 160 of the present embodiment.
Includes RAMs 176 to 178 for storing calculation results.
Is prepared. This calculation result storage RAM 176-
178 is connected to the CPU communication control unit 164.
Further, the CPU 102 can refer to the information held in the calculation result storage RAMs 176 to 178 via the CPU communication control unit 164. In this embodiment, the calculation result storage RAMs 176 to 178 are respectively provided in the individual processing units A.
171, the individual processing unit B172, and the individual processing unit C173. The processing result of the individual processing unit A171 is stored in the calculation result storage RAMs 176 to 178, and the processing result of the individual processing unit B172 is stored in the calculation result storage RAMs 176 to 178. The processing result of the individual processing unit C173 is the calculation result storage RAM1.
76 to 178, respectively.

In this embodiment, the CPU 102 periodically executes the reading process and the writing process on the periodic processing target 3. If the read process is performed, the CPU 102 processes the read data.
However, the periodic communication processing device 160 processes according to the contents of the input data attribute table 161 registered in advance. In this way, the CPU 102
Can execute the interrupt processing for the periodic processing without waiting for the response from the periodic processing target 3 after executing the reading and writing by the periodic processing.
The load on 102 can be reduced.

The distribution processing unit 162 of this embodiment receives the input data from the bus communication control unit 164, determines the individual processing unit for processing the data according to the contents of the input data attribute table 161 registered in advance, and The individual processing unit is notified of the input data and the storage location of the processing result. The bus communication control unit 164 of this embodiment notifies the distribution processing unit 162 of the data transferred from the cyclic processing target 3 via the communication bus 2 and the address of the transfer source of the data. The processing of the distribution processing unit 162 is activated by the transfer of data from the bus communication control unit 163.

FIG. 1 shows the flow of processing of the distribution processing unit 162.
3 shows. First, the distribution processing unit 162 determines the input data identifier based on the transfer source address notified from the bus communication control unit 163 (step 1301). Next, the distribution processing unit 162 searches the input data attribute table 161 based on the determined input data identifier, and allocates the input data identifier storage area 181 to the distribution destination address storage area of the item holding the input data identifier. 1
82 and the storage destination address storage area 183 are read (step 1302). Finally, the distribution processing unit 162
Indicates an address read from the allocation destination address storage area 182 (this address indicates a predetermined individual processing unit (any of 171 to 173)),
Input data and read storage destination address storage area 18
3 is transferred (step 1303), and the process is terminated.

In step 1303, the transferred individual processing unit performs a predetermined process on the transferred input data, and outputs the result to the address held in the transferred storage destination address storage area 183. , CPU
It is stored via the communication control unit 164.

FIG. 6 shows an operation example of the distribution processing section 162 of this embodiment. Here, the input data 301 to
The input data transferred from the address corresponding to the identifier of 310 is transferred from the bus communication control unit 163 to the distribution processing unit 1
The case where the data is input to 62 will be described as an example. In this embodiment, the addresses of the distribution destinations of the input data 301 to 310 are the input data 301, 302, 307, and 310, the individual processing unit A171, and the input data 304, 305, and 309.
Is the individual processing unit B172 and the input data 303, 306,
308 are defined in the individual processing unit C173 and the input data attribute table 161 respectively.

The input data are obtained in step 130, respectively.
In step 1, the distribution processing unit 162 determines that the identifier is the input data 301 to 310, and in step 1302, the transfer destination and storage address are read from the input data attribute table 161.
In 303, input data 301, 302, 307,
Reference numeral 310 denotes the input data 304, 3
05 and 309 are input data 30 to the individual processing unit B172.
3, 306, and 308 are transferred to the individual processing unit C173, respectively.

The input data 301, 302, 307, and 310 distributed to the individual processing unit A171 are respectively stored in the addresses 321 and 322 in the calculation result storage RAM 176.
The arithmetic results are subjected to arithmetic addition processing with the values held in 327 and 330, and the arithmetic results are respectively stored in the arithmetic result storage RAM 17
6 are stored at addresses 321, 322, 327, and 330. The input data 304, 305, and 309 distributed to the individual processing unit B172 are RAMs for storing calculation results, respectively.
177, the logical addition processing with the values held in the addresses 324, 325, and 329 in 177 is performed, and the calculation result is calculated as the address 32 in the calculation result storage RAM storage area 177.
4, 325, 329. Individual processing unit C173
The input data 303, 306, and 308 assigned to each are assigned to the address 323 in the calculation result storage RAM 178,
After undergoing logical integration processing with the values held in 326 and 328, the operation results are stored in addresses 323, 326 and 328 in the operation result storage RAM storage area 178, respectively.

In the present embodiment, the issuance of the periodic processing is C
Although executed by the PU 102, the periodic communication processing device 100 according to the first embodiment may also issue the periodic processing independently of the CPU 102.

(Fourth Embodiment) Next, a fourth embodiment will be described. The periodic communication processing device according to the present embodiment includes a CPU 10
It is a device that autonomously performs a registered periodic process without inputting / outputting data to and from the data, and further executes and outputs a predetermined process for the data read by the periodic process. The configuration of the periodic communication processing device of the fourth embodiment is shown in FIG. The periodic communication processing device 200 of this embodiment is
The arithmetic unit 209, the memory 208, and the input / output unit 211 are provided.

The arithmetic unit 209 is a bus communication control unit 202.
An arbitration unit 210, a scanning unit selector 204, three cycle counters 101, three cyclic table scanning units 107, a distribution processing unit 203, a table selector 207, and three individual processing units 205. . The bus communication control unit 202 is connected to the communication bus 2. Note that the number of cycle counters 101 is not limited to three, and as many cycles as the cycle processing to be executed are prepared. Further, the cyclic table scanning unit 107 uses the cycle counter 101.
Will be prepared. The number of individual processing units 205 is not limited to three, and may be prepared according to the type of individual processing to be executed.

The memory 208 includes three cyclic tables 111a to 111c, a standby list 112, a priority holding unit 113, and three individual processing tables 201a to 201c.
And three result storage areas 206. Note that the result storage areas are prepared as many as the individual processing units 205. Further, the cyclic tables 111a to 111c are prepared as many as the cyclic table scanning units 107. Further, in this embodiment, the individual processing tables 201a to 201c are prepared by the number of the cyclic tables 111. In the individual process tables 201a to 201c, among the periodic processes registered in the corresponding cyclic tables 111a to 111c, respectively,
The address of the individual processing unit 205 that processes the data read by the reading process and the address that stores the processing result are registered in the processing order (that is, in the same order as the reading cycle processing registered in the cyclic table). In this embodiment, the individual processing hand table 201a is the cyclic table 111a, and the individual processing hand table 201b is the cyclic table 111b.
In addition, the individual processing table 201c corresponds to the cyclic table 111c.

The input / output unit 211 of this embodiment includes a keyboard, a print output device, and a screen display device, and receives registration and update of the priority holding unit 113, the cyclic table 111, and the individual processing table 201. ,Run. In addition, the contents of the result storage area 206 are referred to and output according to the input. Further, the executed cycle process may be output by monitoring the bus communication control unit 202. In addition, the individual processing unit 205 uses the result storage area 206.
When the processing result is stored in the
1 is also notified, and when the processing result satisfies a predetermined condition, the input / output unit 211 outputs C
You may make it notify this to PU102.

Each component of the periodic communication processing device 200 of this embodiment includes a functional block 241 for issuing periodic processing,
It can be roughly divided into a functional block 242 that processes data read by the periodic processing and a functional block (not shown) related to input / output.

The functional blocks relating to input / output include a bus communication control unit 202 and an input / output unit 211. The bus communication control unit 202 creates a cyclic processing command based on the cyclic processing information transferred from the scanning unit selector 204, and issues it to the communication bus 2. In addition, the bus communication control unit 2
02 transfers the data transferred via the communication bus 2 to the distribution processing unit 203. Input / output unit 211
Receives an input, and executes a processing start instruction and a processing end instruction to the arbitration unit 210, registration and update of data in the memory 208, reference and output of a processing result, and the like in response to the input.

The function block 241 which issues the periodic process includes the arbitration unit 210, the scanning unit selector 204, the period counter 101, the cyclic table scanning unit 107, the priority order holding unit 113, the waiting list 112, and the cyclic tables 111a to 111a. b is included. The operation of each of these components is the same as in the first embodiment. That is, the cyclic table scanning unit 107 requests the arbitration unit 210 to connect the bus in response to the cyclic activation request issued by the cycle counter 101, and the arbitration unit 210 causes the cyclic table scanning unit 107 to respond to the request. Register in the waiting list 112. Further, the arbitration unit 210 detects the one having the highest priority among the cyclic table scanning units 107 registered in the waiting list 112 based on the priority holding unit 113, and the cyclic table scanning unit 107.
To the bus communication control unit 202 to instruct the scanning unit selector 204 (corresponding to the selector 121 of the first embodiment) to connect the bus to the cyclic table scanning unit 107.
To notify. Upon receiving this notification, the cyclic table scanning unit 107 reads the cyclic processing information registered in the cyclic table in the order in which it is registered, and transfers it to the bus communication control unit 202.

The arbitration unit 210 of the fourth embodiment also includes a selector control unit and a standby list registration unit, as in the first embodiment. However, the selector control unit of the arbitration unit 210 of the fourth embodiment differs from the selector control unit 142 of the first embodiment in that the table selector 207 determines the individual processing table to be connected to the distribution processing unit 203 and its connection. The difference is that it further includes means for instructing the table selector 207.

The selector control unit of the arbitration unit 210 according to the fourth embodiment, when instructing the scanning unit selector 204 to connect the bus, also connects the table selector with the data bus connected to the distribution processing unit 203. To connect. At this time, the selector control unit of the present embodiment corresponds in advance to the cyclic table scanning unit 107 for which the selector control unit has instructed the scanning unit selector 204 to connect to the individual processing table connected to the distribution processing unit 203. The assigned individual processing table is assigned to the distribution processing unit 203.
It is decided as an individual processing table to be connected with. That is, in this embodiment, when the cyclic table scanning unit 107 connected to the cyclic table 111a is connected to the bus communication control unit 202, the individual processing table 2
01a is connected to the distribution processing unit 203. When the cyclic table scanning unit 107 connected to the cyclic table 111b is connected to the bus communication control unit 202, the individual processing table 201b is connected to the distribution processing unit 203 and is connected to the cyclic table 111c. When the cyclic table scanning unit 107 is connected to the bus communication control unit 202, the individual processing table 201c is connected to the distribution processing unit 203.

The function block 242 for processing the data read by the periodic processing includes a distribution processing unit 203.
A table selector 207, an individual processing unit 205,
Result storage area 206 and individual processing tables 201a-2
01c is included. The operations of the distribution processing unit 203, the individual processing unit 205, and the result storage area 206 (corresponding to the calculation result storage RAMs 176 to 178 of the third embodiment) are the same as those of the third embodiment. However, the distribution processing unit 2
Reference numeral 03 denotes an individual process for transferring data by sequentially referring to the information registered in the individual process table (any of 201a to 201c) connected by the table selector 207 without determining the identifier of the input data. This is different from the third embodiment in that the unit 205 and the address for storing the processing result are determined.

According to the cyclic communication processing device 200 of this embodiment, it is possible to execute the cyclic process registered in advance according to the cycle without imposing a load on the CPU 102, and further, the data read by the executed cyclic process. This process can also be executed without imposing any load on the CPU 102.

[0069]

According to the present invention, it is possible to reduce the load on the CPU due to the execution of the periodic processing and improve the throughput of the CPU.

[Brief description of drawings]

FIG. 1 is an explanatory diagram illustrating a bus system according to a first embodiment.

FIG. 2 is an explanatory diagram showing an example of a bus system to which the present invention is applied.

FIG. 3 is an explanatory diagram showing a configuration of a cyclic table according to an embodiment.

FIG. 4 is an explanatory diagram illustrating a configuration of an arbitration unit according to the first embodiment.

FIG. 5 is a time chart of arbitration processing in the first embodiment.

FIG. 6 is an explanatory diagram showing the structure and operation of an input data attribute table in the third embodiment.

FIG. 7 is an explanatory diagram illustrating a configuration of a periodic communication processing device according to a fourth embodiment.

FIG. 8 is an explanatory diagram showing a configuration of the periodic communication processing device according to the first embodiment.

FIG. 9 is a flowchart showing the processing of the cyclic table scanning unit according to the first embodiment.

FIG. 10 is a flowchart showing processing of a waiting list registration unit of the arbitration unit according to the first embodiment.

FIG. 11 is a flowchart showing the processing of the selector control unit of the arbitration unit according to the first embodiment.

FIG. 12 is a flowchart showing the processing of the cyclic table scanning unit according to the second embodiment.

FIG. 13 is a flowchart showing the processing of a distribution processing unit according to the third embodiment.

FIG. 14 is an explanatory diagram illustrating a configuration of a periodic communication processing device according to a third embodiment.

[Explanation of symbols]

1 ... Data processing unit, 2 ... Communication bus, 3 ... Data transfer target, 101 ... Cycle counter, 102 ... CPU,
103 ... CPU RAM, 104 ... CPU RO
M, 106 ... CPU bus, 107 ... Cyclic table scanning unit, 108 ... Memory, 109 ... Arithmetic unit,
110 ... Periodic activation request signal, 111 ... Cyclic table, 112 ... Standby list, 113 ... Priority holding unit, 121 ... Selector, 122 ... Arbitration unit, 12
3 ... Bus communication control unit, 124 ... CPU communication control unit,
132 ... Access target ID storage area, 133 ... Data transfer start address storage area, 134 ... Processing type storage area, 135 ... Access size storage area, 136 ... Access data storage area, 137 ... Data transfer target area size, 138 ... Data Transfer target area, 139 ...
Data transfer start position, 141 ... Data bus for periodic processing information, 142 ... Selector control section, 143 ... Standby list registration section, 145 ... Communication output section identifier storage area, 1
46 ... Priority storage area, 147 ... Bus connection, 15
1-153 ... Cyclic processing, 154-156 ... Cyclic table start interruption, 160 ... Cyclic communication processing device,
161 ... Input data attribute table, 162 ... Distribution processing unit, 163 ... Bus communication control unit, 164 ... CPU communication control unit, 165 ... Memory, 166 ... Arithmetic unit, 17
1 ... Individual processing unit A (for arithmetic addition), 172 ... Individual processing unit B (for logical addition), 173 ... Individual processing unit C (for logical integration), 176 to 178 ... RAM for storing operation result, 1
81 ... Input data identifier storage area, 182 ... Allocation destination address storage area, 183 ... Storage destination address storage area, 201a-c ... Individual processing table, 202 ... Bus communication control unit, 203 ... Allocation processing unit, 204 ...
Scan unit selector, 205 ... Individual processing unit, 206 ... Result storage area, 207 ... Table selector, 208 ...
Memory, 209 ... Arithmetic unit, 210 ... Arbitration unit, 21
1 ... I / O unit, 241 ... Periodic processing issue block, 2
42 ... Input data processing block.

Claims (6)

[Claims] 1. An arithmetic unit and a memory, which are connected to at least one periodic processing target via a communication bus, and predetermined data transfer to the periodic processing target at a predetermined cycle. In the cyclic communication processing device that repeatedly executes processing, the memory stores at least one cyclic table in which cyclic processing information, which is information of one or more data transfer processing, is registered in advance and a bus connection request. And a standby list which is a storage area of the bus communication control unit, the arithmetic unit having a bus communication control unit, a cycle counter, a cyclic table scanning unit, a scanning unit selector, and an arbitration unit. The unit receives the transfer of the cyclic processing information, and based on the received cyclic processing information, sets the cyclic processing target specified by the cyclic processing information to the cyclic processing target. The cyclic counter comprises means for executing a data transfer process specified by the cyclic process information, and the cycle counter comprises at least one means for issuing a cyclic process activation request at a predetermined cycle. The table scanning unit issues means for issuing a bus connection request to the arbitration unit in response to the periodic process activation request of the period counter, and the cyclic table in the cyclic table in response to the bus connection notification from the arbitration unit. Means for reading the registered periodic processing information and transferring the periodic processing information to the bus communication control section, wherein the arbitration section registers the standby list with a standby list registration section and the scanning section selector. And a selector control unit for controlling the above, wherein the standby list registration unit responds to the bus connection request from the cyclic table scanning unit. The selector control unit includes means for registering the cyclic table scanning unit that has issued the request in the standby list, and the selector control unit determines any one of the cyclic table scanning units registered in the standby list as a connection target. Connection means determining means, means for instructing the scanning section selector to connect the cyclic table scanning section to be connected and the bus communication control section, wherein the scanning section selector is the selector In response to an instruction from the control unit, the instructed cyclic table scanning unit,
A periodic communication processing device comprising means for connecting to the bus communication control unit. 2. The connection target determining means according to claim 1, further comprising means for determining, as the connection target, one of the cyclic table scanning units registered in the waiting list, which has the highest priority. A characteristic periodic communication processing device. 3. The cyclic processing information according to claim 1, wherein the data transfer target identifier, a data transfer start address, a processing type indicating whether the data transfer processing is read or write, and data to be transferred. And a periodic communication processing device. 4. The arithmetic unit according to claim 1, wherein the arithmetic unit performs at least one individual processing unit that performs predetermined processing on the input data, and the data read by the data transfer processing by the individual processing unit. The memory further includes a distribution processing unit that distributes the data to the processing unit, and the memory has a distribution destination of the data read by the data transfer processing and a position in a storage area that stores a processing result of the data by the distribution destination. An individual processing table to be held and a storage area for the processing result are further included, and the individual processing unit performs predetermined processing on the input data, and stores the processing result in the storage area for the processing result. Has a means for storing it at a position designated by the input of, and the distribution processing unit refers to the individual processing table to perform the data transfer processing. Ri read data determines the individual processing unit for processing, periodic communication processing device characterized by having means for transferring the data to the individual specific processing sections. 5. The individual processing table according to claim 4, wherein a plurality of the individual processing tables are provided, and the arithmetic unit includes means for connecting a designated one of the plurality of individual processing tables to the distribution processing unit. The selector control unit further includes: an individual processing table determining unit that determines the individual processing table connected to the distribution processing unit; and a connection between the determined individual processing table and the distribution processing unit. A periodic communication processing device, further comprising means for instructing a table selector. 6. The individual processing table determining means according to claim 5, wherein the individual processing table determined in advance as the one corresponding to the cyclic table scanning unit which is the connection target by the connection target determining means. A periodic communication processing device, comprising means for determining as an individual processing table connected to the distribution processing unit.