JPH0720967Y2 - Ground isolation circuit - Google Patents

Description

[Detailed description of the device]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ground isolation circuit that prevents a low-frequency component of the ground level of a power supply from changing to an output side in response to an input signal. It is an object of the present invention, in particular, to secure a high dynamic range and maintain good distortion characteristics while shortening the stabilization time of an output signal at power-on.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a conventional ground isolation circuit. This figure (A) shows a ground isolation circuit using a PNP transistor. The configuration of this figure will be described. This figure shows a capacitor 100 connected between the power supply and the input ground (GND) terminal, a capacitor 101 for receiving one of the input signals, and a capacitor 100 for receiving the input signal.
The other of 1 and a resistor 102, the other of which is connected to the power supply,
A resistor 103, one of which is connected to the other of the resistors 102 and the other of which is connected to the input ground terminal, and a PNP transistor 105 whose base is connected between the resistors 102 and 103.
A resistor 106, one of which is connected to the power supply and connected to the emitter of the PNP transistor 105, one of which is connected to the collector of the PNP transistor 105, and the base of which is connected to the PNP transistor 105. An NPN transistor 108 connected to the collector and having its collector connected to the power supply, and one of which is connected to the emitter of the NPN transistor 108 and the other of which is connected to the resistor 10
A resistor 109 connected to the other of 7 and to the output ground (GND) terminal, and a capacitor 110 having one connected to the emitter of the NPN transistor 108 and the other connected to the output terminal.

The operation of the ground isolation circuit of the PNP transistor has the advantage that the time until the output signal stabilizes after the power is turned on is short.
The bias voltage of the PN transistor 108 cannot be freely set, the dynamic range is low, and the signal level cannot be increased. Further, feedback cannot be obtained, and the distortion factor characteristic must be improved without depending on the transistor characteristic. It had the drawback of not being able to.

FIG. 1B is a diagram showing a ground isolation circuit using a differential amplifier, which is a modification of the defect of FIG. 1A. In the configuration of this figure (B), a buffer amplifier 120 and a differential amplifier 121, which are respectively connected between a power supply and an input ground, are supplied with power and whose output is feedback-connected to an inverting input terminal, and one of which is A capacitor 122, which is connected to the input and the other of which is connected to the non-inverting input terminal of the buffer amplifier 120, and one of which is connected to the output of the buffer amplifier 1 and which is the other of
Of the differential amplifier 121, one of which is connected to the inverting input terminal of the differential amplifier 121 and the other of which is connected to the output of the differential amplifier 121. A resistor connected to the non-inverting input terminal of the 121
125, one of which is connected to the power supply and the other of which is a resistor 12
5, a resistor 126 connected to the other side, a voltage regulator diode 127 whose anode is connected to the input ground and whose cathode is connected to the other side of the resistor 126, and one of which is connected to the non-inverting input terminal of the buffer amplifier 120. Resistor 128 connected between resistor 126 and the zener diode, and capacitor 129 connected to the other of resistor 128 and the other to input ground And a resistor 130 connected to the non-inverting input terminal of the differential amplifier 121 and one connected to the output of the differential amplifier 121. And the other one is the output 132 and the other one is connected to the other of the resistor 131 and the other one is the output ground (GND)
3 and are included. Here the resistors 123, 124, 125 and 13
If the resistances of ₁ are R ₁ , R ₂ , R ₃ and R ₄ , respectively, then R ₁ = R ₂ = R ₃ = R ₄ . Thus resistance 12
6 and the constant voltage diode 127 form a bias circuit for the buffer amplifier 120 and the differential amplifier 121, and the resistor 124 feeds the feedback circuit back to the differential amplifier 121. Therefore, distortion is compared with the configuration of this figure ( A ). The rate is improved.

[0005]

However, as described above, the ground isolation circuit using the conventional differential amplifier has a high dynamic range and can further improve distortion. There was a problem that it took a very long time to stabilize. Especially CD (Compact Disk), DAT (Digital Aud)
In order to support digital sources such as io Tape), not only a high dynamic range and good distortion characteristics but also the time for the signal output to stabilize after the power is turned on is short (within 2 to 3 seconds).
Is required.

Next, in FIG. 6B for explaining the operation until the output signal stabilizes after the power is turned on, R ₁ = R ₂ = R ₃ = R ₄
Therefore, 1 / jwC ₃ ?? in the audible frequency band
R ₄ , Z _D1 / (1 + jwC ₄ Z _D1 ) ?? R ₃ (Z _D1 : internal impedance of constant voltage diode 127), buffer amplifier 120
Requirements ground isolation is formed as the output impedance ?? R _1.

Next, the change in output when the power is changed from OFF to ON will be described with reference to FIG. FIG. 7 shows FIG. 6 (B).
3 is a time chart for explaining the operation of the ground isolation circuit using the differential amplifier of FIG. This figure (a) shows the voltage waveform V _B1 across the capacitor 129, which is formed by the resistor 126 and the constant voltage diode 127, and becomes the respective bias voltages at the non-inverting terminals of the buffer amplifier 120 and the differential amplifier 121. The voltage V _cc represents the supply voltage between the power supply and the input ground.

FIG. 1B shows a voltage waveform V _f between the non-inverting terminal of the differential amplifier 121 and the input ground. This figure (c) is a voltage waveform input to the inverting terminal of the differential amplifier 121 and shows the voltage between one of the resistors 123 and the input ground. This figure (d)
Is the output voltage waveform V ₀ with respect to the input ground with the differential amplifier 121.
Indicates.

FIG. 3E shows the voltage waveform e ₀ between the output sides of the capacitors 132 and 133. Generally a capacitor 133
It is necessary that the capacity C ₃ of C is large. On the other hand, Z _D1
Is small, and the capacitance C _{4 of the} capacitor 129 may be relatively small. Therefore, if the power is immediately turned on,
As shown in (a), the bias power supply V _B1 rises relatively quickly. However, since the capacitance C ₃ of the capacitor 133 is large, it takes a long time to charge the capacitor 133 (time constant C ₃ (R ₃ + R ₄ + R ₅ )), and the voltage of the non-inverting terminal of the differential amplifier 121 becomes constant. Up to td ₁ is required for a long time as shown in FIG.

On the other hand, the time required for the output of the differential amplifier 121 to fluctuate as shown in FIGS. 7 (d) and 7 (e) and for the output e ₀ to stabilize (until e ₀ settles at 0). Therefore, in view of the above problems, it is an object of the present invention to provide a ground isolation circuit for shortening the unstable time at power-on while maintaining high dynamic and good distortion characteristics.

[0011]

FIG. 1 is a diagram showing the principle configuration of the present invention. In order to solve the above problems, the present invention has a second bias circuit 4 in the ground isolation circuit. Second bias circuit 4 is connected with a power source and a high impedance, connected across the capacitor 3 between the first bias circuit 2, the first bias circuit 2
The same bias voltage as that of the input bias voltage is supplied to the capacitor 3.

[0012]

[Action] In Figure 1, first is connected between the input ground According if power and ground isolation circuit of the present invention 1
Is the bias circuit 2 is input bias voltage of the differential amplifier circuit 1 formed, DC voltage of the bias circuit 2 of the first is blocked by the capacitor 3 is connected with power supply and high impedance, the first bias circuit A second bias circuit 4 connected between the capacitor 2 and
As a result, the bias voltage which is substantially the same as the input bias voltage of the first bias circuit 2 is supplied to the capacitor 3, so that the charging of the capacitor 3 can be reduced when the power is turned on. The period of voltage fluctuation between the output and the output ground and the voltage fluctuation of the output ground can be shortened.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a ground isolation circuit according to the first embodiment of the present invention. The structure of the ground isolation according to the first embodiment will be described. The configuration of this figure (A) is provided so as to be connected between the power supply and the input ground (GND) at the connection ends E and F, and the differential amplifier circuit 1 connected to the input at the connection end A, the power supply and the input. ground
A first bias circuit 2 which is provided between (GND) and is output to the connection end B of the differential amplification circuit 1, a capacitor 3 of which one is connected to the connection end D of the differential amplification circuit 1, and a capacitor A second bias circuit 4 which is connected to the other of 3 and connected between the power supply and the output ground (GND).

The differential amplifier circuit 1 is supplied with electric power from the connection terminals E and F, and outputs a differential amplifier 10 via the connection terminal C. One of the differential amplifiers 10 is connected to the connection terminal A and the other is differential. A resistor 11 connected to the inverting input terminal of the amplifier 10, a resistor 12 connected between the output of the differential amplifier 10 and the inverting input terminal, and a connection between the connection terminal B and the non-inverting terminal of the differential amplifier 10. It includes a resistor 13 and a resistor 14 connected between the connection terminal D and the non-inverting terminal of the differential amplifier 10.

The first bias circuit 2 has resistors 21 and 22 connected in series between a power supply and an input ground, and a resistor 23 having one of them connected between the resistors 21 and 22 and the other connected to a connection terminal B. Including and The second bias 4 includes resistors 41 and 42 connected in series between the power supply and the output ground, and a resistor 43, one of which is connected between the resistors 41 and 42 and the other of which is connected to the other of the capacitors C _13. Including.

FIG. 3B shows a differential amplifier circuit 1-1 which is a modification of this FIG. In this circuit 1-1, the differential amplifier 10-1 swaps the inverting and non-inverting input terminals of the differential amplifier 10, switches the other connection of the resistor 12 from the connection terminal C to D, and further connects the other end of the resistor 14. Connection end D
To C, and has substantially the same configuration as the differential amplifier circuit 10.

If the resistance values of the resistors 11, 12, 13 and 14 are R11, R12, R13 and R14, respectively, then R11 / R
It is necessary that 12 = R13 / R14. Also, resistors 21, 2
RB21, RB21, RB23, RB4 resistance of 2, 23, 41, 42 and 43
1, RB42 and RB43, RB21 + RB23 ?? R13, RB41
+ RB43 ?? R14, RB41 ?? RB42, RB42 ?? ZP are required. ZP is a power source impedance. The terminal E of the differential amplifier circuit 1 is a positive power supply terminal, and the terminal F is a negative power supply terminal. The capacity C ₃ of the capacitor ₃ is usually 100 to 220 μm.
It is F.

Next, the operation of this embodiment will be described. FIG. 3 is a time chart for explaining the operation of FIG. The figure (a) shows the power supply voltage waveform V _cc and the first bias voltage waveform V _B1 , and the figure (b) shows the second bias voltage waveform V
_B2 shows the voltage waveform V _f of the non-inverting terminal of the differential amplifier 10, FIG. 7C shows the input voltage V _in to the inverting terminal of the differential amplifier 10, and FIG. (E) is a differential amplifier 10
Shows the voltage waveform V ₀ of the output terminal, and FIG. 6 (f) shows the voltage waveform e _{0 of} only the AC component between the output of the differential amplifier 10 and the output ground.

The feature of this embodiment is that the second bias circuit 4 is provided at the output ground side terminal of the capacitor 3 as compared with the conventional circuit shown in FIG. 6B. Since the second bias voltage V _B2 shown in FIG. 3B is generated with respect to the first bias voltage V _B1 shown in FIG. Terminal voltage waveform V
_{The f} rises faster as shown in FIG. Therefore, with respect to the input voltage waveform V _in of the differential amplifier of this figure (d), only the AC component between the output terminal voltage waveform V _{0 of} this figure (e) and the differential amplifier 10, the output terminal of this figure (f) is shown. The fluctuation time of the voltage waveform e ₀ is extremely short.

Since the internal impedance of the second bias circuit 4 has a relation of RB41 + RB43 ?? R14, the voltage drop of the vehicle noise signal flowing between the input ground terminal and the output ground terminal due to this can be ignored. Furthermore, since it is RB42? ZP, this signal is prevented from flowing out to the power supply side. In addition, the bias voltages V _B1 and V _{B2 of} the first and second bias circuits
Are made substantially equal to each other, the charging of the capacitor 13 is reduced, and the rise of the voltage waveform V _f at the non-inverting terminal of the differential amplifier 10 is made steep.

The relation of resistances constituting the differential amplifier circuit 1 is R
Although 11 / R12 = R13 / R14, the above relationship is maintained as RB21 + RB23 ?? R13 for the internal impedance of the first bias circuit 2. The DC voltage output from the terminal D of the differential amplifier circuit 1 and the DC voltage of the bias voltage of the second bias circuit 4 are cut by the capacitor 13. The configurations of the first bias circuit 2, the second bias circuit 4, and the differential amplifier circuit are not limited to those described above. Further resistors 11, 12, 1
It is not always necessary for 3 and 14 to be resistors. Further, it does not have to be composed of a single element. Furthermore the first
The bias voltage values of the bias circuit 2 and the second bias circuit 4 are not particularly specified, and the capacitor 13 may be omitted if the offset or the like does not matter.

FIG. 4 is a diagram showing a ground isolation circuit according to the second embodiment of the present invention. The configuration of this figure differs from that of FIG. 6B in that the second bias circuit 4-
It is 1. The second bias circuit 4-2 has a capacitor 44, one of which is connected to the output side of the capacitor 13 and the other of which is connected to the output ground terminal, and a second bias circuit 4-2, one of which is connected to the power supply and the other of which is the output side of the capacitor 13. Resistor connected to
47 and a constant voltage diode 46 connected in parallel with the capacitor 44.

R11 = R, where R11, R12, R13 and R14 are the resistance values of the resistors 11, 12, 13 and 14 in the figure, respectively.
12 = R13 = R14 and Z _D1 / in the audible frequency band
(1 + jwC ₄ Z _D1 ) ?? R13, 1 / jwC ₁₃ + Z _D2 / (1 + jw
C ₆ Z _D2 )? R14 (Z _D1 ; internal impedance of constant voltage diode 127, Z _D2 : internal impedance of constant voltage diode 46, C ₆ ; capacity of capacitor 44), output impedance of buffer amplifier 1? R11. If so, the configuration of FIG. 4 has the necessary condition to act as ground isolation.

The operation of this circuit also has the characteristics shown in FIG. To explain the features of this circuit, the value of Z _D1 is generally small, and the capacity C _{4 of the} capacitor 129 may be relatively small.
Although the value of Z _D2 is small, the capacitor C ₆ having a capacitance of C ₆ is connected in series with the capacitor 3 having a capacitance of C ₁₃ , so that a capacitor having a relatively large capacitance of C ₆ and C ₃ is required. Normal V
_Since it is difficult to equalize the values of _B1 and V _B2 , a capacitor 13 is inserted as shown in FIG. 4 to prevent the output of the differential amplifier 10 from being offset.

When the power source rises in this state, the bias voltage V _B1 rises relatively quickly with a time constant of C ₄ R ₅ . On the other hand, since the bias voltage V _B2 has a large capacitance C _6, it rises later than V _{B1 with} a time constant of approximately C ₆ R ₇ (see FIGS. 3A and 3B). However, the rising speed of V _B2 can be improved (fastened) by reducing the resistance value R ₇ of the resistor 47. Further, the voltage difference between V _B1 and V _B2 is applied to both ends of the capacitor C ₁₃ , and the potential difference between the two is small, so
Since the degree of charging the electric charge to 13 is small, it is a capacitor.
The time required to charge 13 is short. As a result, the differential amplifier
The non-inverting terminal 10 as shown in FIG. 3 (c), the the variation FIG. 3 (e), the prior art circuit the differential its variation e ₀ is at the output of the amplifier 10 as (f) Short time td ₂ (?? td
It stabilizes at ₁ ).

FIG. 5 is a diagram showing a ground isolation circuit according to the third embodiment of the present invention. The second bias circuit 4-2 differs from that of FIG. 4 in the configuration of this figure. The second bias circuit 4-2 has a capacitor 44, one of which is connected to the output side of the capacitor 3 and the other of which is connected to the output ground terminal, and the emitter of which is connected to the capacitor 3.
An NPN transistor 45 connected to the output side of the NPN transistor 45, the collector of which is connected to the power supply, and a constant voltage diode 46 whose cathode is connected to the base of the NPN transistor 45 and whose anode is connected to the output ground terminal. NP
It includes a resistor 47 connected between the collector and the base of the N-type transistor 45, and a capacitor 48 connected between the base of the NPN-type transistor 45 and the output ground terminal.

As in this embodiment, the second bias circuit 4-
In the case of 2, the NPN transistor 45 is grounded at the base, so the impedance between the opposite input terminal and the output ground of the differential amplifier 10 is low, but the impedance between the power supply and the output ground is large (almost the resistance of the resistor 47). Value R ₇
be equivalent to). Further, characteristics equal to or better than those of the second bias circuit 4-1 of the second embodiment can be expected. For example, in the case of the second embodiment, the larger the capacitances C ₃ and C ₆ , the better the effect of isolation in the low frequency range. Therefore, the capacitance C ₆ needs to be compromised to some extent, and the characteristics must be sacrificed to some extent (the degree of freedom in design is low). On the other hand, in the case of the third embodiment, the isolation effect in the low frequency range is substantially determined by the capacitances C ₃ and C ₆ ,
(The larger C ₃ and C ₆ are, the better). The time from power-on to the stable output is determined by the capacitance C ₇ and the resistance value R ₇ (the smaller C ₇ and R ₇ are the better). Therefore, both characteristics can be determined independently, and a ground isolation circuit with excellent characteristics can be created (the degree of freedom in design is high).

[0028]

As described above, according to the present invention, it is connected to a power source with high impedance, and a capacitor is inserted between the first bias circuit and the first bias circuit so that the input bias voltage of the first bias circuit is almost the same. Since the second bias circuit that supplies the same bias voltage to the capacitor is provided,
Since the charge to the capacitor can be reduced, the unstable period due to the voltage fluctuation at power-on can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a ground isolation circuit according to a first embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of the embodiment of FIG.

FIG. 4 is a diagram showing a ground isolation circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a ground isolation circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a conventional ground isolation circuit.

FIG. 7 is a time chart for explaining the operation of the ground isolation circuit using the differential amplifier of FIG. 6 (B).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Differential amplifier circuit 2 ... 1st bias circuit 3 ... Capacitor 4 ... 2nd bias circuit

Claims (1)

[Scope of utility model registration request] 1. For an input signal of a differential amplifier circuit (1)
Connect a voltage divider resistor between the power supply and input ground to
First bias circuit (2) supplied as a bias voltage
And a bias voltage supplied from the first bias circuit
Output signal of the differential amplifier (1) by cutting off the DC voltage of
A capacitor (3) to form an output ground for
In ground isolation circuits having the
Connect the power supply and the capacitor (3) with a voltage divider resistor
Make the voltage dividing resistor of the high impedance to the capacitor (3)
The accumulated DC voltage should be canceled and this voltage dividing point should be
Setting the output for the output signal of the differential amplifier (1)
A ground isolation circuit comprising two voltage dividing circuits (4) .