JPH0720441A - Driving method of antiferroelectric liquid crystal display - Google Patents

Abstract

PURPOSE:To obtain a display whose flicker is inconspicuous by inverting the polarity of the nonselection voltages of not only scanning electrodes which are selected for interlaced scanning, but unselected scanning electrodes. CONSTITUTION:A scanning-side driving circuit 15 is connected to the scanning electrodes L of an AFLC panel 1 and a signal-side driving circuit 16 is connected to the signal electrodes S. The scanning-side driving circuit 15 is a circuit for impressing the voltage to the scanning electrodes L and consists of a shift register 17a, a latch 18a, and an analog switch array 19a, and an inputted display Y1 is transferred by synchronizing the shift register 17a with a clock CK. In this case, every Nth scanning electrode L is selected for interlaced scanning and the polarity of the voltage impressed to pixels on the scanning electrode L is inverted; when the pixels on the selected scanning electrode L are in a 1st stable state, the pixels are rewritten into a 3rd stable state at the same time and when the pixels are in a 2nd stable state. the stable state is held.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display driving method, and more particularly to a liquid crystal display driving method using an antiferroelectric liquid crystal (hereinafter abbreviated as AFLC).

[0002]

2. Description of the Related Art FIG. 2 is a sectional view showing a schematic structure of an AFLC panel. That is, the two glass substrates 5a and 5b
Are arranged so as to face each other, and a plurality of transparent signal electrodes S made of indium tin oxide (hereinafter abbreviated as ITO) or the like are arranged in parallel with each other on the surface of one glass substrate 5a. It is covered with a transparent insulating film 6a made of SiO ₂ or the like. On the surface of the other glass substrate 5b facing the signal electrode S, a plurality of transparent scanning electrodes L made of ITO or the like are arranged in parallel to each other in a direction orthogonal to the signal electrode S, and SiO ₂ or the like is formed thereon. Is covered with a transparent insulating film 6b. Each insulating film 6a, 6
On b, transparent alignment films 7a and 7b made of polyvinyl alcohol or the like (hereinafter abbreviated as PVA) which have been subjected to a rubbing treatment are formed. After the two glass substrates 5a and 5b are bonded together with a sealant 8 leaving an injection port in part, AFLC 9 is introduced from the injection port into the space sandwiched by the alignment films 7a and 7b by vacuum injection. The injection port is sealed with the sealant 8. The two glass substrates 5a and 5b thus bonded together are sandwiched between the two polarizing plates 10a and 10b arranged so that their polarization axes are orthogonal to each other.

AFLC molecules are ferroelectric liquid crystals (hereinafter referred to as FLC).
Like each molecule, each molecule moves on a cone and has two stable states on the cone. However, the AFLC molecule repeats its two stable states alternately as shown in FIG. 22B when no electric field is applied, but when a positive electric field exceeding a certain threshold is applied, as shown in FIG. 22C. One of the stable states is established, and when a negative electric field exceeding a certain threshold value is applied, the other stable state is established as shown in FIG.

Of the three stable states of this AFLC, FIG.
The upper and lower polarizing plates 10 so that the state of (B) 2 is the darkest.
When a and 10b are combined, the applied voltage-transmitted light amount characteristic of the AFLC panel 1 exhibits a double loop hysteresis characteristic as shown in FIG. Japanese Patent Laid-Open No. 2-153322 and the like are known as a driving method utilizing this characteristic. In addition, the driving method that improved the driving method is Japan Display '
In 92, Yamada et al. "Multi-Color Video-Rate Antifer
roelectric LCDds with High Contrast and WideView
It is announced as ".

FIG. 24 shows a schematic structure of an AFLC display (hereinafter abbreviated as AFLCD) used in these driving methods. AFLCD4 is the AF of FIG.
The scanning side drive circuit 11 is connected to the scanning electrode L of the LC panel 1, and the signal side drive circuit 12 is connected to the signal electrode S. Here, in order to simplify the description, in the case where there are 16 scanning electrodes L and 16 signal electrodes S, that is, 1
The figure shows an AFLCD 4 composed of 6 × 16 pixels, and each scanning electrode L is added to the symbol L with a subscript i (i =
0 to F) are added for distinction, and each of the signal electrodes S is represented by a symbol S.
Are distinguished by adding a subscript j (j = 0 to F). Further, a portion where an arbitrary scanning electrode L _i and an arbitrary signal electrode S _j intersect each other is defined as a pixel and is represented by a symbol A _ij .

The scanning side driving circuit 11 is a circuit for applying a voltage to the scanning electrode L, and is composed of a shift register of a 2-bit structure and an analog switch array (not shown), and the displays YD ₀ and YD ₁ to which it is input are ". The selection voltage V _C0 is applied to the scan electrode L _i corresponding to “0”, and the input data YD ₀ , YD ₁ corresponds to “1”.
_When the non-selection voltage V _C1 is applied to _i , the input data YD ₀ ,
The non-selection voltage V _{C2 is} applied to the scan electrode L _i corresponding to YD ₁ of “2”.
Is applied.

The signal side drive circuit 12 is a circuit for applying a voltage to the signal electrode S, and includes a shift register, a latch and an analog switch (not shown) having a 1-bit structure.
The rewriting bright voltage V _S0 is applied to the signal electrode S corresponding to the input data DATA corresponding to “0”, and the rewriting bright voltage V _S1 is applied to the signal electrode S corresponding to the input data DATA of “1”. .

That is, the signals are input to the drive circuits 11 and 12.
The combination of the drive voltage depends on the voltage of FIG. 25 or 26.
A combination of waveforms is used. That is, the voltage wave of FIG.
V in combination of shapes_C0= V_CA, V_C1= V_CB, V_C2= V
_CF, V_S0= V_SC, V_S1= V_SDAnd the voltage waveform in Figure 26
In combination of V_C0= V_CE, V_C1= V_CB, V_C2=
V _CF, V_S0= V_SG, V_S1= V_SHBecomes

FIG. 27 shows the scanning procedure in this driving method. FIG. 27 shows a voltage waveform to be applied to each scan electrode L _i , A is the (1) selection waveform V _CA of FIG. 25, and B is the (2) non-selection waveform of FIG. 25 or FIG. V _CB
And F is (2) non-selected waveform V in FIG. 25 or FIG.
_CF is E, and E is (1) selection waveform V _CE in FIG.

In order to rewrite the stable state of the AFLC molecules forming the pixel A _ij to the stable state of FIG. 22C, the selection voltage V _CA shown in FIG. 25A is applied to the scan electrode L _i , The rewrite bright voltage V shown in (4) of FIG. 25 is applied to the signal electrode S _j .
Applying _SC to the AFLC molecules that make up pixel A _ij
The voltage waveform AC shown in (6) of 5 is applied. Further, in order to rewrite the stable state of the AFLC molecules constituting the pixel A _ji in Figure 22 to a stable state of (A), FIG to the scanning electrodes L _i 2
By applying the selection voltage V _CE shown in (1) of 6, the signal electrode S _j
To the pixel A by applying the bright voltage V _SG shown in (4) of FIG.
_The voltage waveform EG shown in (6) of FIG. 26 is applied to the AFLC molecule forming _ij .

When the selection voltage V _CA shown in (1) of FIG. 25 is applied to the scan electrode L _i in order to rewrite the stable state of the AFLC molecule forming the pixel A _ij to (B) of FIG. 22, a signal is generated. The rewrite dark voltage V _SD shown in (5) of FIG. 25 is applied to the electrode S _j, and the voltage waveform A-D shown in (7) of FIG. 25 is applied to the AFLC molecules forming the pixel A _ij . Further, when applying a selection voltage V _CE of the scanning electrodes L _i shown in (1) in FIG. 26, by applying the rewriting dark voltage V _SH indicating the signal electrode S _j to (5) in FIG. 26, pixel A _The voltage waveform E-H shown in (7) of FIG. 26 is applied to the AFLC molecule forming _ij .

After applying the selection voltage V _CA to the scan electrodes L _i , the non-selection voltage V shown in (2) of FIG. 25 or FIG.
Figure 2 shows the voltage waveform applied to pixel A _ij when _CB is applied.
(8) B-C or (9) B-D of 5 or (8) of FIG.
The stable state of the pixel is held as BG or (9) BH.

After the selection voltage V _CE is applied to the scan electrode L _i , the non-selection voltage V _CF shown in (3) of FIG. 25 or 26 is applied, and the voltage waveform applied to the pixel A _ij . 25 (10) FC or (11) FD or FIG.
The stable state of the pixel is held as (10) F-G and (11) F-H of 6.

Between the voltage applied to the pixel A _ij in FIGS. 25 and 26 and the voltages V ₁ , V ₂ and V _{3 in} FIG. 23, V _A + V _B ≧ V ₂ (1) V _A −V _B The relationship of ≦ V ₁ (2) V ₀ + V _B ≦ V ₁ (3) V ₀ −V _B ≧ V ₃ (4) is required.

When the AFLCD displaying "ABCD" shown in FIG. 24 actually displays "EBCD" in FIG. 7, the scan electrodes L ₀ , L ₁ , L ₂ , L ₃ and the signal electrodes S ₁ , S are displayed. _The voltage waveform applied to ₂ is as shown in (1) to (6) of FIG. 28, and as a result, the voltage waveform applied to the pixels A ₁₁ , A ₁₂ , A ₂₁ , and A ₂₂ is (7) of FIG. ~ It becomes like (10).

That is, (1) of FIG. 28 shows a voltage waveform applied to the scan electrode L ₀ , which is the selection voltage V in the period of ₀ to 3t _0.
FIG. 28 (2) shows the voltage waveform applied to the scan electrode L ₁ when _CA is applied, and is the selection voltage V _CE during the period of 3t _{0 to} 6t _{0 .}
28 is a voltage waveform applied to the scan electrode L ₂ , and the selection voltage V _CA is applied during the period of 6t _{0 to} 9t _0. (4) of FIG. 28 shows the scan electrode L ₄ The selected voltage V _CE is applied in the period of 9t _{0 to} 12t ₀ .

FIG. 28 (5) shows a voltage waveform applied to the signal voltage S ₁ , and FIG. 28 (6) shows a voltage waveform applied to the signal electrode S ₂ . As a result, the pixel A ₁₁ is displayed in FIG.
The voltage waveform of 9 (7) is applied, the voltage waveform of (8) of FIG. 29 is applied to the pixel A ₁₂ , the voltage waveform of (9) of FIG. 29 is applied to the pixel A ₂₁ , and the pixel A ₂₂ is applied. Is applied with the voltage waveform of (10) in FIG.

[0018]

In this way, the driving method in which the scanning electrodes are sequentially selected from the top to the bottom is composed of AFLC molecules in the display state of FIG. 22A or 22C. The pixel to be displayed is temporarily in the display state of FIG. 22B when a selection voltage is applied, and therefore the amount of transmitted light is different when the pixel in the same bright display state is selected and other times. When the field period (the time required to select from the top to the bottom of the scanning electrode) becomes long, the difference in the amount of transmitted light is recognized as flicker by the human eye.

Therefore, in the conventional driving method, the field frequency must be set to a certain frequency (for example, 30 Hz) or more, and there is a problem that the number of scan electrodes of the AFLCD that can be displayed is limited by the frequency.

The present invention addresses such problems by using FLC.
This is an attempt to solve the problem by using the idea of a driving method that performs partial rewriting driving while performing interlaced scanning performed on a display.

[0021]

According to the present invention, an antiferroelectric liquid crystal having three stable states is interposed between a plurality of scanning electrodes and a plurality of signal electrodes arranged in a direction intersecting with each other. A method for driving an anti-ferroelectric liquid crystal in which the first stable state and the third stable state of the anti-ferroelectric liquid crystal are set to a bright display state and the second stable state is set to a dark display state. An electrode is selected, the polarity of the voltage applied to the pixel on the scan electrode is inverted, and if the pixel on the selected scan electrode is in the first stable state, the pixel is switched to the third stable state, If it is the stable state of, rewrite it to the first stable state, and if it is the second stable state, hold that stable state,
After that, when the scan electrode forming the pixel whose display state is to be changed is selected and the pixel is changed from the dark display state to the bright display state, the antiferroelectric liquid crystal forming the pixel is changed from the second stable state. When the pixel is rewritten to the third stable state or the first stable state and the pixel is changed from the bright display state to the dark display state, the antiferroelectric liquid crystal forming the pixel is changed to the third stable state or the first stable state. Driving method for an anti-ferroelectric liquid crystal display, characterized in that the stable state of the anti-ferroelectric liquid crystal forming the pixel is maintained when the state is rewritten to the second stable state and the display state of the pixel is not changed. Is provided.

Further, the step of selecting the scan electrodes by the interlaced scanning also inverts the polarity of the voltage applied to the pixels on the non-selected scan electrodes, so that the pixels on the selected scan electrodes are first stabilized. It may include a step of transitioning from the state to the third stable state, transition from the third stable state to the first stable state, or holding the second stable state.

Further, according to the present invention, a plurality of scanning electrodes and a plurality of signal electrodes arranged in a direction intersecting with each other are provided between the scanning electrodes and the signal electrodes.
An antiferroelectric liquid crystal having two stable states is interposed, and the first stable state and the third stable state of the antiferroelectric liquid crystal are set to a bright display state, and the second stable state is set to a dark display state. A method of driving an anti-ferroelectric liquid crystal, wherein a scan electrode is selected by interlaced scanning, a polarity of a voltage applied to a pixel on the scan electrode is inverted, and a pixel on the selected scan electrode is set to a first position. If the stable state of is, rewrite to the third stable state,
If it is the third stable state, it is rewritten to the first stable state, and if it is the second stable state, the stable state is held, and thereafter, the scan electrode forming the pixel whose display state is to be changed is selected, and When setting the pixels to a bright display state,
When the antiferroelectric liquid crystal forming the pixel is rewritten to the third stable state or the first stable state and the pixel is brought into the dark display state, the antiferroelectric liquid crystal forming the pixel is changed to the second stable state. The present invention provides a method for driving an antiferroelectric liquid crystal display characterized by rewriting to a state.

The step of selecting the scan electrodes by the interlaced scanning also reverses the polarity of the voltage applied to the pixels on the non-selected scan electrodes, and the pixels on the selected scan electrodes are first stabilized. It may include a step of transitioning from the state to the third stable state, transition from the third stable state to the first stable state, or holding the second stable state.

[0025]

[Action]

1) An antiferroelectric liquid crystal display is constructed by sandwiching an antiferroelectric liquid crystal panel between polarizing plates having polarization axes orthogonal to each other. The antiferroelectric liquid crystal panel is constructed by interposing antiferroelectric liquid crystal having three stable states between a plurality of scanning electrodes and a plurality of signal electrodes arranged in directions intersecting with each other. If the polarization axis of the polarizing plate and the second stable state of the anti-ferroelectric liquid crystal are made parallel (or orthogonal), the first stable state and the third stable state of the anti-ferroelectric liquid crystal are brought into a bright display state. Therefore, the second stable state can be a dark display state.

The scanning electrodes of such an anti-ferroelectric liquid crystal display are selected by interlaced scanning every N lines (N is an integer of 2 or more), and the polarity of the voltage applied to the pixel on the scanning electrode is inverted. , At the same time, if the pixel on the selected scan electrode is in the first stable state (or the third stable state), rewrite to the third stable state (or the first stable state),
If it is the second stable state, the stable state is maintained.

In the interval between such interlaced scans, if the scan electrode forming the pixel whose display state is to be changed is selected by partial rewriting scanning and that pixel is to be changed from the dark display state to the bright display state, the If it is desired to rewrite the antiferroelectric liquid crystal forming the pixel from the second stable state to the third stable state (or the first stable state) and change the pixel from the bright display state to the dark display state, the pixel The antiferroelectric liquid crystal forming the pixel is rewritten from the third stable state (or the first stable state) to the second stable state, and it is not desired to change the display state of the pixel. An anti-ferroelectric liquid crystal display without flicker can be obtained regardless of the number of scanning electrodes of the anti-ferroelectric liquid crystal panel by driving the dielectric liquid crystal while maintaining the stable state.

2) In the driving method of the above 1), even if the polarity of the voltage applied to the pixel on the scan electrode which is not selected in the interlaced scanning is also inverted, the pixel on the scan electrode is the first stable. If it is in the state (or the third stable state), it transits to the third stable state (or the first stable state), and if it is the second stable state, the stable state is held.

3) The anti-ferroelectric liquid crystal display similar to the above 1) is skipped every N scanning electrodes, and the pixel on the selected scanning electrode is in the first stable state (or the third stable state). For example, the third stable state (or the first stable state)
If the second stable state is maintained, the stable state is maintained, and in the interval between such interlaced scans, the scan electrode forming the pixel whose display state is to be changed is selected by the partial rewriting scan, and the pixel is changed. If it is desired to make the display state brighter, the change in the transmitted light amount due to the partial rewriting scanning cannot be distinguished from the crosstalk even if the antiferroelectric liquid crystal forming the pixel is rewritten to the second stable state. An anti-ferroelectric liquid crystal display in which flicker is not noticeable can be obtained regardless of the number of scanning electrodes of the dielectric liquid crystal panel.

2) In the driving method of the above 1), even if the polarity of the voltage applied to the pixel on the scan electrode which is not selected in the interlaced scanning is also inverted, the pixel on the scan electrode is the first stable. If it is in the state (or the third stable state), it transits to the third stable state (or the first stable state), and if it is the second stable state, the stable state is held.

If a frame frequency f _R that does not cause flicker in sequential scanning on a display having a memory property is f ₀ , a field frequency f _D that does not cause flicker when interlaced scanning of N: 1 is performed on the same display is almost f _0. Becomes That is, if interlaced scanning of N: 1 is performed, the number of scanning electrodes that can be displayed without feeling flicker can be about N times that of sequential scanning.

However, when changing pixels are displayed on a display performing interlaced scanning of N: 1,
The pixels on the scanning electrodes forming the image change every N lines, which is not a preferable display method. Therefore,
If the changing image is rewritten by sequential scanning, and the unchanged image is rewritten by N: 1 interlaced scanning, the changing image can be displayed continuously, and the number of scanning electrodes that does not cause flicker is sequentially scanned. It is possible to obtain a display that can be approximately N times as large as

Further, in order to change the antiferroelectric liquid crystal from the first stable state (or the third stable state) to the second stable state, it is necessary to apply a voltage near Ov for some time. By utilizing this characteristic, if the polarity of the voltage applied to the pixel is rapidly reversed, the first stable state (or the third stable state) changes to the third stable state (or the first stable state). You can let me do it.

Pixels in the second stable state remain in the second stable state even if the polarity of the voltage applied to the pixels is changed. Even if the polarity changes, the dark display state (second stable state) is maintained.

Further, if a part of the pixel is from the first stable state (or the third stable state) to the second stable state, or from the second stable state to the first stable state (or the third stable state). ) Change to a third stable state (or a first stable state) if the pixel should be in a bright display state when the scan electrode forming the pixel is selected by interlaced scanning. If it should be in the dark display state, it is rewritten to the second stable state.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited to this.

Example 1 Since the structure of the AFLC panel used in the present invention is the same as that of the conventional example shown in FIG. 2, its explanation is omitted here. However,
The antiferroelectric liquid crystal material used in this example is TCK-C100 manufactured by Chisso Corporation, and the alignment film is PS manufactured by Chisso Corporation.
It is IA-2101.

The structure of the AFLCD 14 used in the present invention is as shown in the plan view schematically shown in FIG. That is,
The scanning side drive circuit 15 is connected to the scanning electrode L of the AFLC panel 1, and the signal side drive circuit 16 is connected to the signal electrode S.

The scanning side driving circuit 15 is a circuit for applying a voltage to the scanning electrode L, and is composed of a shift register 17a, a latch 18a and an analog switch array 19a, and an input display YI clocks the shift register 17a to a clock CK. Is transferred in synchronization with the latch 18 and the transferred data is latched by the timing pulse LPN.
is held in a, the voltage V _C0 is applied to the scanning electrodes L _i where the held data corresponding to "0", V _C0 is applied to the scanning electrodes L _i corresponding to "1".

The signal side drive circuit 16 is a circuit for applying a voltage to the signal electrode S, and is composed of a shift register 17b, a latch 18b and an analog switch array 19b, and the input data XI receives the input data XI.
Is transferred in synchronization with the clock CK, the transferred data is held in the latch 18b by the timing pulse LPN, and the held data is applied with the voltage V _C0 to the signal electrode S _j corresponding to “0”. V _C0 is applied to the signal electrode S _j corresponding to “1”.

The combination of the drive voltage waveforms input to the drive circuits 15 and 16 is the combination of the voltage waveforms shown in FIG. 10 or FIG. 11 when the interlaced scanning of N: 1 is performed, and when the partial rewriting scanning is performed. It is a combination of the voltage waveforms of FIGS. 14 to 17.

The driving method is as follows: N: 1 interlace scanning is performed using the voltage waveform of FIG. 10, partial rewriting scanning is performed using the voltage waveform of FIG. 14, and partial rewriting scanning is performed using the voltage waveform of FIG. , ..., N: 1 interlace scanning is performed using the voltage waveform of FIG. 11, partial rewriting scanning is performed using the voltage waveform of FIG. 16, and partial rewriting scanning is performed using the voltage waveform of FIG. ............ The procedure is repeated.

In the first N: 1 interlaced scan, selected
Scan electrode L_iTo the selection voltage V shown in (1) of FIG._CR
Applied to the selected scan electrode L_iUpper pixel A_ijMake up
22A shows the stable state of the AFLC molecule that
To the stable state of FIG.
In order to maintain the stable state of (B) of 22, the pixel A _ij
The signal electrode S that constitutes the_jTo non-rewriting shown in (3) of FIG.
Voltage V_SUIs applied to the pixel A_ijTo (5) in Figure 10
Voltage waveform R-U is applied. In addition, the selected scanning voltage
Pole L_iUpper pixel A_ijState of AFLC molecules that make up
In order to rewrite the stable state of FIG.
A_ijThe signal electrode S that constitutes the_jTo the book shown in (4) of Figure 10
Replacement dark voltage V_swIs applied to the pixel A_ijTo FIG. 10 (6)
The voltage waveform RW shown in is applied. Other scan electrodes L
_kFor (k ≠ i), the non-selection voltage V shown in (2) of FIG._cs
Is applied to pixel A_kjThe voltage waveform S shown in (7) of FIG.
-U or the voltage waveform SW shown in (8) of FIG. 10 is applied,
Scan electrode L not selected_kUpper pixel A_kjMake up
Is the stable state of the AFLC molecule the stable state of FIG.
To the stable state of FIG. 22C, or
The stable state of (B) of 22 is maintained. Note that the
The voltage supplied to the AFLCD 4 in the combination of pressure waveforms
Is V _C0= V_CR, V_C1= V_CS, V_S0= V_SU, V_S1= V_SWso
is there.

In the first partial rewriting scan, the selected
Scan electrode L_iTo the selection voltage V shown in (1) of FIG._CAPMark
In addition, the selected scanning electrode L_iUpper pixel A_ijMake up
Is the stable state of the AFLC molecule the stable state of FIG.
Alternatively, in order to maintain the stable state of FIG.
Pixel A_ijThe signal electrode S that constitutes the_jTo (3) in Figure 14
Non-rewriting voltage V_SGPIs applied to the pixel A_ijTo Figure 14
The voltage waveform AP-GP shown in (5) is applied. Also, select
Selected scan electrode L_iUpper pixel A_ijAFLC which constitutes
Rewrite the stable state of the molecule to the stable state of Fig. 22 (B)
Pixel A_ijThe signal electrode S that constitutes the_jTo Figure 14
Rewriting dark voltage V shown in (4) of_SDPIs applied to the pixel A
_ijTo the voltage waveform AP-DP shown in (6) of FIG.
It Other scan electrodes L_k(K ≠ i)
Non-selection voltage V shown in (2)_CSPIs applied to pixel A_kjTo figure
14 (7) voltage waveform BP-GP shown in FIG.
Apply the voltage waveform BP-DP shown in (8) and select
Not scan electrode L_kUpper pixel A_kjAFLC components that make up
The stable state of the child is the stable state of FIG.
The stable state of (B) of 2 is maintained. In addition, the voltage of FIG.
With the combination of waveforms, the voltage supplied to AFLCD4 is
V _C0= V_CAP, V_C1= V_CBP, V_S0= V_SGP, V_S1= V_SDP
Is.

In the second partial rewriting scan, the selected
Scan electrode L_iTo the selection voltage V shown in (1) of FIG._CEPMark
In addition, the selected scanning electrode L_iUpper pixel A_ijMake up
The stable state of the AFLC molecule is changed to the stable state of FIG.
To rewrite, the pixel A _ijThe signal electrode S that constitutes the_j
To rewrite bright voltage V shown in (3) of FIG._SCPIs applied,
Pixel A_ijTo voltage waveform EP-CP shown in (5) of FIG.
Is applied. In addition, the selected scan electrode L_iUpper pixel A
_ij22C shows the stable state of the AFLC molecule constituting the
Or the stable state of FIG. 22B is maintained.
Pixel A_ijThe signal electrode S that constitutes the_jTo Figure 15
Non-rewriting voltage V shown in (4) of_SHPIs applied to the pixel A
_ijTo the voltage waveform EP-HP shown in (6) of FIG.
It Other scan electrodes L_k(K ≠ i)
Non-selection voltage V shown in (2)_CEPIs applied to pixel A_kjTo figure
The voltage waveform FP-CP shown in (7) of FIG.
Apply the voltage waveform FP-HP shown in (8) and select
Not scan electrode L_kUpper pixel A_kjAFLC components that make up
The stable state of the child is the stable state of FIG.
The stable state of (B) of 2 is maintained. In addition, in FIG.
The combination of voltage waveforms in (B) is supplied to the AFLCD 4.
The voltage applied is V_C0= V_CEP, V_C1= V_CFP, V_S0=
V_SHP, V_S1= V_SCPIs.

For the second N: 1 interlace scan, selected
Scan electrode L_iTo the selection voltage V shown in (1) of FIG._CX
Applied to the selected scan electrode L_iUpper pixel A_ijMake up
22C shows the stable state of the AFLC molecule that
To rewrite from Fig.22 (A) to the stable state,
Element A_ijThe signal electrode S that constitutes the_jTo (3) in FIG. 11
Rewriting voltage V_SYIs applied to the pixel A_ijTo Figure 11
The voltage waveform XY shown in (5) is applied. Also selected
Scan electrode L_iUpper pixel A_ijAFLC molecule that constitutes
To keep the stable state of the stable state of FIG.
Or from the stable state of FIG. 22 (C) to that of FIG. 22 (A)
In order to make a transition to a stable state, the pixel A_ijThe beliefs that make up
No. electrode S_jTo the non-rewriting voltage V shown in (4) of FIG._SZ
Is applied to the pixel A_ijTo the voltage wave shown in Fig. 11 (6)
Apply Form X-Z. The combination of voltage waveforms in FIG.
In addition, the voltage supplied to the AFLCD 4 is V _C0= V_CX，
V_C1= V_CT, V_S0= V_SZ, V_S1= V_SYIs.

Selected in the third partial rewriting scan
Scan electrode L_iTo the selection voltage V shown in (1) of FIG._CANMark
In addition, the selected scanning electrode L_iUpper pixel A_ijMake up
Is the stable state of the AFLC molecule the stable state of FIG.
Alternatively, in order to maintain the stable state of FIG.
Pixel A_ijThe signal electrode S that constitutes the_jTo (3) in Fig. 16
Non-rewriting voltage V_SGNIs applied to the pixel A_ijTo Figure 16
The voltage waveform AN-GN shown in (5) is applied. Also, select
Selected scan electrode L_iUpper pixel A_ijAFLC which constitutes
Rewrite the stable state of the molecule to the stable state of Fig. 22 (B)
Pixel A_ijThe signal electrode S that constitutes the_jTo Figure 16
Rewriting dark voltage V shown in (4) of_SDNIs applied to the pixel A
_ijTo the voltage waveform AN-DN shown in (6) of FIG.
It Other scan electrodes L_k(K ≠ i)
Non-selection voltage V shown in (2)_CBNIs applied to pixel A_kjTo figure
The voltage waveform BN-GN shown in (7) of FIG.
Apply the voltage waveform BN-DN shown in (8) and select
Not scan electrode L_kUpper pixel A_kjAFLC components that make up
The stable state of the child is the stable state of FIG.
The stable state of (B) of 2 is maintained. In addition, the voltage of FIG.
With the combination of waveforms, the voltage supplied to AFLCD4 is
V _C0= V_CAN, V_C1= V_CBN, V_S0= V_SGN, V_S1= V_SDN
Is.

Selected in the fourth partial rewriting scan
Scan electrode L_iTo the selection voltage V shown in (1) of FIG._CENMark
In addition, the selected scanning electrode L_iUpper pixel A_ijMake up
The stable state of the AFLC molecule is changed to the stable state of FIG.
To rewrite, the pixel A _ijThe signal electrode S that constitutes the_j
Rewrite bright voltage V shown in (3) of FIG._SCNIs applied,
Pixel A_ijTo voltage waveform EN-CN shown in (5) of FIG.
Is applied. In addition, the selected scan electrode L_iUpper pixel A
_ij22B shows the stable state of the AFLC molecule constituting the
Or the stable state of FIG. 22A is maintained.
Pixel A_ijThe signal electrode S that constitutes the_jTo Figure 17
Non-rewriting voltage V shown in (4) of_SHNIs applied to the pixel A
_ijTo the voltage waveform EN-HN shown in (6) of FIG.
It Other scan electrodes L_k(K ≠ i)
Non-selection voltage V shown in (2)_CFNIs applied to pixel A_kjTo figure
The voltage waveform FN-CN shown in (7) of FIG.
The voltage waveform FN-HN shown in (8) is applied and selected.
Not scanning electrode L_kUpper pixel A_kjAFLC which constitutes
The stable state of the molecule is the stable state of FIG.
22 (B) is held in a stable state. Note that the
The voltage supplied to the AFLCD 4 in the combination of pressure waveforms
Is V _C0= V_CEN,V_C1= V_CFN, V_S1= V_SCNIs.

[0049] At this time, the pixel voltage is applied to the _{A ij V 0, V A,} V B, V C as well as V _A + V and conventional example between the voltage V _1, V _2, V ₃ of FIG. 23 _B ≧ V ₂ (1) _VA −V _B ≦ V ₁ (2) V ₀ + V _B ≦ V ₁ (3) V ₀ −V _B ≧ V ₃ (4) It is necessary to further have a relationship of V _C + V The relationship of _B ≧ V ₃ (5) V _C −V _B ˜0 (6) is also required. Further, instead of the combination of the voltage waveforms of FIGS. 10 and 11, the combination of the voltage waveforms of FIGS. 12 and 13 may be used.

In the combination of voltage waveforms shown in FIG. 12, selection is made.
Scan electrode L_iTo the selection voltage V shown in (1) of FIG.
_CRApplied to the selected scan electrode L_iUpper pixel A_ijConstruct
The stable state of the formed AFLC molecule is shown in FIG.
To rewrite from the state to the stable state of FIG.
Pixel A_ijThe signal electrode S that constitutes the_jTo (3) in Fig. 12
Rewriting voltage V_SUIs applied to the pixel A_ijTo Figure 12
The voltage waveform RU shown in (5) is applied. Also selected
Scan electrode L_iUpper pixel A_ijAFLC molecule that constitutes
To keep the stable state of the stable state of FIG.
Or from the stable state of FIG. 22 (A) to that of FIG. 22 (C)
In order to make a transition to a stable state, the pixel A_ijThe beliefs that make up
No. electrode S_jTo the non-rewriting voltage V shown in (4) of FIG._SWMark
Add the pixel A_ijVoltage waveform R shown in (6) of FIG.
-W is applied. Others are the same as the description of FIG. 10, so
The description is omitted here. The voltage waveform of FIG.
In combination, the voltage supplied to the AFLCD 4 is V _C0=
V_CR, V_C1= V_CS, V_S0= V_SW, V_S1= V_SUIs.

In addition, in the combination of voltage waveforms in FIG.
Selected scan electrode L_iTo the selection voltage shown in (1) of FIG.
V_CXApplied to the selected scan electrode L_iUpper pixel A_ijTo
The stable state of the constituent AFLC molecules is shown in FIG.
If the state is changed to the stable state shown in FIG.
In order to maintain the stable state of FIG.
A_ijThe signal electrode S that constitutes the_jTo the non-shown in (3) of FIG.
Rewriting voltage V_SYIs applied to the pixel A_ijTo Figure 13 (5)
The voltage waveform X-Y shown in FIG. Also the selected run
Inspection electrode L_iUpper pixel A_ijOf AFLC molecules that make up
To rewrite the state to the stable state of FIG.
Pixel A_ijThe signal electrode S that constitutes the_jTo (4) in Fig. 13
Rewriting dark voltage V_SZIs applied to the pixel A_ijTo Figure 13
The voltage waveform X-Z shown in (6) is applied. Others are Figure 1
Since it is the same as the description of 1, the description thereof will be omitted here. Na
The combination of voltage waveforms shown in FIG.
The supplied voltage is V _C0= V_CX, V_C1= V_CT, V_S0=
V_SY, V_S1= V_SZIs.

Many AFLC molecules have an applied voltage of −V ₃ or less (or + V ₃ or more) when in the stable state of FIG. 22A (or the stable state of FIG. 22C). To a voltage of + V ₃ or higher (or a voltage of −V ₃ or lower), the stable state of FIG.
(C) stable state) changes to the stable state of FIG. 22C (or the stable state of FIG. 22A). Also,
In the stable state of FIG. 22B, the applied voltage is + V ₁
Switching to a voltage below (or -V ₁ or voltage) from -V ₁ or more voltage (or + V ₁ voltage below) Figure 22
22 (B) remains stable and does not reach the stable state of FIG. 22 (A) (or the stable state of FIG. 22 (C)).

However, some of the AFLC molecules have stable states shown in FIG. 22 (A) (or stable states shown in FIG. 22 (C)).
When the applied voltage is switched from −V ₃ or lower voltage (or + V ₃ or higher voltage) to + V ₃ or higher voltage (or −V ₃ or lower voltage), the stable state of FIG. 22 (C) stable state) to FIG. 22 (C) stable state (or FIG. 22 (A) stable state).
If the stable state of (B) is likely to occur, the combination of the voltage waveforms of FIGS. 11 and 12 may be used.

When the AFLC molecule is in the stable state shown in FIG. 22B, the applied voltage is changed from a voltage of + V ₁ or less (or a voltage of −V ₁ or more) to a voltage of −V ₁ or more (or + V _1).
When the voltage is switched to the following voltage), the stable state of FIG. 22B does not remain and the stable state of FIG.
(Stable state of (C)) is likely to occur,
It is also conceivable to use a combination of voltage waveforms.

When the AFLCD 14 displaying "ABCD" shown in FIG. 3 actually displays "EBCD" in FIG. 7, the scan electrodes L ₀ , L ₁ , L ₂ , L ₃ and the signal electrodes S ₁ , S are displayed. _The voltage waveforms applied to ₂ are as shown in (1) to (6) of FIG. 18, and as a result, the voltage waveforms applied to the pixels A ₀₁ , A ₀₂ , A ₁₁ , and A ₁₂ are shown in (7) of FIG. )-(10).

That is, (1) of FIG. 18 shows the voltage waveform applied to the scan electrode L ₀ , and the selection voltage V _CR for interlaced scanning of N: 1 is applied in the period of ₀ to 2t ₀ , and 2 to 4t. _The partial rewriting scanning selection voltage V _CAP is applied in the period ₀ , the partial rewriting scanning selection voltage V _CEP is applied in the period 4 to 6t ₀ , and the interlaced scanning of N: 1 is performed in the period 10 to 12t _0. The selection voltage V _CX is applied. FIG. 18 (2) shows a voltage waveform applied to the scan electrode L ₁ , which is 6 to
Selection voltage V _CAP of the partial rewriting scanning for a period of 8t ₀ is applied, the selection voltage V _CEP for partial rewriting scanning for a period of 8～10T ₀ is applied. FIG. 18 (3) shows a voltage waveform applied to the scanning electrode L ₂ , and the selection voltage V _CAN for partial rewriting scanning is applied during the period of 12 to 14t ₀ , and 14
Select voltage V _CEN for partial rewriting scanning in a period of up to 16t ₀
Is applied. (4) in FIG. 18 is selected voltage V _CAN for partial rewriting scan is applied at a period of 16～18T ₀ is the voltage waveform applied to the scan electrodes L _4, for partial rewriting scanning for a period of 18～20T ₀ Selection voltage V _{CE N} is applied. 18 (5) shows the voltage waveform applied to the signal electrode S ₁ , and FIG. 18 (6) shows the voltage waveform applied to the signal electrode S ₂ .

As a result of applying these voltages, pixel A ₀₁
19 is applied with the voltage waveform of (7) in FIG. 19, the pixel A ₀₂ is applied with the voltage waveform of (8) of FIG. 19, and the pixel A ₁₁ is applied with the voltage waveform of (9) of FIG. , To pixel ₁₂ is shown in FIG.
The voltage waveform of (10) of 9 is applied.

The following is a description of the operation of the display control device 13 used in this embodiment. The data to be displayed on the AFLCD 14 is obtained from a digital RGB signal (with a clock) sent from the personal computer 2 to the CRT display 3 as shown in FIG. This digital RGB
The signals are shown in (1) of FIG. 4 and (4) of FIG. 4, and a horizontal synchronizing signal HD which gives a period for one horizontal scanning section of the image information output to the display 3, and (2) of FIG. A vertical synchronizing signal VD which gives a cycle of the information for one screen, and FIG.
(3) and display data DI which is the information itself shown in (5) of FIG. 4, and a clock CLK for transferring the information shown in (6) of FIG. Display data D
I is distinguished by attaching a number for each horizontal scanning section in (3) of FIG. 4 and by attaching a number for each pixel in (5) of FIG.

The 16 × 16 pixels of the AFLCD 14 are scanned
Electrode L₀~ L₇And signal electrode S₀~ S₇Display P consisting of
₀And the scanning electrode L₀~ L₇And signal electrode S₈~ S_FTable consisting of
Indicator P₁And the scanning electrode L₈~ L_FAnd signal electrode S₀~ S₇From
Display P₂And the scanning electrode L₈~ L _FAnd signal electrode S₈~ S
_FDisplay P consisting of₃And is virtually divided into
The data of the 0th horizontal scanning section of the display data of (3) is
The data of the 1st to 8th horizontal scanning sections following this are displayed on the display unit.
Minute P₀~ P₃Indicate which of these corresponds.

That is, when the display data of (3) of FIG. 4 is shown in a matrix form as shown in FIGS. 5 and 6, the third data of the 0th horizontal scanning section is “bright” (data without diagonal lines), 7th
If the data is “bright” (corresponding to this in FIG. 5), the data of the following 1st to 8th horizontal scanning sections corresponds to the display portion P ₀ , and the 3rd data of the 0th horizontal scanning section is “bright”. "And the seventh
If the data is “dark” (data with diagonal lines), the data of the following 1st to 8th horizontal scanning sections corresponds to the display portion P ₁ , and the 3rd data of the 0th horizontal scanning section is “dark”, seventh data if "bright" data (FIG. 6 corresponds to this) subsequent first to eighth horizontal scanning segment corresponding to the display portion P _2, the third data of the 0th horizontal scan segment in the "dark", the data of the first to eighth horizontal scanning segment seventh data followed next if "bright" corresponds to the display portion P _3.

The structure of the display control device 13 is as shown in the block diagram of FIG. First, the digital RGB signal output from the personal computer 2 is distributed to the input control circuit 23 and the display memory circuit 20.

The display memory circuit 20 already has the FLCD 1
Although the data of "ABCD" shown in FIG. 3 displayed in FIG. 4 was recorded, the display data DI of "E" shown in FIG. 5 was recorded.
Is input, the data changes to the "EBCD" data shown in FIG. At this time, the changed pixel data of the data of each pixel of the display memory circuit 20 is shown in FIG. The change in the data shown in FIG. 8 is the transition data ID
It is output as F to the identification memory circuit 21 and the different memory circuit 22.

In the identification memory circuit 22, the scan electrodes L ₀ ,
L ₁ corresponds to group G ₀ , scan electrodes L ₂ and L ₃ correspond to group G ₁ ,. ． ． ． , Scan electrodes L _E and L _F correspond to G ₇ . The transition data IDF corresponding to the group is 1
If any one of them is "1" (changed), the identification data GDF corresponding to that group becomes "1" (changed), and all the shift data IDFs corresponding to that group are "0".
If (no change), the identification data GDF corresponding to the group remains unchanged.

In the same different memory circuit 22, the transition data IDF
Are grouped into four pixels, and if the shift data IFD corresponding to the four pixels are all "0" (no change), the identification data GDF corresponding to that group remains unchanged. In the different memory circuit 22, the shift data IDFs are grouped into four pixels, and when all the shift data IDFs corresponding to the four pixels are "0" (no change), "0" otherwise, "1".
(Changed) is recorded as shown in FIG.

The output side control circuit 24 is the identification memory circuit 22.
The group address GAC is output to and the corresponding identification data GDF is received as output identification data OGDF. If the data is "1" (changed), the scan electrode corresponding to the group is partially rewritten and driven, and the data is output. Is 0 (no change), the operation of checking the output identification data OGDF of the next group is repeated.

The drive control circuit 25 includes the display memory circuit 20.
From the same memory circuit 22 to the data DF
From the identification memory circuit 21 to the identification data RGDF, DG
The EF outputs the address OAC and the control signal from the output control circuit 24.
E / WN, H / RN, TOG are input. These de
The display data XI from the drive control circuit 25,
Optional data YI, transfer clock CK, latch pulse LP
N, drive voltage V_C0, V _C1, V_S1Output to AFLCD14
To be done.

FIG. 21 is a timing chart for explaining the operation of the display control device 13. 21 (1)
Is an address O output from the output control circuit 24 to the display memory circuit 20, the different memory circuit 22 and the drive control circuit 25.
21 is an address OAS output from the output control circuit 24 to the display memory circuit 20 and the different memory circuit 22. 21 (3) shows data DA output from the display memory circuit 20 to the drive control circuit 25, and FIG. 21 (4) shows data DF output from the different memory circuit 22 to the drive control circuit 25. 21, (5) is the identification data RGDF output from the identification memory circuit 21 to the drive control circuit 25, and (6) in FIG. 21 is the identification data DGDF output from the identification memory circuit 21 to the drive control circuit 25. 21 (7) is a control signal H output from the output control circuit 24 to the drive control circuit 25.
21 is a control signal E / WN output from the output control circuit 24 to the drive control circuit 25, and (9) in FIG. 21 is output from the output control circuit 24 to the drive control circuit 25. The control signal TOG is output, (10) in FIG. 21 is the display data XI output from the drive control circuit 25 to the AFLCD 14, and (11) in FIG. 21 is the display output from the drive control circuit 25 to the AFLCD 14. Data YI, (12) in FIG. 21 is a latch pulse LPN output from the drive control circuit 25 to the AFLCD 14, and (13) in FIG. 21 is from the drive control circuit 25 to AFL.
It is the selection voltage V _CO output to the CD 14. The operation of the display control device 13 will be described below with reference to FIG.

The output side control circuit 24 has already made the FLCD 1
It is assumed that the display of No. 4 becomes the state of "ABCD" shown in FIG. 3, and the states of the different memory circuits 22 are all "0" (no change). After that, before the time t = -4t ₀ , the input control circuit 23 changes the recording data of the display memory circuit 20 from the state of “ABCD” shown in FIG. 3 to the state of “EBCD” shown in FIG. All the identification data GDF of 21 changes from “0” (no change) to the states of groups G _{0 to} G ₃ of “1”, and the state of the different memory circuit 22 changes to the state shown in FIG. 9 and thereafter. It is assumed that the recording data of the display memory circuit 20 continues to be in the "EBCD" state shown in FIG.

Time t = -2t _{0 to} 0 is a period for preparing a signal for the first interlace scanning, and the output control circuit 24
Outputs an output address OAC = "0" to the display memory circuit 20, the different memory circuit 22 and the drive control circuit 25,
Data DA corresponding to the scan electrode L ₀ from the display memory circuit 20, data DF corresponding to the scan electrode L ₀ from the different memory circuit 22, and group G ₀ from the identification memory circuit 21.
The data RGDF = “1” (changed) corresponding to is output to the drive control circuit 25. Further, from the output control circuit 24 to the drive control circuit 25, the control signal H / RN = "0" (see FIG.
At 1, a low level potential) and TOG = “0” are output.

In the drive control circuit 25, 1) when the control signal H / RN is "0" (interlaced scanning), the data DF is "0" or the data RGDF is "0" (no change) and the data DA is " If it is "0", the display data XI = "1", and 2) when the control signal H / RN is "0" (interlaced scanning), the data DF is "0" or the data RGDF is "0" (no change). If the data DA is "1", the display data XI = "0", and 3) when the control signal H / RN is "0" (interlaced scanning), the data DF is "1" and the data RGDF is "1".
If (changed), the display data XI = "0" is AFL.
Output to CD14. Also, the address OAC = "0"
The selection data YI corresponding to is output to the AFLCD 14.

At time t = _{0 to} 2t ₀ , A) control signal H / RN = “0”, control signal TOG = based on the control signals H / RN and TOG at this time.
If "0", the combination of voltage waveforms in FIG.
Is output to. Further, the time t = ₀ to 2t ₀ is also a period for preparing a signal for the first partial rewriting scanning, and the output control circuit 24 changes the display memory circuit 20 and the different memory circuit 2 from each other.
2, the output address OAC = "0" is output to the drive control circuit 25, the display memory circuit 20 outputs the data DA corresponding to the scan data L ₀ , and the different memory circuit 22 outputs the data DF corresponding to the scan data L _0. The identification memory circuit 21 outputs data DGDF = “1” (changed) corresponding to the group G ₀ to the drive control circuit 25. Further, the output control circuit 24 sends a control signal H / RN to the drive control circuit 25.
= “1” (high-level potential in FIG. 21) and E / WN =
"0" and TOG = "0" are output.

In the drive control circuit 25, 4) when the control signal H / RN is "1" (partial rewriting scan) and the control signal E / WN is "0", the data DF is "1" and the data DGDF is " 1 "(changed) and the data DA is" 1 ", the display data XI =" 1 ", 5) the control signal H / RN is" 1 "(partial rewriting scan), and the control signal E / WN is" When the data DF is "1", the data DGDF is "1" (changed) and the data DA is "0", the display data XI = "0" is 6) and the control signal H / RN is "1". When the control signal E / WN is "0" and the data DF is "0" or the data DGDF is "0" (no change), the display data XI = "0" is sent to the AFLCD 14. Is output. Further, the selection data YI corresponding to the address OAC = “0” is output to the AFLCD 14.

Further, during the time t = 2t _{0 to} 4t ₀ , B) the control signal H / RN is “1” based on the control signals H / RN, E / WN and TOG at this time, and the control signal E / W
If N is “0” and the control signal TOG is “0”, FIG.
The combination of the voltage waveforms is output to the AFLCD 4. Further, the time t = 2t _{0 to} 4t ₀ is also a period for preparing a signal for the second partial rewriting scanning, and the output control circuit 24 outputs the signal to the display memory circuit 20, the different memory circuit 22 and the drive control circuit 25. The address OAC = “0” is output, the display memory circuit 20 outputs the data DA corresponding to the scan electrode L ₀ , the different memory circuit 22 outputs the data DF corresponding to the scan electrode L ₀ , and the identification memory circuit 21 outputs the group G. Data DGDF = “1” (changed) corresponding to ₀ is output to the drive control circuit 25. Also, the output control circuit 2
Control signals H / RN = “1”, E / WN = “1” and TOG = “0” are output from 4 to the drive control circuit 25.

In the drive control circuit 25, 7) when the control signal H / RN is "1" (partial rewriting scanning) and the control signal E / WN is "1", the data DF is "1" and the data DGDF is "1". If the data DA is "1" (changed) and the data DA is "0", the display data XI = "1", 8) the control signal H / RN is "1" (partial rewriting scan), and the control signal E / WN is " When the data DF is "1", the data DGDF is "1" (changed) and the data DA is "1" when the data is "1", the display data XI = "0", 9) the control signal H / RN is " When the data signal DF is “0” or the data DGDF is “0” (no change) when the control signal E / WN is “1” (partial rewriting scanning), the display data XI = “0” is displayed on the AFLCD 14. Is output to. Further, the selection data YI corresponding to the address OAC = “0” is output to the AFLCD 14. Further time t
= 4t _{0 to} 6t ₀ , the control signals H / RN and E at this time are
/ WN, TOG C) Control signal H / RN is "1" and control signal E / W
If N is “1” and the control signal TOG is “0”, FIG.
The combination of the voltage waveforms is output to the AFLCD 4.

Further, the time t = 4t _{0 to} 6t ₀ is also a period for preparing a signal for the first partial rewriting scanning, and the output control circuit 24 changes the display memory circuit 20, the different memory circuit 22 and the drive control circuit. Output address OAC to 25 = “1”
Is output, the data DA corresponding to the scan electrode L ₁ from the display memory circuit 20, the data DF corresponding to the scan electrode L ₁ from the different memory circuit 22, and the data DGDF corresponding to the group G ₀ from the identification memory circuit 21. = “1” (changed) is output to the drive control circuit 25. Further, from the output control circuit 24 to the drive control circuit 25, the control signal H / RN =
"1", E / WN = "0", and TOG = "0" are output.

The drive control circuit 25 outputs the display data XI to the AFLCD 14 according to the rules 4) to 6). Further, the selection data YI corresponding to the address OAC = “1” is output to the AFLCD 14. Further time t = 6
Between t _{0 and} 8t ₀ , the control signals H / RN and E / W at this time are
Based on N and TOG, the combination of the voltage waveforms of FIG. 14 is output to the AFLCD 4 according to the rule of B).

Further, the time t = 6t _{0 to} 8t ₀ is also a period for preparing a signal for the second partial rewriting scanning, and the output control circuit 24 causes the display memory circuit 20 and the different memory circuit 2 to operate.
2, the output address OAC = "1" is output to the drive control circuit 25 and the data DA corresponding to the scan electrode L ₁ from the display memory circuit 20 is output from the different memory circuit 22 to the scan electrode L 1.
_The data DF corresponding to ₁ is output from the identification memory circuit 21 to the drive control circuit 25 as data DGDE = “1” (changed) corresponding to the group G ₀ . Further, from the output control circuit 24 to the drive control circuit 25, the control signal H / RN =
“1”, E / WN = “1” and TOG = “0” are output.

The drive control circuit 25 outputs the display data XI to the AFLCD 14 according to the rules 7) to 9). Further, the selection data YI corresponding to the address OAC = “1” is output to the AFLCD 14. Further time t = 8
Between t _{0 and} 10t ₀ , the control signals H / RN and E /
Based on WN and TOG, the combination of voltage waveforms in FIG. 15 is output to the AFLCD 4 according to the rule of C).

Further, the time t = 8t _{0 to} 10t ₀ is a period for preparing a signal for the second interlaced scanning, and the output control circuit 24 transfers to the display memory circuit 20, the different memory circuit 22 and the drive control circuit 25. The output address OAC = “0” is output, the data DA corresponding to the scan electrode L ₀ from the display memory circuit 22, the data DF corresponding to the scan electrode L ₀ from the same memory circuit 22 are grouped from the identification memory circuit 21. Data corresponding to G ₀ DGDF = “1” (changed)
Is output to the drive control circuit 25. Further, the control signal H / RN = "0" is sent from the output control circuit 24 to the drive control circuit 25.
And TOG = “1” are output.

The drive control circuit 25 outputs the display data XI to the AFLCD 14 according to the rules 1) to 3). Further, the selection data YI corresponding to the address OAC = “0” is output to the AFLCD 14. Further time t = 1
Between 0t _{0 and} 12t ₀ , the control signals H / RN and T at this time are
Based on OG D) Control signal H / RN = “0”, control signal TOG =
If “1”, the combination of the voltage waveforms in FIG. 11 is AFL.
Output to CD4.

Further, the time t = 10t _{0 to} 12t ₀ is a period for preparing a signal for the third partial rewriting scan, and the output control circuit 24 changes the display memory circuit 20, the different memory circuit 22 and the drive control circuit. 25 Output address OAC =
“2” is output, and the scan electrode L is output from the display memory circuit 20.
_The data DA corresponding to ₂ is the same as the data DF corresponding to the scan electrode L ₂ from the different memory circuit 22 in the identification memory circuit 2
Data corresponding to group G 1 from ₁ DGDF = “1”
(Changed) is output to the drive control circuit 25. Also,
From the output control circuit 24 to the drive control circuit 25, a control signal H /
RN = "1" and TOG = "1" are output.

The drive control circuit 25 outputs the display data XI to the AFLCD 14 according to the rules 4) to 6). Further, the selection data YI corresponding to the address OAC = “2” is output to the AFLCD 14. Further time t = 1
Between 2t _{0 and} 14t ₀ , the control signals H / RN and E at this time are
/ WN, TOG E) Control signal H / RN is "1" and control signal E / W
If N is “0” and the control signal TOG is “1”, FIG.
The combination of the voltage waveforms is output to the AFLCD 4.

Further, the time t = 12t _{0 to} 14t ₀ is a period for preparing a signal for the fourth partial rewriting scanning, and the output control circuit 24 changes the display memory circuit 20, the different memory circuit 22 and the drive control circuit 25. Output address OAC = "2"
Is output, data DA corresponding to the scan electrode L ₂ from the display memory circuit 20, data DF corresponding to the scan electrode L ₂ from the different memory circuit 22, and data DGDF corresponding to the group G ₁ from the identification memory circuit 21. = “1” (changed) is output to the drive control circuit 25. Further, from the output control circuit 24 to the drive control circuit 25, the control signal H / RN =
“1”, E / WN = “1”, and TOG = “1” are output.

The drive control circuit 25 outputs the display data XI to the AFLCD 14 according to the rules 7) to 9). Further, the selection data YI corresponding to the address OAC = “2” is output to the AFLCD 14. Further time t = 1
Between 4t _{0 and} 16t ₀ , the control signals H / RN and E at this time are
/ WN, TOG E) Control signal H / RN is "1" and control signal E / W
If N is “1” and the control signal TOG is “1”, FIG.
The combination of the voltage waveforms is output to the AFLCD 4.

Further, the time t = 14t _{0 to} 16t ₀ is a period for preparing a signal for the third partial rewriting scanning, and the output control circuit 24 changes the display memory circuit 20, the different memory circuit 22 and the drive control circuit 25. Output address OAC = "3"
Is output, data DA corresponding to the scan electrode L ₂ from the display memory circuit 20, data DF corresponding to the scan electrode L ₂ from the different memory circuit 22, and data DGDF corresponding to the group G ₁ from the identification memory circuit 21. = “1” (changed) is output to the drive control circuit 25. Further, from the output control circuit 24 to the drive control circuit 25, the control signal H / RN =
"1", E / WN = "0", and TOG = "1" are output.

The drive control circuit 25 outputs the display data XI to the AFLCD 14 according to the rules 4) to 6). Further, the selection data YI corresponding to the address OAC = “3” is output to the AFLCD 14.

Further, during the time t = 16t _{0 to} 18t ₀ , the combination of the voltage waveforms of FIG. 16 follows the rule of E) based on the control signals H / RN, E / WN and TOG at this time.
It is output to the AFLCD 4.

Further, time t = 16t _{0 to} 18t ₀ is a period for preparing a signal for the fourth partial rewriting scanning, and the output control circuit 24 changes the display memory circuit 20, the different memory circuit 22, and the drive control circuit 25. Output address OAC = "3"
Is output, data DA corresponding to the scan electrode L ₂ from the display memory circuit 20, data DF corresponding to the scan electrode L ₂ from the different memory circuit 22, and data DGDF corresponding to the group G ₁ from the identification memory circuit 21. = “1” (changed) is output to the drive control circuit 25. Further, from the output control circuit 24 to the drive control circuit 25, the control signal H / RN =
“1”, E / WN = “1”, and TOG = “1” are output.

The drive control circuit 25 outputs the display data XI to the AFLCD 14 according to the rules 7) to 9). Further, the selection data YI corresponding to the address OAC = “3” is output to the AFLCD 14.

Further, during the time t = 18t _{0 to} 20t ₀ , the combination of the voltage waveforms of FIG. 17 is A according to the rule of the above F) based on the control signals H / RN, E / WN and TOG at this time.
It is output to the FLCD 4. This operation is repeated thereafter. As a result, the display on the AFLCD 14 is displayed as “ABC
It changes from "D" to "EBCD" in FIG.

In the case of this driving method, the pixel A _kj (k ≠ i) to which the voltage waveform of (7) in FIG. 14 or (8) in FIG. 14 is applied.
It is preferable that the change in the amount of transmitted light of (1) and the change in the amount of transmitted light of the pixel A _ij are approximated by applying the voltage waveform of (5) in FIG.
Further, it is preferable that the same applies to FIGS.

Embodiment 2 Instead of the rules 4) to 9) of Embodiment 1, 10) the control signal H / RN is "1" (partial rewriting scanning).
When the control signal E / WN is "0" and the data DA is "1", the display data XI = "1", 11) the control signal H / RN is "1" (partial rewriting scan).
When the control signal E / WN is “0” and the data DA is “0”, the display data XI = “0”, and instead of the rules 7) to 9), 12) the control signal H / RN is “1” (partial rewriting scan)
When the control signal E / WN is "1" and the data DA is "0", the display data XI = "1", 11) the control signal H / RN is "1" (partial rewriting scan).
When the control signal E / WN is "1" and the data DA is "1", the display data XI = "0" may be used, but in this case, crosstalk due to partial rewriting scanning is likely to occur. This also causes flicker, but such a driving method is possible if some crosstalk is not a concern.

[0093]

According to the present invention, the polarity of the non-selection voltage of not only the scan electrodes selected by the interlaced scanning of 4: 1 but also the scan electrodes not selected is inverted. Therefore, the polarity is inverted. If the period T _{D to be performed} is a frequency of 30 Hz or higher, a display with no noticeable flicker can be obtained.

Further, when interlaced scanning of 4: 1 is performed, flicker due to rewriting is less noticeable than rewriting by sequential scanning from top to bottom of the panel as in the conventional example. Therefore,
The driving method according to the present invention can scan an anti-ferroelectric liquid crystal display having more scanning electrodes than the conventional driving method without causing flicker to be noticeable.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display system using an AFLCD.

FIG. 2 is a sectional view showing a schematic configuration of an AFLC panel.

FIG. 3 is a plan view showing a schematic configuration of an AFLCD used in an embodiment of the present invention.

FIG. 4 is a waveform diagram showing an output signal of a personal computer input to the display system.

5 is an explanatory diagram showing the display data of FIG. 4 in a matrix.

6 is an explanatory diagram showing the display data of FIG. 4 in a matrix.

FIG. 7 is an explanatory diagram showing a matrix of data to be displayed on the AFLCD.

FIG. 8 is an explanatory diagram showing a matrix of differences between data displayed on the AFLCD and data to be displayed.

FIG. 9 is an explanatory diagram collectively showing the differences from FIG. 8 for every four pixels.

FIG. 10 is a waveform diagram showing voltages applied to the scanning electrodes, signal electrodes, and pixels of the AFLC panel when N: 1 interlaced scanning is performed in the embodiment of the present invention.

FIG. 11 is a waveform diagram showing voltages applied to the scanning electrodes, the signal electrodes, and the pixels of the AFLC panel when N: 1 interlaced scanning is performed in the embodiment of the present invention.

FIG. 12 is a waveform diagram showing voltages applied to the scanning electrodes, signal electrodes, and pixels of the AFLC panel when N: 1 interlaced scanning is performed in the driving method of the present invention.

FIG. 13 is a waveform diagram showing voltages applied to scan electrodes, signal electrodes and pixels of an AFLC panel when N: 1 interlaced scanning is performed in the driving method of the present invention.

FIG. 14 is a waveform diagram showing voltages applied to the scanning electrodes, signal electrodes and pixels of the AFLC panel when the partial rewriting drive is performed in the example of the present invention.

FIG. 15 is a waveform diagram showing voltages applied to the scanning electrodes, the signal electrodes, and the pixels of the AFLC panel when the partial rewriting drive is performed in the example of the present invention.

FIG. 16 is a waveform diagram showing voltages applied to the scanning electrodes, signal electrodes and pixels of the AFLC panel when the partial rewriting drive is performed in the embodiment of the invention.

FIG. 17 is a waveform diagram showing voltages applied to the scanning electrodes, signal electrodes and pixels of the AFLC panel when the partial rewriting drive is performed in the embodiment of the invention.

FIG. 18 is a waveform chart showing voltages applied to some scan electrodes, signal electrodes, and pixels in the embodiment of the invention.

FIG. 19 is a waveform diagram showing voltages applied to some scan electrodes, signal electrodes, and pixels in the embodiment of the invention.

FIG. 20 is a block diagram showing a schematic configuration of a display control device used in an embodiment of the present invention.

FIG. 21 is a timing chart for explaining the operation of the display control device of FIG.

FIG. 22 is a conceptual diagram showing three stable states of an AFLC molecule.

FIG. 23 is a diagram showing applied voltage-transmitted light amount characteristics of an AFLC panel.

FIG. 24 is a plan view showing a schematic configuration of an AFLCD used in a conventional example.

FIG. 25 is a waveform chart showing voltages applied to the scanning electrodes, the signal electrodes, and the pixels of the AFLC panel in the conventional example.

FIG. 26 is a waveform diagram showing voltages applied to the scanning electrodes, the signal electrodes, and the pixels of the AFLC panel in the conventional example.

FIG. 27 is a diagram showing a procedure of performing N: 1 interlaced scanning in the conventional example.

FIG. 28 is a waveform diagram showing voltages applied to some scan electrodes, signal electrodes, and pixels in the conventional example.

FIG. 29 is a waveform diagram showing voltages applied to some scan electrodes, signal electrodes, and pixels in the conventional example.

[Explanation of symbols]

 1 AFLC Panel 2 Personal Computer 3 CRT Display 4 AFLCD 5 Glass Substrate 6 Insulating Film 7 Alignment Film 8 Sealant 9 AFLC 10 Polarizing Plate 11 Scanning Side Driving Circuit 12 Signal Side Driving Circuit 13 Display Control Device 14 AFLCD 15 Scanning Side Driving Circuit 16 signal side drive circuit 17 shift register 18 latch 19 analog switch array 20 display memory circuit 21 identification memory circuit 22 same memory circuit 23 input control circuit 24 output control circuit 25 drive control circuit S signal electrode L scan electrode

Claims (4)

[Claims] 1. An antiferroelectric liquid crystal having three stable states is interposed between a plurality of scanning electrodes and a plurality of signal electrodes arranged in directions intersecting with each other, and the first antiferroelectric liquid crystal is provided.
A method of driving an anti-ferroelectric liquid crystal in which the stable state and the third stable state are set to a bright display state, and the second stable state is set to a dark display state, in which a scanning electrode is selected by interlaced scanning and the scanning electrode is selected. The polarity of the voltage applied to the upper pixel is reversed, and if the pixel on the selected scan electrode is in the first stable state, it is in the third stable state, and if it is in the third stable state, it is in the first stable state. To the stable state, and if it is the second stable state, hold that stable state, and then select the scan electrode that constitutes the pixel whose display state should be changed, and change that pixel from the dark display state to the bright display state. When changing, the antiferroelectric liquid crystal that constitutes the pixel is
When the pixel is changed from the bright display state to the dark display state by rewriting from the stable state of No. 3 to the third stable state or the first stable state, the antiferroelectric liquid crystal forming the pixel is changed to the third stable state.
The stable state of the anti-ferroelectric liquid crystal forming the pixel is maintained when the stable state or the first stable state is rewritten to the second stable state and the display state of the pixel is not changed. Driving method for ferroelectric liquid crystal display. 2. The step of selecting a scan electrode by interlaced scanning also reverses the polarity of the voltage applied to the pixel on the non-selected scan electrode, and the pixel on the selected scan electrode is first stabilized. Transition from state to third stable state,
The method for driving an anti-ferroelectric liquid crystal display according to claim 1, further comprising the step of changing from the third stable state to the first stable state or maintaining the second stable state. 3. An antiferroelectric liquid crystal having three stable states is interposed between a plurality of scanning electrodes and a plurality of signal electrodes arranged in directions intersecting with each other, and the first antiferroelectric liquid crystal is provided.
A method of driving an anti-ferroelectric liquid crystal in which the stable state and the third stable state are set to the bright display state and the second stable state is set to the dark display state, and the scan electrode is selected by the interlaced scanning, and the scan electrode is selected. The polarity of the voltage applied to the upper pixel is inverted, and the pixel on the selected scan electrode is rewritten to the third stable state if the first stable state, and the first stable state is rewritten to the first stable state. When the second stable state is maintained, the stable state is maintained, and then the scan electrode forming the pixel whose display state is to be changed is selected, and when the pixel is set to the bright display state, When the anti-ferroelectric liquid crystal forming the pixel is rewritten to the third stable state or the first stable state and the pixel is brought into the dark display state, the anti-ferroelectric liquid crystal forming the pixel is changed to the second stable state. Special to rewrite to Driving method for anti-ferroelectric liquid crystal display. 4. The step of selecting a scan electrode by interlaced scanning also reverses the polarity of a voltage applied to a pixel on an unselected scan electrode, and the pixel on the selected scan electrode is first stabilized. Transition from state to third stable state,
4. The method for driving an anti-ferroelectric liquid crystal display according to claim 3, further comprising the step of changing from the third stable state to the first stable state or maintaining the second stable state.