JPH0720382B2 - Digital speed controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital speed control device for controlling the rotation speed of a controlled object.

Prior Art As a digital speed control device, Japanese Patent Application No. 59-215403 was previously used.
It proposes what is shown in the specification.

FIG. 4 is a block diagram of this digital speed control device, in which 1 is a controlled body (a motor or a rotating body driven by the motor, hereinafter referred to as a motor), 2
Is a frequency generator that detects the number of revolutions of the motor 1 (hereinafter referred to as FG), 3 is the frequency discrimination (speed comparison) of the FG signal S _FG which is the output of FG ₂ using the clock pulse CK ₁
Digital speed comparison means 4 for detecting speed error information (hereinafter referred to as speed error) D ₁ , 4 is a digital filter for inputting speed error D ₁ and digitally processing this, 5 is a digital filter 4 Driving means for driving the motor 1 based on the output D ₂ and 6 are state detecting means for detecting the speed comparison state of the speed comparing means 3, and control the digital filter 4 by the detection output S ₁ .

5 and 6 are waveform charts for explaining the operation of the speed comparison means 3.

Normally, the speed comparison means 3 has a trapezoidal wave S as shown in FIG.
_TZ is created digitally. That is, the speed comparison means 3 is formed of an M-bit binary counter, and the output is obtained from the lower N bits. Preset pulse S _PR (6th pulse created from FG signal S _FG using clock pulse CK ₁
(See the figure) to preset the initial count value NP to the binary counter. Count NH decodes the output of the binary counter, a signal S _NH representing the NL, to create the S _NL, trapezoidal wave S _TZ "H" level period b the "L" level period C and lower N-bit output To obtain the slope period b and. NC is a count value 2 ^N-1 that represents the central value of the slope period b, and the period from NP to NC is the reference time Ti of the speed comparison means 3, which is the speed reference. From the trapezoidal wave S _TZ created in this way, the period T of the FG signal S _FG
A digital speed error D ₁ proportional to _FG can be obtained.

Next, the speed control operation will be described with reference to FIG.

The speed comparison means 3 uses the clock pulse CK ₁ to generate the FG signal S
A latch pulse S _LA preceding the timing and a preset pulse S _PR following the timing are created from _FG , and a trapezoidal wave S _TZ is created based on the preset pulse S _PR . Then, the trapezoidal wave S _TZ immediately before presetting is latched (sampled and held) by the latch pulse S _LA to obtain the digital speed error D ₁ . Here, the periods A, B, and C show three states when the period of the FG signal S _FG is larger than, equal to, and smaller than the reference period Ti. When T _FG > Ti, the obtained speed error D ₁ Is at “L” level and issues an acceleration command, T _FG = Ti
In the case of, a constant speed command is issued with a center value of 2 ^N-1 , and in the case of T _FG <Ti, a deceleration command is issued at the “H” level. As a result, the motor 1 goes through the acceleration or deceleration period of the period A or C and then the period B.
The control shifts to the constant speed rotation control of. However, in reality, the digital filter 4 is interposed, and due to the transient response of this filter, speed pull-in such as start-up or speed change is not immediately performed, and it takes a lot of time for pull-in. The state detecting means 6 is for solving this problem, detects the operating states a, b, and c of the speed comparing means 3 and controls the digital filter 4 by the detection output S ₁ . That is, when the operating state is a or c, the direct output of the filter 4 is cut, and instead the output equivalent to the speed error D ₁ is set as the filter output D ₂ ,
And the filter 4 is set to the center value ₂ ^N-1 . Then, the setting operation is released from the time of shifting to the operation state (b), and the filter is made to function.
With this configuration, acceleration and deceleration can be smoothly performed during transition periods A and C such as start-up and speed switching, and the filter 4 is operated from a state close to a steady state after shifting to the inclination period B. It is possible to shorten the time required for pulling in the speed.

Problems to be Solved by the Invention However, in the above configuration, as the output D ₂ of the digital filter 4 in the steady operation deviates from the center value 2 ^N-1 , the time required for the transient response after entering the slope period mouth However, there is a problem in that the speed pull-in time becomes long.

In view of such a point, the present invention provides a digital speed control device capable of shortening the speed pull-in time regardless of the value of the output D ₂ of the digital filter 4 in the steady operation from the minimum value to the maximum value. To aim.

Means for Solving the Problems A digital speed control device of the present invention comprises a speed comparison means for digitally detecting speed error information of a controlled object and a digital filter for digitally processing the output of the speed comparison means. And a first state indicating a period during which the speed comparison state of the speed comparison means is detected and speed error information corresponding to the speed of the controlled object is obtained, or a constant state regardless of the speed of the controlled object. Second indicating the period for which speed error information is obtained
State detection means for outputting a state detection signal indicating whether the first state or the second mode is selected by the mode switching signal indicating the first and second modes and the state detection signal. A signal representing the second state is transmitted to the second
And a state switching means for outputting a signal representing the second state as a state switching signal in the mode of 1), and when the state switching signal is a signal representing the first state, the digital filter is processed normally. When the state switching signal is a signal representing the second state, the processing operation of the digital filter is stopped and the immediately preceding state is held and the speed comparison means outputs the state. (Or an output equivalent thereto) is output to control the controlled object.

With the above-described structure, the present invention sets the operation state of the digital filter in the steady operation to the normal processing operation state when the state switching signal output from the state switching means represents the first state, and outputs the processing result. When the state switching signal represents the second state, the processing operation is stopped and the immediately preceding state is held to output the output of the speed comparison means (or an output equivalent thereto) to control the controlled object. By doing so, the controlled object can be smoothly accelerated and decelerated, and the speed can be immediately pulled in after shifting to the slope period for speed comparison. Therefore, unlike the case where the filter is simply set to the center value 2 ^N-1 to perform the speed pull-in, the speed pull-in can be performed in a short time regardless of the value of the filter output in the steady operation.

Practical Example FIG. 1 is a block diagram of a digital speed control device according to an embodiment of the present invention. In FIG. 1, 1 to 6 are fourth
The state switching means 7 is the same as the constituent elements of the device shown in the figure.
Is different in that it is added and functions as a new component.
State switching device 7 as an input the output S ₁ and the mode switching signal S ₂ of the state detection means 6, a state switching signal S ₃ to the operating state of the digital filter 7 performs whether switching states held
To occur.

FIG. 2 is a waveform diagram of the signals S _{1 to} S ₃ for explaining the operation of FIG. The mode switching signal S ₂ is, for example, a switching signal for starting or stopping the motor 1. In the illustrated example, when the mode switching signal S ₂ is “H”, a start command is given, and when it is “L”, a stop command is given. Here, times t ₁ and t ₅ are timings at which the motor 1 is started, and times t ₃ and t ₇ are timings at which the motor 1 is stopped. Further, the times t ₂ and t ₆ are the timings when the operation of the speed comparison means 3 enters the inclining period b, and the times t ₄ and t ₈ are the timings to escape. However, the mode switching signal S ₂ changes H at time t ₁ from the L, at time t ₃ from the H L, H from L at time t _5, from H to L at time t _7, the state detection signals S ₁ at time
H from L at t _2, L from H at the time t _4, at time t ₆ from L H,
It changes from H to L at time t ₈ . Where t ₁ ~ t ₂ , t ₅ ~ t ₆
Represents a period during which the motor 1 is _{started, t 3 ~t 4, t 7} ~t 8 represents the period until the escape slope period from issues a stop command. Although _{t 2 ~t 3, t 6 ~t} 7 is a period speed control device is operating normal, it is immediately after the time t _2, t ₆ there is a transient response period for speed retraction, thereafter It is in a steady state between t ₃ and t ₇ . State switching signal S ₃ is generated from the state detection signals S ₁ and mode switching signal S ₂ in the state switching means 7, H from L at time t _2, L from H at time t _3, H from L at time t _6, It changes from H to L at time t ₇ . Switching the operating state of the digital filter 4 as follows with reference to the state switching signal S _3. That is, without being allowed to state retaining operation as a normal filter in the period _{t 2 ~t 3, t 6 ~t} 7,
During the other period, the operation state of the filter is maintained. In this way, the operating state of the filter immediately before time t ₃ can be retained, so that the filter can be started from the value during steady operation when the state retention is next released at time t ₆ , and immediately after that. The speed can be pulled in immediately. It is not constrained by the value of the filter output in steady state. Further, the same applies after time t ₇ . In addition, in the periods other than t _{2 to} t ₃ and t _{6 to} t ₇ , since acceleration or deceleration is performed smoothly as in the conventional example,
The function of the digital filter 4 is cut, and D ₂ = D ₁ (that is, the output D ₂ of the digital filter 4 is used as the speed comparison means 3
Output of D ₁ or output equivalent to D ₁ . ), The “L” level or “H” level output is guided to the driving means 5. Note that this operation may be directly performed by the state detection signal S ₁ as shown by the dotted line in FIG. ₁ , and the period t _{3 to} t ₄ , t _{7 to} t.
_{If 8} is a value that can be ignored with respect to the response of the digital filter 4, the mode switching signal S ₂ can be omitted.

On the other hand, when the rotation speed of the controlled body 1 is switched from the first speed to the second speed, the speed pull-in can be similarly performed in a short time.

FIG. 3 shows a digital filter 4 which is a component of the present invention.
3 is a block diagram showing a specific circuit example of FIG. In the figure,
8 is the input digital signal (speed error) D ₁ and the predetermined value 2 ^N-1
A frequency dividing means for generating an output having a frequency proportional to the absolute value of the difference between the clock pulse CK ₂ and a gate means 9 for gated the output S ₄ of the frequency dividing means 8 by a state switching signal S ₃ .
10 uses the output S ₅ of the gate means 9 as a clock input (CK),
An up / down (UD) counter that uses the most significant bit signal S ₆ of the input digital signal D ₁ as an up / down switching input (U / D). 11 is a UD counter based on the status switching signal S ₃ (or status detection signal S ₁ ). Output switching means for selectively switching and outputting either output D ₃ or output equivalent to D _{1 of} 10, output means 12 for multiplying input digital signal D ₁ by a coefficient, output 13 for output switching means 11 ₄ and the output D ₅ of the multiplying means 12 are added, and the filter output D ₂ is obtained from the adding means 13.

The digital filter having such a configuration is a comparison and integration circuit having the frequency dividing unit 8, the UD counter 10, the multiplying unit 12, and the adding unit 13 as basic components, and has a filter characteristic suitable for the speed control device. In this digital filter, it is the gate means 9 that switches the state hold and the state hold release, and this can be achieved by whether or not the clock input to the UD counter 10 is prohibited by the state switch signal S ₃ . When the UD counter 10 has a preset function, it is necessary to cancel the preset function to maintain the state. While the state of the UD counter 10 is maintained, the output switching means 11 cuts the output of D ₃ and outputs an output equivalent to D ₁ as D ₄ . Output like this
D ₂ can be equal to D ₁ . Output switching means
11 may have a configuration in which the state detection signal S ₁ is used as a switching signal, or may be provided in a stage next to the adding means 13.

Of course, the digital filter 4 is not limited to the specific circuit example shown in FIG.

The state detection signals S ₁ shown in FIG. 2 time t ₂ which is delayed a time _{t 2, t 6 ', t} 6' and the state switched entered the inclined period rate compared after the lapse of a predetermined time It may be configured to do so.

Furthermore, in the above description, an example of application to the speed control device is shown, but it goes without saying that the same can be applied to a phase control device that controls the rotation phase of the motor 1.

EFFECTS OF THE INVENTION As described above, according to the present invention, by adding the function of holding the operating state of the digital filter which is a constituent element of the speed control device, it is possible to start regardless of the value of the filter output during steady operation. It is possible to shorten the speed pull-in at the time of speed change, etc., and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital speed control device according to an embodiment of the present invention, and FIG. 2 is an operation waveform diagram of the same embodiment.
FIG. 3 is a block diagram showing a concrete circuit example of a digital filter which is a constituent element of the present invention, FIG. 4 is a block diagram of the previously proposed digital speed control device, and FIGS. 5 and 6 show the same device. It is an operation waveform diagram. 3 ... Speed comparison means, 4 ... Digital filter, 6 ...
... state detecting means, 7 ... state switching means.

Claims (1)

[Claims] 1. A speed comparison means for digitally detecting speed error information of a controlled object, a digital filter for digitally processing the output of the speed comparison means, and a speed comparison state of the speed comparison means. A first state indicating a period during which speed error information corresponding to the speed of the controlled object is obtained, or a second state indicating a period during which constant speed error information is obtained regardless of the speed of the controlled object. When in the first mode, the first state or the first state is detected by the state detection means for outputting a state detection signal indicating whether or not, the mode switching signal indicating the first and second modes, and the state detection signal. And a state switching means for outputting a signal indicating the second state as a state switching signal in the second mode, wherein the state switching signal indicates the first state. When a signal The digital filter is put into a normal processing operation state and a processing result is output. When the state switching signal is a signal representing the second state, the processing operation of the digital filter is stopped and the immediately preceding state is held. A digital speed control device for controlling the controlled object by outputting the output of the speed comparing means (or an output equivalent thereto).