JPH07203557A - Multiplex transmission equipment - Google Patents

Abstract

PURPOSE:To provide multiplex transmission equipment in which the load of a data processing unit is lightened. CONSTITUTION:In this multiplex transmission equipment, the plural numbers of nodes constituted so as to be provided respectively with a communication control unit 101 to control communication and the data processing unit 102 to process data given and received through the communication are connected to a common communication line, and the communication control unit 101 is provided with a receiving buffer 203 which stores the data in a frame and repeats that data to the data processing unit 102, and circuits 201, 202 which judges whether or not the frame data DATA in the corresponding frame is valid on the basis of the flag data V/IV of the received frame, and stores only the data DATA of the frame shown to be valid by the result of that judgement in the receiving buffer 203.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex transmission apparatus having a plurality of nodes used in, for example, a vehicle, and more particularly to reducing the number of buffers in a node.

[0002]

2. Description of the Related Art To simplify wiring, a plurality of nodes are connected to a common communication line, and a controller, switches, lamps, auxiliary devices, etc. are connected to each of these nodes. Has been proposed (for example, Japanese Patent Laid-Open No. 3-1
No. 48936). Particularly, in a multiplex communication system for automobiles, each node has a communication control IC for controlling communication.
And a CPU for data processing. The communication control IC controls communication with other nodes. Also CPU
Passes data to or receives data from the communication control IC. For example, a switch or an actuator is connected to the CPU, collects the information indicated by the switch, passes it to the communication IC, and sends the information to other nodes. Information from other nodes is received by the communication IC and received by the CPU, and the CPU controls the connected actuator based on the information.

[0003]

In such a multiplex communication system, a frame stores a plurality of types of data, so that the storage position of each individual data is predetermined. For example, four nodes (W,
Consider a system consisting of (X, Y, Z) in which one frame F exchanged between these nodes contains, for example, four types of data A, B, C, D. Among these nodes, one node X generates data A, and the other nodes (for example, nodes Y and Z) use the data A. Further, it is assumed that the data B is generated in the node Y and the data B is used in the nodes X and Z. Further, it is assumed that the data C is generated in the node Z and the data C is used in the node X. That is, the node X is in a position to use the data B and C.

As described above, since the frame F stores a plurality of types of data, and the storage positions of the individual data are in a predetermined relationship, the frame F always stores all the data A, B ,. It is necessary to include C and D, and therefore, when the data C is updated in the node Z, the node Z includes the frame C including the latest value of the data C.
Is transmitted to the node X, the frame F will include B, which is the old value.

The node X which has received the frame F cannot judge that the data C is the latest value and the data B is the old value only by the data value. Therefore, in a multiplex communication system in which a frame with a fixed data storage position is exchanged, a flag indicating whether data is valid or invalid (hereinafter referred to as V / IV (valid / invalid) flag) It is set in the data.

In the above-described multiplex communication system in which each node is divided into a communication control IC for controlling communication and a CPU for data processing, the communication IC receives the V / IV flag as it is and passes it to the CPU. According to the flag, the CPU has been able to sort out necessary data and unnecessary data. As described above, in the conventional multiplex communication system, the CPU is forced to take in even unnecessary data, and when the CPU is required to perform high-speed processing, the burden of this wasteful processing increases the high-speed processing of the CPU. It was a hindrance factor.

[0007]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to propose a multiplex transmission apparatus in which the processing efficiency of the entire system is improved without putting an unnecessary load on the data processing unit. The configuration of the present invention for achieving the above-mentioned object is a node having a communication control unit for performing communication control and a data processing unit for processing data transmitted and received via communication in a plurality of common communication lines. A connected multiplex transmission device, which is configured to exchange a frame including frame data and flag data indicating whether the frame data is valid or not between these nodes, wherein the node Each of the communication control units stores the data in the frame and relays the data to the data processing unit, and whether the frame data in the frame is valid based on the flag data of the received frame. Means for determining whether or not, and only the frame data indicating that the determination result is valid is stored in the reception buffer. Characterized by comprising a means.

Since the communication control unit controls all the updates necessary for updating the reception buffer, the data processing unit is released from the data management of the buffer.

[0009]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In this embodiment, the multiplex communication device of the present invention is used in a multiplex communication system of an automobile. <System Configuration> FIG. 1 shows a format of a transmission frame used in this multiplex communication system.
This frame includes SOM (start of message) and EOM (end of message).
delimited by message). PR is a priority field, TY, which specifies the priority order of transmission of this frame.
PE is a field that indicates the type of this frame, ID is a field that defines the receiver of this frame, and V _{0 to} V ₃ are the following data fields that are valid (V = 1) or invalid (V = 0). Field that indicates the error, CRC is the field that stores the error check code, and ACK _{1 to} ACK _n are the ackn from the receiver.
This field stores the owledge bit.

The ID field means a so-called functional address. That is, a single value can specify a plurality of nodes as recipients. Further, one frame can transmit / receive up to four data (D _{0 to} D ₃ ).
FIG. 2 shows a typical configuration of a node used in this system. That is, the node 100 is basically a CSMA.
/ CD communication IC 101 and IC 10 for performing communication
1 includes a CPU 102 that processes data received by the IC 1 or prepares data to be transmitted by the IC 101, and a power supply 103 that generates a DC voltage from a battery power supply.

In this system, 1 sent by a node
IC1 of all other nodes for one transmission frame
01 is determined to have to return the ACK bit, respectively, as long as the frame is received without error. After transmitting the frame, the transmission source node checks all ACK bits, and retransmits the frame if there is a node that has not responded.

If the number of retransmissions to a particular node exceeds a predetermined number, the particular node is judged to be in failure. FIG. 3 shows the configuration of the multiplex communication network of the embodiment. In the example of this network, four nodes A, B, C and D are connected to one communication line. Two motors M ₂ and M ₃ and a switch SW ₁ are connected to the node A. Two motors M ₂ and M ₃ and a switch SW ₁ are connected to the node A. The motor M ₁ and the switch SW ₂ are connected to the node B. A motor M ₁ and a switch SW ₃ are connected to the node C. The motor M ₁ is connected to the node D.

FIG. 4 shows an example of a data frame used in the system of FIG. In the example of FIG. 4, the state of the switch and an instruction as to whether or not the motor should be turned on are included. The frame of ID = 1 indicates that the switch 1 is turned on and the motor 1 is turned on. The frame of ID = 2 indicates that the switch 2 is turned on and the motor 2 is turned on. ID = 3
Frame indicates that the switch 3 is turned on and the motor 3 is turned on.

Further, the CPU of the node A has ID = 2 or ID
It is set to receive = 3 frames. The CPU of node B is set to receive the frame with ID = 1. The CPU of node C is set to receive the frame with ID = 1. The CPU of node D has ID = 1
Is set to receive frames. Node A
When the switch SW1 of 1 is turned on, the motors of the nodes B, C and D are activated. Therefore, the frame (ID = 1) notifying that the switch SW1 is turned on and indicating that the motor 1 should be turned on is transmitted from the node A through the respective communication ICs of the node B, the node C, and the node D, respectively. Passed to the CPU.

When the switch SW2 of the node B is turned on, the motor M2 of the node A is activated. Therefore, the frame (ID = 2) notifying that the switch SW2 is turned on and indicating that the motor 2 should be turned on is passed from the node B to the CPU via the communication IC of the node A. When the switch SW3 of the node C is turned on, the motor M3 of the node A is activated. Therefore, the frame (ID = 3) notifying that the switch SW3 is turned on and indicating that the motor 3 should be turned on is passed from the node C to the CPU via the communication IC of the node A.

FIG. 4 is a diagram showing one data form of a frame transmitted / received in the system of FIG. This frame has ID = 1, and reception is permitted by all the nodes in FIG. Also, in the frame of FIG. 4, the data SW
₁ (= data D ₀ ) is SW ₂ (= data D ₁ )
Is generated by the node B, and SW ₃ (= data D ₂ ) is generated by the node C. The data D ₃ is unused. These data S
Flags V _{0 to} V ₃ are added to W ₁ , SW ₂ , and SW _{3 at} the nodes that generate the respective data. If the node A generates the signal of the switch 1 to generate the frame, the frame becomes as shown in FIG. In FIG. 5, the data SW1
, The corresponding V / IV flag is 1, and the V / IV flags of other data are 1.

The feature of the communication control IC of this embodiment is that the value of the V / IV flag of each data is checked and only the data whose value is 1 (that is, the corresponding data is valid) is checked. It tries to get it into the buffer. Figure 6
2 shows the communication IC of FIG. 2 in more detail. The communication IC 101 has the following features: It has a number of transfer buffers 201 according to the type of ID. The transfer buffer 201 temporarily stores the frame data received from the communication control. Therefore, the transfer buffer 201 has four data registers (DAT) for each ID.
A0 to DATA3) and four flag registers (V / IV0 to V / IV3) are provided. : It has the number of V / IV calculation units 202 according to the type of ID. : It has the number of reception buffers 203 according to the type of ID. Each transmission / reception buffer 203 has the format shown in FIG. 1, that is, it has a priority field, a TYPE field, and an ID field in addition to the data part. However, the V / IV field is unnecessary because the calculation unit 202 has already used it.

FIG. 7 shows a detailed configuration of the V / IV calculation section 202. The buffer 203 is a memory that can control data writing on a byte-by-byte basis, and is D only when there is 1 in W input.
The data at the input is written. The W input of each register of the buffer 203 is the write signal WR from the control unit 205 of the IC 101 and the flag of the temporary buffer 201.
It is a logical product with V / IV. This logical product is AND gate 20
It is generated in 4. The AND gate 204 writes only to the buffer 203 when the flag register V / IV is 0. Therefore, if all the V / IV flags of the four data received from the communication line are 1, only 0 is input to the W input of the buffer 203, so that even if the control unit 205 generates a WR pulse, it is written. Is not done. Then, if there is an update of data at any node, that node should have set the corresponding V / IV flag to 0 and transmitted the frame, so this node corresponds to the updated data. AND gate is 1
Is output to write to the corresponding register position in the buffer 203.

In other words, even if the AND gate 204 controls writing to the buffer according to the value of the V / IV flag,
The buffer 203 always stores and holds the latest data value of the system. FIG. 8 shows the transition of the reception buffer 203 of the node D. That is, it is assumed that 1011 is initially stored in the reception buffer 203 of the node D.
Here, from the A node, 01110100 (= V ₀ V ₁ V ₂ V ₃ SW ₀ SW ₁ SW ₂ S
If the frame W ₃ ) is received, V ₁ = 0, SW ₁ = 0, and even if SW ₂ = 1 V ₂ = 1 holds, node D
The buffer 203 of is 0011. Further, from the node B, 1010000 (= V ₀ V ₁ V ₂ V ₃ SW ₀ SW ₁ SW ₂ S
W ₃ ), V ₂ = 0 and SW ₂ = 0, so node D
The buffer 203 of 0001 becomes 0001. Further, from the node C, 11010010 (= V ₀ V ₁ V ₂ V ₃ SW ₀ SW ₁ SW ₂ S
W ₃ ), V ₃ = 0 and SW ₃ = 1 are satisfied, so node D
The buffer 203 of is 0011.

As described above, since the IC 101 carries out all the operations to make the buffer 203 reflect the latest system state, the CPU is released from the management of the buffer 203, and the CPU 102 is originally released by the released amount. Can concentrate on processing. The present invention can be variously modified without departing from the spirit thereof. For example, although the above embodiment has been described by taking the multiplex communication device of an automobile as an example, the present invention is not limited to this.

The frame format is not limited to that shown in FIG. Further, the V / IV calculation unit 202 of FIG. 6 is useful in the following points. That is, since the V / IV register is provided in common to all the nodes, the IC 101 can be created for general purposes. Moreover, even if the type of data generated by the CPU 102 is changed, the change can be flexibly dealt with. Therefore, if there is no change, that is, if the type of data generated in the node is fixedly determined, only the V / IV corresponding to that data needs to be set.

Although the calculation unit 202 in the above embodiment is composed of an individual circuit, a software or hardware scanner is provided, the scanner checks the value of the V / IV flag, and the flag is 1. It is possible to store only the data in the buffer.

[0023]

According to the present invention described above, since the buffer is managed by the communication control unit, the data processing unit is released from the management, so that the efficiency of the entire system is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a frame format used in a system of an embodiment.

FIG. 2 is a diagram showing a typical configuration of a node.

FIG. 3 is a diagram showing a network configuration of an embodiment.

FIG. 4 is a diagram showing an example of a frame format used in the system of FIG.

5 is a diagram showing an example of a frame format used in the system of FIG.

FIG. 6 is a diagram showing a detailed configuration of a communication IC 101 of a node according to the embodiment.

FIG. 7 is a diagram showing a detailed configuration of a V / IV calculation unit 202.

FIG. 8 is a diagram showing the transition of the buffer of the node D in the system shown in FIG.

Claims (3)

[Claims] 1. A multiplex transmission apparatus in which a node including a communication control unit for controlling communication and a data processing unit for processing data transmitted and received via communication is connected to a plurality of common communication lines. A multiplex transmission device configured to transmit and receive a frame including frame data and flag data indicating whether the frame data is valid or not between these nodes, wherein each communication control unit of the nodes is A receiving buffer for storing the data in the frame and relaying the data to the data processing unit; a means for judging whether or not the frame data in the frame is valid based on the flag data of the received frame; Means for storing in the receive buffer only the data of the frame indicating that the result is valid. Multiplex transmission apparatus according to. 2. A temporary buffer for temporarily storing a frame received from a communication line, wherein the determination means determines whether the frame data in the frame is valid based on the flag data in the temporary buffer. The multiplex transmission device according to claim 1, wherein it is determined whether or not it is. 3. The frame has a plurality of data and a plurality of flag data indicating whether or not the data is valid for each of the plurality of data, and the storage means has the data valid. 2. The multiplex transmission device according to claim 1, wherein only the data indicated by the flag data is stored in the reception buffer.