JPH07202676A - Driving circuit - Google Patents

Abstract

PURPOSE:To realize a driving circuit where an optimum matching with an external circuit is maintained. CONSTITUTION:An output circuit 2 is composed of plural try state buffers A1, A2,... activated or nonactivated individually by selection signals C1, C2,... and an external circuit 21 is driven. The levels of the input signal St and the output signal So of the output circuit 2 at the time of a test mode are compared in a test circuit 3, a buffer addition request signal Sa is outputted to a selection circuit 4 at the time of St>So, the selection circuit 4 outputs the selection signals C1, C2,..., buffer A1, A2,... are successively activated and driving capacity is increased. At the time of St=Go, a test circuit 3 outputs an addition disconnection signal Sb. The information on the buffer A to be required for obtaining a matching is stored in a freely writable nonvolatile memory 5 and reproducibility is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for driving an external circuit, and more particularly to a driving circuit capable of changing its driving ability in accordance with the external circuit.

[0002]

2. Description of the Related Art In a logic circuit, a driving circuit using a buffer is used to drive an external circuit based on an input signal. A buffer is a circuit element that outputs the signal to an external circuit without changing the logic of the signal, but depending on the input condition of the external circuit, the load capacity, the fanout of the buffer, or the like, one buffer may not be sufficient. . In such a case, it is necessary to use a buffer having a large driving capacity or add a buffer. Further, as disclosed in Japanese Patent Application Laid-Open No. 4-348487, a drive circuit in which an output circuit is formed by using a plurality of tristate buffers and a necessary tristate buffer is activated by a selection signal to increase the driving capability. Are also proposed.

A typical prior art is shown in FIG. The drive circuit 51 includes a plurality of tristate buffers C.
1, C2, ..., Cn (reference numeral C is used when collectively referred to) are connected in parallel, and an output circuit 52 and a shift register 53 are included. The tri-state buffer C having the same output capacity is used. Shift register 53
Receives the clock signal CK and the data signal DATA and outputs the buffer selection signal D1 from the output terminals Q1 to Qn.
D2, ..., Dn are sequentially derived. Buffer selection signal D1
~ Dn are individually applied to the control terminal c of the tri-state buffer C, and the corresponding tri-state buffer C is activated. In this way, the driving capability for the external circuit 61 is increased.

[0004]

However, in the drive circuit 51 according to the above-mentioned prior art, it is necessary to set the buffer selection signal D in order to obtain the drive capability adapted to the external circuit 61. is there. Further, since it is unknown whether the output from the selected buffer and the external circuit 61 match, trial and error is necessary. If a buffer having a large driving capacity is prepared in advance in order to avoid such trouble, a problem arises in that power is wasted in the case of the external circuit 61 having a small load capacity. Moreover, in the prior art, the stored contents of the shift register 53 are lost due to a power failure or power failure, so that the same procedure must be repeated every time the power is turned on again.

The object of the present invention is to solve the above-mentioned problems,
It is an object of the present invention to provide a drive circuit in which a switching element necessary for driving an external circuit is automatically selected and there is no problem even when troubles such as power interruption occur.

[0006]

According to the present invention, an external circuit is connected, a drive signal for driving the external circuit is given, and a drive circuit for outputting to the external circuit without changing the logic of the drive signal. In which a plurality of switching elements that are individually activated or deactivated are connected in parallel, the drive signal is applied to each switching element, and an output circuit that outputs the output from each switching element to the external circuit And a matching determination unit that determines the matching status of the output of the output circuit with respect to the external circuit and outputs selection information for selecting the switching element required for matching, and a matching determination unit based on the output of the matching determination unit. Selection means for selecting and activating the switching element necessary for, and storage means for storing the selection result of the selection means. Is a drive circuit characterized by.

The present invention is also characterized in that the output circuit includes a plurality of switching elements having the same output capacitance.

Further, in the present invention, the output circuit has a switching element having a predetermined output capacitance, and the output capacitances of the switching element are 2 ⁿ (n = 1, 2, 3, 3), respectively.
, N) times as many switching elements are included.

Furthermore, the present invention is characterized in that the storage means is a writable non-volatile memory.

[0010]

In the drive circuit according to the present invention, an external circuit is connected to the output circuit, and a drive signal is applied to the external circuit via the output circuit to drive the external circuit. In the drive circuit,
An output circuit in which a plurality of switching elements that are individually activated or deactivated are connected in parallel, a matching determination unit, and a storage unit are included.

The matching determination means compares the drive signal input to the output circuit with the output signal output from the output circuit to an external circuit, and the level of the output signal is higher than the level of the drive signal. When it is low, it is determined that there is no matching, selection information is given to the selecting means, and a switching element required for matching is selected and activated. This enhances the drive capability of the output circuit and eliminates the mismatch. The selection of the switching element and the activation or deactivation are performed by the cooperation of the matching determination means and the selection means, and accurate matching is automatically obtained, and the information about the selection mode of the switching element is stored in the storage means. Remembered. Therefore, optimal matching conditions are preserved and reproducible.

According to the invention, the output circuit is composed of a plurality of switching elements having the same output capacitance. Therefore, a desired switching element can be easily selected.

Further, according to the present invention, the output circuit has a switching element having a predetermined output capacitance and an output capacitance of 2 ⁿ (n = 1, 2, 3, 3) for the element.
, N) times as many switching elements are included.
Therefore, a desired driving capability can be realized with fewer switching elements.

Still further according to the invention, the storage means is realized by a writable non-volatile memory. As a result, even if a power failure such as a power failure occurs, the stored contents will not be lost.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a drive circuit 1 which is an embodiment of the present invention.
3 is a block diagram schematically showing the configuration of FIG. Drive circuit 1
Is an output circuit 2 and a test circuit 3 which is a matching determination means.
And a buffer selection circuit 4 which is a selection unit and a memory 5 which is a storage unit. The drive circuit 1 derives the input signal Si input to the input terminal 11 to the output terminal 12 without changing its logic. An external circuit 21 is connected to the output terminal 12. The output circuit 2 includes a plurality of tristate buffers A1, A2, ..., A which are switching elements.
n (reference numeral A is used for generic name) are connected in parallel. Each tri-state buffer A has selection signals C1, C2, ..., C applied to its control terminal c.
It is individually activated or deactivated by n (reference numeral C is used when collectively referred to). The memory 5 is, for example, E
It is realized by a non-volatile memory such as a PROM (erasable programmable read only memory).

The drive circuit 1 has a test mode for selecting a tristate buffer (hereinafter abbreviated as "buffer") A necessary for driving the external circuit 21, and an input signal S.
It has two operation modes: a normal mode in which the external circuit 21 is driven by i. The input switching circuit 6 realized by a logic gate or the like is connected to the input terminal 11. The contact of the input switching circuit 6 is switched to the input terminal 11 side in the normal mode and to the buffer selection circuit 4 side in the test mode by the input switching signal Sc.

In the test mode, the test signal St is output from the buffer selection circuit 4 via the input switching circuit 6 to the output circuit 2.
The level of the output signal So input to the output terminal 12 is monitored by the test circuit 3. The test circuit 3 determines the matching state with the external circuit 21 based on the level of the output signal So from the output circuit 2, and when it determines that there is a mismatch due to lack of level or the like, a buffer increase request signal (hereinafter, referred to as selection information) Sa (referred to as "multiplication request signal") is output to the buffer selection circuit 4. Buffer selection circuit 4
Select signals C2, C3 in response to the increase request signal Sa.
Is output, the other buffer A is activated to increase the driving capability, and the inconsistent state is eliminated. At this time, the selection information of the buffer A is written and stored in the memory 5. Memory 5
Since is non-volatile, power troubles such as power failure will not be affected.

In the normal mode, the data on the selection of the buffer A stored in the memory 5 is read, the corresponding buffer A is activated, and the external circuit 21 is activated.
The optimum drive capacity for is set. The two operation modes are set to the test mode when the mode signal Sm input to the mode terminal 14 is at high level, and to the normal mode when it is at low level. Hereinafter, a high-level signal is marked with (H) and a low-level signal is marked with (L) for distinction.

A mode signal Sm is output via the mode terminal 14.
When (H) is input, the buffer selection circuit 4 outputs the selection signal C1 to activate one buffer A1, and also outputs the test signal St and the input switching signal Sc (H).
The monitor ON signal Sf (H) is output. The input switching signal Sc (H) switches the input switching circuit 6 to the buffer selection circuit 4 side, and the test signal St is input to the output circuit 2 and the test circuit 3. Also, monitor ON signal Sf (H)
Then, the test circuit 3 is activated, and the output signal So is also input to the test circuit 3. The test signal St has the same logic level as that of the input signal Si, is in synchronization with the clock signal CK input from the clock terminal 13, and has a double cycle thereof. The test signal St is led to the output terminal 12 as the output signal So via the buffer A1 and input to the external circuit 21.

The test circuit 3 is realized by a comparison circuit or the like,
In the test mode, the test signal St and the output signal So
When the output signal So does not reach the specified level at a predetermined timing, it is determined that the output circuit 2 has insufficient driving capability and is in a mismatched state, and the increase request signal Sa is buffered. It outputs to the selection circuit 4 and requests the increase of the buffer A. The buffer selection circuit 4 is realized by, for example, a shift register, outputs the selection signals C2, C3, ... In response to the increase request signal Sa, sequentially activates the buffer A, and increases the driving capability for the external circuit 21. .

When the output signal So reaches the specified level due to the sequential increase of the buffer A, the test circuit 3 judges that the output circuit 2 and the external circuit 21 are matched, and outputs the increase stop signal Sb. When the buffer selection circuit 4 receives the increase stop signal Sb, it is necessary to write the number of the increase request signals Sa received up to that point or the number of output selection signals C to the memory 5 and drive the external circuit 21. The selection information of the buffer A is stored. When the writing to the memory 5 is completed, the buffer selection circuit outputs a mode switching request signal Sw for notifying the end of the test mode operation to the control unit (not shown) via the terminal 15. The mode signal Sm becomes low level and the mode is switched to the normal mode. In the normal mode, the stored data regarding the buffer A is read from the memory 5, the buffer A selected in the previous test mode is activated, and thereafter, the external circuit 21 is driven by the input signal Si.

According to the present invention, the buffer A necessary for driving the external circuit 21 is automatically selected in the test mode in this way, so that the optimum driving capability is always applied to the external circuit 21 whose load capacity is unknown. Is set, and the trouble of trial and error as seen in the prior art is unnecessary. Further, since the memory 5 is a non-volatile memory, the data is not lost even if a power failure such as a power failure occurs, and the data is read at the time of re-input and the optimum driving capability is always maintained.

FIG. 2 is a block diagram showing a specific electrical configuration of the drive circuit 1 shown in FIG. In FIG. 2, FIG.
The same parts as those are designated by the same reference numerals. The buffer selection circuit 4 includes a control unit 4a, a selection unit 4b, an AND gate 4c, and a buffer control unit 4d. The selection unit 4b is realized by, for example, a shift register, and the outputs Q1, Q2, ..., Qn have the buffer control unit 4d.
Entered in. The buffer controller 4d outputs the outputs Q1 to Q1.
The selection signals C1, C2, ..., Cn corresponding to Qn are generated. Further, the input switching circuit 6 includes two AND gates 6a,
6b and an OR gate 6c.

The drive circuit 1 is set to the test mode when the mode signal Sm input to the control section 4a is at high level (H), and to the normal mode when it is at low level (L). When the mode signal Sm (H) is input, the control section 4a outputs one pulse of the reset signal Sr, and outputs Q1, Q2 of the selection section 4b.
, Qn (reference numeral Q is used for generic name) are once reset. After the reset, the control unit 4a outputs the one-pulse data control signal Sd in synchronization with the clock signal CK, and sets the head output Q1 of the selection unit 4b to the high level. As a result, the selection signal C is output from the buffer control unit 4d.
1 is output, and one buffer A1 is activated. After the reset, the control section 4a outputs the input switching signal Sc, the clock control signal Se, the monitor ON signal Sf and the test signal St. These plurality of signals are high level signals in the test mode except the test signal St. The test signal St is a signal that is synchronized with a cycle twice that of the clock signal CK, and is the AND gate 6 of the input switching circuit 6.
It is input to one terminal of b.

The input switching signal Sc is the A of the input switching circuit 6.
One terminal (inverting input terminal) of the ND gate 6a and AN
It is input to the other terminal of the D gate 6b. As a result, the output of the AND gate 6a becomes low level, and the connection with the input terminal 11 is cut off. On the other hand, the test signal St is derived from the AND gate 6b. The test signal St is led to the output terminal 12 via the output circuit 2 as the output signal So and input to the external circuit 21.

The clock control signal Se is supplied to the AND gate 4
It is input to one terminal of c. The clock signal CK is input to the other terminal of the AND gate 4c. This makes A
A timing signal Sck synchronized with the clock signal CK is derived from the ND gate 4c and input to the selection unit 4b and the test circuit 3.

The monitor ON signal Sf is a signal for activating the test circuit 3. The test circuit 3 has a monitor ON signal S
When f is given, the level of the test signal St is compared with the level of the output signal So. If the comparison result is St> So, the increase request signal Sa for the buffer A is output, and if St = So due to the increase in the buffer A, the increase stop signal Sb is output.

Table 1 shows the types and conditions of the above signals.

[0029]

[Table 1]

The control unit 4a outputs the data control signal Sd in response to the increase request signal Sa, and the output Q of the selection unit 4b.
Shift 1 step. As a result, the buffer control unit 4
A selection signal C2 is output from d, and the buffer A2 is connected. Therefore, the output capacity of the output circuit 2, that is, the drive capacity, doubles together with the buffer A1 which is activated first. As a result, the level of the output signal So rises, and when the matching with the external circuit 21 is achieved, the test circuit 3 outputs the addition stop signal Sb. When the addition stop signal Sb is input, the selection unit 4b causes the data write line 18
For example, "1", which is the number of times the increase request signal Sa is input, is written in the memory 5 via. In addition, the increase request signal S
When a is continuously input, the selection unit 4b continues to activate the other buffer A. After that, at the time when the increase stop signal Sb is input, the number of times the increase request signal Sa has been input so far is written in the memory 5, and the mode switching request signal Sw is written.
(H) is output, the mode signal Sm is switched to the o-level, and the normal mode is set. The data written in the memory 5 is stored in the buffer controller 4 when the mode is switched to the normal mode.
The buffer A read by d and selected in the test mode is activated. Therefore, the drive capability of the output circuit 2 with respect to the external circuit 21 is kept optimum even after shifting to the normal mode. As the data written in the memory 5, bit data of the output Q of the selection unit 4b may be stored as described below.

FIG. 3 is a circuit diagram showing a configuration example of the selection unit 4b. In FIG. 3, parts corresponding to those in FIG. 2 are given the same reference numerals. The selection unit 4b is realized by a shift register including a plurality of D flip-flop circuits F1, F2, ..., Fn, and the number of stages n corresponds to the number of buffers A. The selection unit 4b includes a data control signal Sd, a timing signal Sck, and a reset signal S from the control unit 4a.
r is input. The outputs Q1 to Qn of the shift register are
After being reset once by the reset signal Sr, each time the timing signal Sck is input, the data control signal S
d is sequentially derived to the outputs Q1, Q2, .... Output Q1,
Q2, ..., Qn are input to the buffer control unit 4d, and the bit data of the outputs Q1 to Qn are sent to the memory 5 via the data write line 18.

FIG. 4 is a time chart showing the operation of the drive circuit 1 in the test mode. In FIG. 4, portions corresponding to those in FIGS. 2 and 3 are designated by the same reference numerals, and description will be given with reference to these drawings as well. The drive circuit 1 is reset, and as shown in FIG. 4 (6), the selection signal C
It is assumed that 1 is output and the buffer A1 is activated. This state is shown in FIG. 4 (9). At the same time, the test circuit 3 is turned on by the monitor ON signal Sf.
Shall be activated.

FIG. 4A is a waveform diagram of the timing signal Sck input from the AND gate 4c to the selection unit 4b. FIG. 4B is a waveform diagram of the test signal St output from the control unit 4a.

FIG. 4C is a waveform diagram of the output signal So input to the external circuit 21 via the output terminal 12. When the driving capability of the buffer A1 is insufficient, the level v1 of the output signal So1 at time t1 is lower than the level v0 of the test signal St that is the input signal. Therefore, the test circuit 3 operates at the time t when the next timing signal Sck rises.
In step 2, the increase request signal Sa1 shown in FIG. 4 (4) is output to the controller 4a.

The control unit 4a outputs the data control signal Sd to the selection unit 4b in response to the increase request signal Sa1. The selection unit 4b outputs the output Q2 to the buffer control unit 4d in response to the data control signal Sd. Control unit 4d
Outputs the selection signal C2 (H) shown in FIG. 4 (7) at time t2 in response to the output Q2. Therefore, the buffer A2 is activated, and the driving capability is doubled by the two buffers A1 and A2, as shown in FIG. Therefore, the waveform of the output signal So2 derived from the time t4 to t6 rises in level in a shorter time than the previous output waveform So1, and the level v2 (>) at the time t5.
v1). However, the level v of the test signal St
It is lower than zero.

Therefore, the test circuit 3 at the time t6, as shown in FIG.
The increase request signal Sa2 shown in (4) is output. The control unit 4a outputs the data control signal Sd in response to the increase request signal Sa2, whereby the selection unit 4b outputs the output Q3. The selection signal C3 (H) shown in FIG. 4 (8) is output from the buffer control unit 4d, and the buffer A3 is activated by the selection signal C3. This state is shown in Figure 4.
It is shown in (11). Three buffers A1, A2
The driving ability is tripled by A3, and the output circuit 2 outputs the output signal So indicated by reference numeral So3 in FIG. 4 (3).
Is output.

The level v3 of the output signal So3 at time t9 is higher than the previous level v2, and the test signal St
Is equal to the level v0. The test circuit 3 determines that the matching is achieved by this, and at time t10, the test circuit 3 of FIG.
And outputs the addition stop signal Sb (H). At the same time, the number "2" of the increase request signal Sa is written in the memory 5, the mode signal Sm is dropped to the low level, and the test mode ends.

In the above-described embodiment, the plurality of buffers A constituting the output circuit 2 are all provided with the control terminal c, but in the test mode, the buffer A1 is always activated after the reset, so that the control of the buffer A1 is controlled. The level corresponding to the selection signal C is always applied to the terminal c,
It may be active from the beginning.

FIG. 5 is a block diagram showing the configuration of a drive circuit 31 which is another embodiment of the present invention. 5 is similar to FIG. 2, and the same portions as the test circuit 3, the memory 5, and the input switching circuit 6 are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, it should be noted that the output capacities of the plurality of buffers B1, B2, ..., Bn (the reference numeral B is used when collectively referred to) constituting the output circuit 2a are
The output capacity of the first buffer B1 and 1 (= 2 ^0), successively 2 ⁿ (n = 1, 2, 3, ..., N) the output capacity of the other buffer B with respect to the first buffer B1 becomes doubled Is defined as follows. Therefore, by using, for example, four buffers B1 to B4, the output circuit 2a having a maximum output capacity of 15 times can be realized, the number of wires in the drive circuit 31 can be significantly reduced, and the circuit can be downsized. Can be planned. Further, if the drive capacity required for the drive circuit 31 is 7 times or less, for example, the number of buffers B may be three.
Further downsizing can be achieved. In this embodiment, since the output capacity of the buffer B is set in this way, a binary counter is used for the selection unit 24b instead of the shift register in the first embodiment.

FIG. 6 is a circuit diagram showing a configuration example of the selection section 24b. The selection unit 24b is composed of, for example, a binary counter composed of four T flip-flops T1 to T4. The outputs Qa, Qb, Qc, Qd derived from the T flip-flops T1 to T4 are input to the buffer control unit 24d. The buffer controller 24d outputs the output Qa ...
Select signals Ca, Cb, Cc, and Cd are output corresponding to Qd, and active / inactive of a buffer B (not shown) is controlled.

FIG. 7 is a time chart showing the operation of the drive circuit 31 in the test mode. In FIG. 7, FIG.
6 will be denoted by the same reference numerals, and description will be given with reference to these figures as well. It is assumed that the selection unit 24b is reset by the reset signal Sr and the test circuit 3 is activated by the monitor ON signal Sf.

At times t0 to t1, as shown in FIG. 7 (4), the data control signal Sd is input to the selection section 24b. This data control signal Sd is first transmitted to the buffer B1.
To form an output circuit 2a having a single driving capability. The data control signal Sd falls at time t1, and as a result, the high-level output Qa is output from the first-stage T-flop flip T1 shown in FIG. The buffer control unit 24d responds to the output Qa by sending the signal shown in FIG.
As shown in (5), the selection signal Ca is output,
Actively the buffer B1 of the output capacitance 1 times (= 2 ^0).
This state is shown in FIG. 7 (9). The buffer B1 inputs the test signal St shown in FIG. 7 (2) to the buffer B1 and outputs the output signal So1 shown in FIG. 7 (3). When the driving capability of the buffer B1 is insufficient, the level v1 of the output signal So1 at the time t2 becomes lower than the level v0 of the test signal St.

Therefore, the test circuit 3 outputs the increase request signal Sa to the control section 24a at the next rising time t3 of the timing signal Sck. In response to the increase request signal Sa, the control unit 24a outputs the data control signal Sd1 shown in FIG. 7 (4) to the selection unit 24b at time t3. The selection unit 24b outputs the output Q when the data control signal Sd1 falls.
Output Qb is output instead of a. Buffer control unit 24
In response to the output Qb, d drops the selection signal Ca to the low level to deactivate the buffer B1, and sets the output Qb to the high level to activate the buffer B2. This state is shown in Figure 7.
It is shown in (6) and (10). With the buffer B2, the driving capability of the output circuit 2a is increased by 2 ¹ = 2.
At time t6 of (3), the output signal So2 of level v2 (> v1) is derived. However, the test signal S
It is lower than the level v0 of t.

Therefore, the test circuit 3 again causes the increase request signal S at the next rising time t7 of the timing signal Sck.
a is output, and the control unit 24a causes the same time t7 in FIG.
And outputs the data control signal Sd2 to the selection unit 24b. The selection unit 24b sets the output Qa to the high level at the fall of the data control signal Sd2. The output Qb output from the previous time remains at the high level and does not change. Therefore, the buffer control unit 24d sets the selection signal output Ca to the high level again at time t8 in FIG. 7 (5) to activate the buffer B1. As a result, the driving capability of the output circuit 2a becomes 2 ⁰ +2 ¹ = 3 times as shown in FIG. 7 (11), and the output signal So3 becomes as shown at time t9 in FIG. 7 (3). Is the level v3 of the test signal St.
Is equal to The test circuit 3 judges that the matching has been achieved by this, and outputs the addition stop signal Sb (not shown).
The selection status of the buffer B at this time is written in the memory 5.

In this way, as in the case of the above-described embodiment, the operation of the drive circuit 31 in the test mode is completed,
Although the mode is switched to the normal mode, for example, when the level v3 of the output signal So3 does not reach the specified level v0 at time t10 in FIG. 7, the increase request signal Sa is further output at time t11. Control unit 24
The a outputs the data control signal Sd3 indicated by the broken line at the same time t11 in FIG. 7 (4) to the selection unit 24b. Therefore, at time t12, the buffer control unit 24d lowers the selection signals Ca and Cb to low level and sets the output Qc to high level. This activates the buffer B3, and the driving capability of the output circuit 2a becomes 2 ² = 4 times as shown in FIG. 7 (12).

In the present embodiment, the drive circuit 31 having a drive capacity up to 15 times is realized by the same operation. It goes without saying that if the buffer B and the selection unit 24b are added, the drive capacity is further increased.

In the above-described embodiments, the test circuit 3 is formed integrally with the drive circuit 1 or the drive circuit 31, but the test circuit 3 is necessary in the test mode. Alternatively, it may be a separate type that is connected outside the drive circuit 31. As a result, the drive circuit 1 or the drive circuit 31 can be made smaller.

[0048]

As described above, in the drive circuit according to the present invention, the output circuit for driving the external circuit is composed of a plurality of switching elements which are individually activated or deactivated, and the output circuit and the external circuit are matched. Since the situation is discriminated by the matching discriminating means and the discriminating result is notified to the selecting means so that the switching element necessary for achieving the matching is selected and activated or deactivated, it is troublesome to obtain the matching. Is unnecessary, and appropriate drive capability can always be obtained even for an external circuit of unknown capacity. Moreover, the selection information about the switching element selected by the selection means is stored in the writable nonvolatile storage means. Therefore, even if a power failure such as a power failure occurs, the stored contents are not lost and the reproducibility is high.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing an operation of a drive circuit 1 which is an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a drive circuit 1 that is an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a selection unit 4b used in the drive circuit 1.

FIG. 4 is a time chart showing the operation of the drive circuit 1.

FIG. 5 is a block diagram showing a configuration example of a drive circuit 31 which is another embodiment of the present invention.

6 is a block diagram showing a configuration example of a selection unit 24b used in a drive circuit 31. FIG.

FIG. 7 is a time chart showing the operation of the drive circuit 31.

FIG. 8 is a block diagram showing a configuration of a drive circuit 51 according to a conventional technique.

[Explanation of symbols]

 1, 31 drive circuit 2, 2a output circuit 3 test circuit 4 buffer selection circuit 4a, 24a control unit 4b, 24b selection unit 4c, 24c AND gate 4d, 24d buffer control unit 5 non-volatile memory 6 input switching circuit 6a, 6b AND Gate 6c OR gate 21 External circuit A1 to An, B1 to B4 Tristate buffer CK Clock signal Sa Addition request signal Sb Addition stop signal Sc Input switching signal Sck Timing signal Sf Monitor ON signal Si input signal Sm mode signal St Test signal

Claims (4)

[Claims] 1. A drive circuit, to which an external circuit is connected, receives a drive signal for driving the external circuit, and outputs the drive signal to the external circuit without changing the logic of the drive signal. A plurality of switching elements to be activated are connected in parallel, each drive signal is given to each switching element, an output circuit for outputting the output from each switching element to the external circuit, and the external circuit in the output circuit Matching discriminating means for discriminating the matching state of the output to the circuit and outputting selection information for selecting the switching element required for the matching, and selecting the switching element required for the matching based on the output of the matching discriminating means. A driving circuit, comprising: a selecting unit that is activated, and a storage unit that stores a selection result of the selecting unit. 2. The drive circuit according to claim 1, wherein the output circuit includes a plurality of switching elements having the same output capacitance. 3. The output circuit comprises a switching element having a predetermined output capacity, and a switching element having an output capacity of 2 ⁿ (n = 1, 2, 3, ..., N) times that of the switching element. The drive circuit according to claim 1, further comprising: 4. The drive circuit according to claim 1, wherein the storage unit is a writable nonvolatile memory.