JPH07202648A - Pulse generation circuit - Google Patents

Abstract

PURPOSE:To obtain the output of an exact pulse width in a pulse generation circuit. CONSTITUTION:A phase comparator 10, a low pass filter 12 and a VCO 14 composes a PLL. In the transistor 24 of a timing circuit determining the frequency of the triangle wave of a VCO 14, current that the change gradient of the terminal voltage of a capacitor 28 becomes always constant flows. As a result, the gradient of the terminal voltage of a capacitor 32 to be charged by a transistor 30 flowing the same current as the transistor 24 also be comes always constant. Therefore, by utilizing the gradient of this terminal voltage, a signal of a constant pulse width can be obtained in a monostatic multivibrator 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generation circuit for generating a pulse signal having an accurate pulse width.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits such as ICs have been widely used, and various pulse generating circuits have been used in this circuit. For example, in a video or television signal processing circuit, various pulse signals are generated inside a semiconductor integrated circuit according to an input horizontal synchronizing signal and vertical synchronizing signal.

FIG. 3 shows an example of a conventional pulse generation circuit, which is provided with a reference resistor RT whose one end is connected to the ground outside the IC. The reference resistor RT is connected to the collector of a diode-connected PNP transistor Q1 inside the IC via the RT terminal, and the emitter of the transistor Q1 is connected to the power source via the resistor R1. On the other hand, at the base of the transistor Q2, the emitter connected to the power source through the resistor R2
The base of the NP transistor Q2 is connected. Therefore, the transistors Q1 and Q2 form a current mirror.

The collector of the transistor Q2 has a capacitor C inside the IC whose other end is connected to the ground.
T (capacitance value is CT) is connected. And
The connection point between the collector of the transistor Q2 and the capacitor CT is connected to a monostable multivibrator (hereinafter referred to as monomulti) 1.

Further, an external trigger signal is supplied to the monomulti 1 through the IN terminal, and charging of the capacitor CT is started at the rising of the trigger signal, and this voltage is a predetermined threshold voltage VTH. Capacitor C
Stop charging T. Then, it outputs a signal that becomes H during this charging period.

Here, the pulse width T which is the output of the monomulti 1 is T = VTHCT / I, where I is the charging current to the capacitor CT.

Therefore, if the reference resistance RT is a fixed resistance, the current I becomes constant. Therefore, by setting the magnitude of the reference resistance RT, a signal having a desired pulse width is obtained at the output of the monomulti 1. be able to.

[0008]

However, in the circuit shown in FIG. 3, the capacitor CT is an element inside the IC. Therefore, it is unavoidable that the capacitance value varies about several percent based on the non-uniformity in the manufacturing process. Therefore, the pulse width T also varies, and there is a problem that an accurate pulse width cannot be obtained for the trigger. Further, since the capacitance value of the capacitor CT and the charging current I to the capacitor CT change with temperature, there is also a problem that the pulse width changes with temperature. Therefore, the above circuit cannot be used when an accurate pulse width is required.

The present invention has been made to solve the above-mentioned problems, and a pulse whose pulse width can be made constant even if the capacitance value of a capacitor in a semiconductor integrated circuit varies or the ambient temperature changes. An object is to provide a generating circuit.

[0010]

SUMMARY OF THE INVENTION The present invention is a pulse generation circuit using a semiconductor integrated circuit, and a voltage controlled oscillator forming a phase locked loop circuit for phase locking to an input signal, and a voltage controlled oscillator provided in this voltage controlled oscillator. And a constant current circuit for generating a constant current according to the error voltage and a first capacitor charged by the constant current circuit, and a timing circuit for generating a triangular wave according to the charging voltage of the first capacitor A current mirror circuit for extracting a constant current of the timing circuit, a second capacitor charged by the constant current extracted by the current mirror circuit, and a pulse width of a pulse width corresponding to a charging voltage of the second capacitor. A pulse generation circuit that generates a pulse signal,
And the first and second capacitors are formed near the semiconductor integrated circuit.

[0011]

The voltage controlled oscillator of the PLL circuit oscillates at the same frequency as the input signal. The timing circuit generates a triangular wave of this frequency, and the gradient of the change in the terminal voltage of the first capacitor is always constant because the variation in the capacitance value of the first capacitor is compensated by the current value of the constant current circuit. become. The second capacitor is provided near the first capacitor on the semiconductor integrated circuit. For this reason,
The first capacitor and the second capacitor have the same variation in capacitance value. Therefore, the gradient of the change in the terminal voltage of the second capacitor also becomes constant. Therefore, a pulse signal having a predetermined width can be obtained by utilizing the change in the terminal voltage of the second capacitor. Further, the change of the capacitance value of the capacitor is similarly compensated according to the change of the ambient temperature, and the change of the pulse width can be suppressed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of the embodiment.
In this example, a horizontal / vertical synchronizing signal (composite synchronizing signal) of a television signal is used as the trigger signal, and this is input to the input terminal 8 of the IC. A phase locked loop is provided to form a signal synchronized with this trigger signal. That is, the input terminal 8
Is connected to a phase comparator 10, the signal of the comparison result is input to a low pass filter 12, and the signal integrated here is input to a voltage controlled oscillator (VCO) 14. The output of the VCO 14 is output as a signal synchronized with the trigger signal, and the phase comparator 1
It is fed back to 0. Therefore, the phase comparator 10 compares the phase of the input trigger signal with the phase of the signal supplied from the VCO 14, and inputs the signal regarding the difference to the VCO 14 via the low pass filter 12. V
Since the CO 14 controls the oscillation by the voltage according to the input phase difference, the phase of the output signal of the VCO 14 is locked to the input trigger signal.

Here, the low-pass filter 12 is provided outside the IC, and a series-connected capacitor 12a and a resistor 12b for connecting a terminal 16 to which the output from the phase comparator 10 is connected to ground and a resistor 12b. Is composed of a capacitor 12c connected in parallel to the phase comparator 10
Predetermined integration processing is performed on the signal from.

The output of the low-pass filter 12 is connected via an external resistor 18 to a terminal 20 to which the input line to the VCO 14 is connected. On the other hand, an external timing setting resistor 22 (resistance value R), which connects the terminal 20 to the ground, is connected to the terminal 20. The timing setting resistor 22 is for determining the constant current value of the timing circuit in the VCO 14, and this constant current is affected by the error voltage supplied from the phase comparator 10 via the resistor 18, and the phase comparison is performed. The phase difference between the two signals supplied to the instrument 10 is eliminated.

In this timing setting circuit, a diode-connected PNP transistor 24 in which a current corresponding to the current flowing in the timing setting resistor 22 flows, and a base connected to the transistor 24 to form a current mirror. 26 and a capacitor 28 for connecting the collector of the transistor 26 to the ground. Then, the VCO 14 is a transistor 26
The capacitor 28 is charged by the amount of current flowing through the capacitor 28, and a triangular wave is formed there.

Here, the formation of this triangle charges the capacitor 28 with the current I1, and when the specified high voltage is reached, the current I1 is reached.
When the capacitor 28 is discharged at 1 and reaches a specified low voltage, switching to charging is repeated. Since the charging and discharging current values are the same, the terminal voltage of the capacitor 28 becomes a triangular wave.

This triangular wave determines the frequency of the output of the VCO 14, and this frequency matches the frequency of the trigger signal. That is, the VCO 14 constitutes a phase locked loop, and in the locked state, the oscillation frequency matches the trigger signal which is the input signal.

Therefore, even if the value of the capacitor 28 varies, the current I1 flowing therethrough is automatically adjusted and the gradient of the triangular wave is always constant.

In the present embodiment, the base of the transistor 24 is also connected to the base of the PNP transistor 30. Therefore, the transistor 30 also passes the same current I2 as the transistors 24 and 26. Also,
A capacitor 32 connected to ground is connected to the collector of the transistor 30, and the connection point between the transistor 30 and the capacitor 32 is input to the monomulti 1. Further, an input terminal 8 is connected to the monomulti 1 and a trigger signal is input. Therefore, the monomulti 1 outputs a pulse signal having a pulse width according to the state of charge of the capacitor 32. That is,
The threshold voltage of this monomulti 1 is set to the VT capacitor
If the capacitance value of C2 is C2, the output pulse width T is T = V
TH ・ C2 / I2.

If the capacitors 28 and 32 are formed in the vicinity of the IC, the characteristics become almost the same. That is, the values of these capacitors 28 and 32 similarly vary. The current I2 is the same as the current I1, and the gradient of the potential on the upper side of the capacitor 32 can be made constant regardless of the variation in the capacitance value of the capacitor 32. Therefore, the pulse width T of the output in the mono-multi 1 can always be made constant.

If the emitter area of the transistor 32 is different from that of the transistor 26 (usually an integer multiple), or if the capacitance value of the capacitor 32 is different from the capacitance value of the capacitor 28 (usually integer multiple), the monomulti 1 The output pulse width T can be set to an arbitrary value.

The emitters of the transistors 24, 26 and 30 are connected to the power source through the adjusting resistors. In addition, these transistors 24, 26 and 30 are also I
It is formed near C.

Next, FIG. 2 shows a configuration example of the timing adjustment circuit of the VCO 14. Thus, the operational amplifier 40 to which the reference voltage VREF is input to the non-inverting input terminal is provided, and the NPN transistor 42 and the resistor 44 are inserted and arranged between the collector of the transistor 24 and the terminal 20. The output of the operational amplifier 40 is connected to the base of the transistor 42, and the resistor 44 and the terminal 20 are connected to the inverting input terminal of the operational amplifier 40. The terminal 20 is connected to the timing setting resistor 22 having the resistance value R.
Is connected to ground via.

In such a configuration, the operational amplifier 40
Since the inverting input terminal of is set to VREF due to imaginary short, when the error voltage is 0, the transistor 24
The current I0 flowing through the line is I0 = VREF / R. Then, due to the error voltage applied to the upper end of the timing setting resistor 22, the current I0 changes so that the potential here becomes VREF. Therefore, the currents I0 and I1
, I2 is automatically adjusted according to the frequency of the trigger signal,
The variations in the capacitors 28 and 32 are caused by the currents I0, I1 and I.
Compensated by the magnitude of 2, the slope of the change in the terminal voltage of capacitors 28, 32 is always constant. Therefore, I
Even if the capacitance of the capacitor in C varies due to the manufacturing process, a signal with a constant pulse width can be obtained. Also,
Since the external timing setting resistor 22 and the like can be fixed and have little variation, the resistance value does not change with temperature, and the capacitance values of the internal capacitors 28 and 32 change as in the case described above. Compensated by the amount of current. Therefore, the pulse width can be maintained constant even if the ambient temperature changes.

[0025]

As described above, the timing circuit of the voltage controlled oscillator in the PLL circuit generates a triangular wave of this frequency, and the slope of the change in the terminal voltage of the first capacitor is the first capacitor. The variation in the capacitance value of is compensated by the current value of the constant current circuit and is always constant.
Since the first and second capacitors are provided in the vicinity of the semiconductor integrated circuit, the variations in the capacitance values of both capacitors are the same. Therefore, the gradient of the change in the terminal voltage of the second capacitor can be made constant, and a pulse signal having a predetermined width can be obtained by utilizing the change in the terminal voltage of the second capacitor. Further, the change of the capacitance value of the capacitor is similarly compensated according to the change of the ambient temperature, and the change of the pulse width can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an example.

FIG. 2 is a diagram showing a configuration of a timing circuit of a voltage controlled oscillator.

FIG. 3 is a diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Monostable Multivibrator (Monomulti) 10 Phase Comparator 12 Low Pass Filter 14 Voltage Controlled Oscillator (VCO) 22 Timing Setting Resistor 24, 26, 30 Transistor 28, 32 Capacitor

Claims (1)

[Claims] 1. A pulse generator circuit using a semiconductor integrated circuit, comprising a voltage-controlled oscillator that constitutes a phase-locked loop circuit that phase-locks to an input signal, and a voltage-controlled oscillator that is provided in the voltage-controlled oscillator and that responds to error voltage. A constant current circuit that generates a current and a first capacitor that is charged by the constant current circuit, a timing circuit that generates a triangular wave according to the charging voltage of the first capacitor, and a constant current of the timing circuit , A second mirror charged by the constant current extracted by the current mirror circuit, and a pulse generation circuit for generating a pulse signal having a pulse width corresponding to the charging voltage of the second capacitor And, wherein the first and second capacitors are formed in the vicinity of the semiconductor integrated circuit. Pulse generating circuit.