JPH07202595A - Inverter type amplifier - Google Patents

Abstract

PURPOSE:To provide the inverter type amplifier with low power consumption and high frequency band characteristics, capable of being subjected to power on and power down at high speed. CONSTITUTION:A power-down switch MOSFET 117 is provided on an amplifier 106. In a bias circuit 105 producing the bias voltage at the operation point, a power-down switch MOSFET 110 is provided. The output of the bias circuit 105 is connected to the input terminal of the amplifier 106 through a resistance 107. When the power-on signal PON is at the power-down state at high level, a node 108 is forced to the earth potential GND. In the power-on state, the node 108 is biased at the level of the operation point of the amplifier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter type amplifier composed of, for example, a MOSFET included in a semiconductor integrated circuit, for example, an input interface between circuits operating with different power supply voltages and signal amplitudes. -It relates to a technology effectively used for a circuit.

[0002]

2. Description of the Related Art The first prior art as an inverter type amplifier
There is a circuit in which a feedback resistor is connected between the input and the output of the inverter to make it self-biased (for example, University Lecture Series Revised Integrated Circuit Engineering (2), p. 176). ~ 178, issued by Corona Publishing Company on October 25, 1989). Since the output of such an amplifier is fed back to the input through a resistor, the point where the output voltage and the input voltage are equal is the operating point. In addition, as a second known example, for example, as described in JP-A-61-142809,
Some include an amplifier main body and a bias circuit having a feedback resistor connected between the input and output of an inverter having the same configuration as that of the amplifier main body, and applying this bias voltage to the input terminal of the amplifier main body.

[0003]

In the self-biased amplifier as in the first known example, the gain varies depending on the feedback resistance value unless the output impedance of the inverter is sufficiently smaller than the feedback resistance. Resulting in. However, the resistance in the semiconductor integrated circuit cannot be made very large because it takes an area. Therefore, it is necessary to reduce the output impedance of the inverter. Since the current always flows in the inverter type amplifier, there is a problem that the power consumption increases if the output impedance of the inverter is small.

In the second known example, a feedback resistor and a MOSFE
Since it is separated from the equivalent resistance of T, it is possible to reduce the current consumption, but the impedance seen from the input end has a capacitance for two inverters, so the characteristics at high frequencies deteriorate. It was discovered.

Further, in the case of providing a period during which no current flows (power down period) for the purpose of reducing power consumption, the output is not fixed unless the potential at the input end changes to the power supply or GND side to some extent. By then, there was a problem that unnecessary current would flow. Conversely, when the power-down period ends and normal operation is restored (power-on), the required output cannot be obtained until the potential at the input end reaches the prescribed potential. However, there was a problem that useless current flows. Especially, the amplifier input is LSI
This is the case where a relatively large capacitance component is coupled to the input terminal when coupled to the external input terminal. For example, when the above-mentioned inverter type amplifier is used in an input interface circuit between circuits which operate with different power supply voltages and signal amplitudes, a coupling capacitor for cutting a DC component of an input signal is interposed. It

An object of the present invention is to provide an inverter type amplifier which has low power consumption and high frequency characteristics. Another object of the present invention is to provide an inverter type amplifier which can be powered down at high speed. Still another object of the present invention is to provide an inverter type amplifier which can be turned on at high speed after power down.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the amplifier main body having the first inverter is provided with the first power-down switch transistor, and the bias circuit for generating the bias voltage at the operating point is provided separately from the amplifier main body to provide a high impedance. A bias voltage is applied to the input terminal of the amplifier body via the dance element.

The bias circuit is composed of circuit elements having substantially the same characteristics as the amplifier body,
A configuration may be employed in which a second inverter and a second power-down switch transistor are connected in series between the pair of operating power supplies, and the input and output of the second inverter are short-circuited.

From the viewpoint of limiting the operating current of the inverter to reduce the power consumption, the first and second power-down switch transistors have a predetermined operating current in the first and second inverters in the ON state. Can also be positioned as a constant current source for flowing

From the viewpoint of reducing the operating voltage applied to the inverter to reduce power consumption, a power down switch element can be provided in each of the first inverter and the second inverter.

When a substantial amplification operation is not performed, the input of the first inverter is forced to a level of one of the operating power supplies by controlling the power-down switch transistor to achieve low power consumption (power down state). Considering this, in order to be able to quickly shift from the power-down state to the operable state (power-on state), the charge element and the discharge are coupled to the input terminal of the first inverter, and the predetermined period immediately after power-on is performed. In the above, there is provided a control circuit for switch-controlling the discharge element and the charge element so as to control the input level of the first inverter in a negative feedback manner based on the output level of the first inverter.

The control circuit can be operated as an input protection diode by turning off the charge element and the discharge element after a predetermined period immediately after the power is turned on.

From the viewpoint of shortening the power-on time, it is also possible to employ a bypass transistor which is connected in parallel to the high impedance element and is kept in the on state for a certain period of power-on.

As another circuit form for powering down, there is provided a second inverter having substantially the same characteristics as the amplifier body, and a first switch transistor for selectively short-circuiting the input and output of the second inverter. And a second switch element which is complementarily switched with the first switch transistor and is arranged between the input of the second inverter and one of the power supplies. Also at this time, in order to realize high-speed power-on and power-down, charge elements and discharges having different conductivity types are coupled to the input terminal of the first inverter, and the first inverter is connected in a predetermined period immediately after power-on. The output of the inverter can be supplied to the control electrodes of the charge element and the discharge element, and the charge element and the discharge element can be controlled to be in the OFF state during the other period.

[0017]

According to the above-mentioned means, the use of the inverter type amplifier main body and the bias circuit as separate circuits acts as a separating element between the feedback resistor and the output impedance of the amplifier main body. As a result, the output impedance of the inverter can be increased and the current can be reduced. By connecting the two with a high impedance element, the impedance seen from the input end can be increased, The frequency characteristics of the band can be obtained. Controlling on / off of the power-down switch transistor provided in each of the amplifier main body and the bias circuit acts to fix the output potential of the amplifier regardless of the potential of the input end of the amplifier, Contributes to low power consumption. The negative feedback ON / OFF control of the discharge element and the charge element provided at the input terminal of the amplifier body by negative feedback for a certain period immediately after the power-on instruction speeds the achievement of the power-on state, and the bias circuit makes Setting either the discharge element or the charge element capable of outputting the level forcing the input of the inverter 1 in synchronization with the power-down instruction speeds up the achievement of the power-down state.

[0018]

1 shows an input interface circuit according to a first embodiment to which an amplifier of the present invention is applied. The input interface circuit 101 shown in the figure is not particularly limited, but it is a digital co-coder used for mobile communication.
It is included in the input stage of the dress signal processing LSI 10 and is used as an interface with the output of the transmitting / receiving LSI (not shown). The input interface circuit 101 receives a signal from the input terminal 103 via the coupling capacitor 102 and outputs a signal from the output 104. The coupling capacitor 102 is provided to cut the DC component of the input signal. That is, the power supply voltage and the signal amplitude of the digital codeless signal processing LSI 10 are different from those of the transmitting / receiving LSI (not shown).

The interface circuit 101 comprises a bias circuit 105 and an inverter type amplifier body 106, and an input 108 of the amplifier and an output 109 of the bias circuit are connected via a resistor 107. .

The bias circuit 105 is composed of a P-channel type MOSFET 111 and an N-channel type MOSFET 112 connected in series and has an output 109 shorted to the input of the inverter, and the inverter and the power source V.
It comprises a power-down P-channel switch MOSFET 110 connected to DD and a power-down N-channel switch MOSFET 113 connected between the inverter and the ground potential GND. It The switch MOSFET 110 is switch-controlled by an inverted signal PON * of the power-on control signal PON. The gate of the switch MOSFET 113 is connected to the power supply voltage VDD.

The inverter type amplifier body 106 is composed of a P-channel type MOSFET 115 and an N-channel type MOSFET 116 connected in series, the input of which is connected to the node 118 and the output of which is the node 104.
Connected to the inverter, the inverter and the power supply VD
Power-down P-channel switch MOSFET 114 connected between D and the inverter and GND
And a power-down N-channel switch MOSFET 117 connected between the power supply and the power supply. Switch M above
The gate of the OSFET 114 is coupled to the ground potential GND, and the switch MOSFET 117 is switch-controlled by the power-on control signal PON. The power-on control signal PON is a control signal for instructing power-on of the input interface circuit 101 etc. by its high level.

Input interface circuit 101 of this embodiment
Then, the input signal Vin is input from the input terminal 103 to the capacitor 1
02 to the node 108 of the amplifier. At this time, the DC potential of the node 108 is the bias circuit 10
5, it is biased to the same potential as its output node 109. The circuit characteristic of the bias circuit 105 is determined so that the bias voltage becomes equal to the voltage when the input and output of the inverter type amplifier 106 are short-circuited. Therefore, this input interface circuit 101
The operation as the inverter amplifier can be used as an amplifier similar to the self-biased inverter amplifier. For example, a P-channel MOSFET and an N-channel MO in the input interface circuit 101
When the SFET is different only in polarity and the other characteristics are the same, the bias voltage when operating as the amplifier, that is, the operating point of the amplifier main body 106 is the power supply voltage VDD.
It is said to be half the level of.

When power-down is performed in this embodiment, the power-on control signal PON is controlled to a low level and its inverted signal PON * is controlled to a high level. This allows
In the bias circuit 105, the MOSFET 113 is turned on and the MOSFET 110 is turned off.
In the main amplifier body 106, the MOSFET 114 is turned on and the MOSFET 117 is turned off. As a result, the output node 109 of the bias circuit 105
Also, the potential of the input node 108 of the amplifier body 106 is set to the low level, and the potential of the output node 104 is fixed to the high level. In this state, no current through path is formed in the bias circuit 105 and the inverter type amplifier main body 106.

When the power-down state is changed to the power-on state to enable the input operation, the power-on control signal PON is set to the high level and the inverted signal PON * thereof is set to the low level, whereby the MOSF of the bias circuit 105 is set.
The ETs 110 and 113 are turned on and the MOSFETs 114 and 11 of the inverter amplifier 106.
7 is turned on to enable the normal amplification operation of inverting and amplifying the input signal Vin and outputting it to the node 104.

In FIG. 1, an N-channel type bypass MOSFET 120 is provided in parallel with the resistor 107,
The MOSFET 120 is connected to the power-on control signal PON.
If the power-on instruction is given when the power-on instruction is given for a certain period immediately after the power-on instruction by
08 is immediately biased to the operating point of the amplifier body 106.

FIG. 2 shows an input interface circuit according to the second embodiment to which the amplifier of the present invention is applied. The input interface circuit 201 shown in the figure is not particularly limited, but is included in the input stage of the digital codeless signal processing LSI 11 used for mobile communication, and has an interface with the output of a transmitting / receiving LSI (not shown). -Used for faces. The input interface circuit 201 receives the signal Vin from the external terminal 203 via the coupling capacitor 202, and the output of the node 204 is the inverter 2.
Input 2 of the switch control circuit 207 via 05 and 206
While being fed back as 08, it is supplied from the output terminal 210 via the inverter 209 to the internal circuit of the signal processing LSI 11 for digital code dress. The coupling capacitor 202 is provided to cut the DC component of the input signal for the same reason as in the first embodiment.

The interface circuit 201 comprises a bias circuit 211 and an inverter type amplifier main body 212, and an input node 214 of the amplifier main body 212 and an output node 215 of the bias circuit 211 are connected via a resistor 213. Has been done. The input node 214 of the amplifier main body 212 has a P-channel type switch M between the power supply voltage VDD and the input node 214.
The OSFET 216 is coupled, and an N-channel type switch MOSFET 217 is connected to the ground potential GND.

The bias circuit 211 is composed of a P-channel type MOSFET 219 and an N-channel type MOSFET 220 connected in series and has an output 215 shorted to the input of the inverter, and the inverter and the power supply voltage VDD. It is composed of a power-down P-channel switch MOSFET 218 connected between them and a power-down N-channel switch MOSFET 221 connected between the inverter and the ground potential GND. The switch MOSFET 218 is switch-controlled by an inverted signal PON * of the power-on control signal PON. The gate of the switch MOSFET 221 is connected to the power supply voltage VDD.

The inverter type amplifier 212 is composed of a P-channel type MOSFET 223 and an N-channel type MOSFET 224 connected in series and has an input connected to the node 214 and an output connected to the node 204. And its inverter and power supply voltage VD
It comprises a power-down P-channel type switch MOSFET 222 connected to D and a power-down N-channel type switch MOSFET 225 connected between the inverter and the ground potential GND. The gate of the switch MOSFET 222 is coupled to the ground potential GND, and the switch MOSFET 225 is switch-controlled by the power-on control signal PON.

The input interface circuit 201 of this embodiment
Then, the input signal Vin is input from the input terminal 203 to the capacitor 2
02 to the node 214 of the amplifier. When the input interface circuit 11 is in the power-on state, the DC potential of the node 214 is biased to the same potential as that of its output node 215 by the bias circuit 2115. This bias voltage is the inverter type amplifier 21.
The circuit characteristic of the bias circuit 211 is determined so as to be equal to the voltage when the input and output of 2 are short-circuited. Therefore, the operation as the inverter amplifier in the input interface circuit 201 can be utilized as an amplifier similar to the self-biased inverter amplifier.

The switch control circuit 207 is a MOSFE.
Switch control of T216 and 217. The switch control circuit 207 includes a 2-input NAND gate 230 whose output is coupled to the gate of the MOSFET 216, and a MOS.
Includes a two-input NAND gate 232 coupled to the gate of FET 217. The power-on control signal PON is commonly supplied to one input of the NAND gates 230 and 232. When the power-on signal PON is low level, that is, in the power-down state, both NAND gates 230,
The output of 232 is fixed to high level. This causes MOSFET 217 to be constantly turned on, forcing the level of node 214 to a low level.

The outputs of the 2-input NOR gate 233 and the 2-input NAND gate 234 are coupled to the other inputs of the NAND gates 230 and 232. NOR Gate 233
And node 208 at one input of NAND gate 234.
Signal is inverted by the inverter 231 and supplied in common. Further, the NAND gate 234 and the NOR gate 23.
The other input of 3 is supplied with the timer signal PS and its inverted signal PS *. The timer signal PS is a control signal that is kept at the high level only for a certain period after the power-on control signal PON is changed from the low level (power down state) to the high level. When the timer signal PS is low level and its inverted signal PS * is high level while the power-on signal PON is high level, the output of the NAND gate 230 is fixed to high level and the output of the NAND gate 232 is fixed to low level. Therefore, the power-on control signal P
In a period in which ON is set to the high level and the timer signal PS is set to the low level, both MOSFETs 216, 2
17 is controlled to a cutoff state. In this state, both MOSFETs 216 and 217 function as an input protection diode.

When the power-on signal PON is set to the high level and the timer signal PS is set to the high level, the MOSFETs 216 and 217 are complementarily switch-controlled in accordance with the level of the node 208 during that period. When the node 208 is at the high level, the MOSFET 216 is turned on to try to invert the logic level of the node 208, and when the node 208 is at the low level, the MOSFET 217 is turned on to invert the logic level of the node 208. And Due to this negative feedback action, the node 214 is promptly forced to a predetermined bias level after power-on. In other words, node 204 is immediately biased to the level of the operating point of inverter amplifier 212 after power on.

When power-down is performed in this embodiment, the power-on control signal PON is controlled to a low level and its inverted signal PON * is controlled to a high level. This allows
The MOSFET 218 in the bias circuit 211 is turned off, and the MOSFET 225 in the inverter type amplifier main body 212 is controlled to be turned off. As a result, the potentials of the output node 215 of the bias circuit 211 and the input node 214 of the amplifier 212 are set to low level,
The potential of the output node 204 of the amplifier body 212 is fixed to the high level. In this state, the bias circuit 211
In addition, no current penetrating path is formed in the inverter type amplifier main body 212. Further, when power down is instructed, the MOSFET 217 is turned on in synchronization with this, so that the node 214 is also forced to the low level. Since the node 214 can be forced to a low level at a higher speed than the bias circuit 211 alone, a power-down state can be achieved at a higher speed, which also contributes to low power consumption.

When the power-down state is changed to the power-on state to enable the input operation, the power-on control signal PON is set to the high level and the inverted signal PON * thereof is set to the low level, whereby the MOSF of the bias circuit 211 is set.
The ET 221 turns on together with the MOSFET 218, and the MOSFET 2 of the inverter amplifier 106
22 is turned on together with the MOSFET 225 to enable the normal operation of amplifying the input signal Vin and outputting it to the terminal 210.

Further, when the power-down state is changed to the power-on state, the timer signal PS is set to the high level for a predetermined period in synchronization with the power-on signal PON being set to the high level. In this state, if the potential of the input 214 of the amplifier 212 is lower than the bias voltage for normal operation (voltage set as the operating point of the amplifier main body 212), the potentials of the nodes 204 and 208 are set to the high level. As a result, the MOSFET 216 is turned on and the MOSFET 217 is turned off, so that the node 2
The potential of 14 is raised. On the contrary, when the potential of the node 214 is higher than the bias point of the normal operation, the potentials of the node 204 and the node 208 are set to the low level, so that the MOSFET 217 is turned on and the MOSF is turned on.
The ET 216 is turned off and the potential of the node 214 is lowered. By this negative feedback operation, the level of node 214, which was forced to the level of ground potential GND in the power down state, is set to the bias level of the normal operation immediately after the power on state. Therefore, even if the coupling capacitor 202 has a large capacity, the power-on operation can be completed at high speed.

According to the above embodiment, there are the following effects. [1] Inverter-type amplifier 106 (212) is provided with power-down switches 114, 117 (222, 225), and bias circuit 105 (211) is provided separately from amplifier 106 (212). Since the bias voltage is applied to the input node 108 (214) of the amplifier 106 (212) via the dance element 107 (213), the inverter amplifier 106 (212) and the bias circuit 105 (211) are different circuits. And this
Since the feedback resistance of the self-bias type and the output impedance of the amplifier body are separated from each other, the output impedance of the inverter amplifier can be increased to reduce the current consumption in the power-on state. Becomes

[2] Further, the inverter type amplifier 106
Since (212) and the bias circuit 105 (211) can be connected by the high impedance element 107 (213), the impedance seen from the input end can be increased and a high-band frequency characteristic can be obtained.

[3] Power provided to each of the amplifier 106 (212) and the bias circuit 105 (212)
Down switch MOSFETs 113, 114 (22
1, 222) is turned off to input terminal 1
The output 10 regardless of the input potential of 03 (203)
Since the potential of 4 (210) can be fixed, power down for reducing unnecessary current becomes possible.

[4] Switch MOSFETs 216 and 217 are provided at the input node 214 of the amplifier 212, and the switch MOSFETs are provided for a predetermined period in synchronization with the power-on instruction.
Since the switches 216 and 217 perform complementary switch operation in a negative feedback manner based on the output level of the amplifier 212, the level of the node 214 biased to the power supply voltage VDD in the power-down state is changed to the normal operation bias immediately after the power-on instruction. Be leveled. Therefore, the power-on operation can be speeded up. Moreover, coupling capacitor 2
Even if 02 has a large capacity, it is possible to compensate for the speedup of the power-on operation.

[5] When there is an instruction from the power-on state to the power-down state, the MOSFET 217 turns on and the MOS is turned on.
Since the FET 216 is fixed in the off state, the node 21
4 can be performed at a higher speed than the case where the bias circuit 211 alone is used to force 4 to a low level. A power-down state can be achieved at high speed, which also contributes to low power consumption.

[6] During the period when the power-on control signal PON is set to the high level and the timer signal PS is set to the low level, in other words, in the state where the amplifier can perform the amplification operation, the MOSFETs 216 and 217 are controlled to the cut-off state. Therefore, in this state, both MOSFE
T216 and 217 function as an input protection diode.

FIG. 3 shows an input interface circuit 301 according to the third embodiment of the present invention. The input interface circuit 301 shown in the figure has a pair of operating power supplies VD.
An amplifier main body 302 and a bias circuit 3 formed by a first CMOS inverter arranged between D and GND
With 03. The bias circuit 303 includes a second CMOS inverter 304 having substantially the same characteristics as the amplifier main body 302, and an N-channel switch MO that selectively shorts the input and output of the second CMOS inverter.
The SFET 305 and the switch MOSFET 305 are complementarily switched to operate the second CMOS inverter 304.
And an N-channel type switch MOSFET 306 arranged between the input and the ground potential GND.
A resistor 307 as an impedance element is provided between the output of the CMOS inverter 304 and the input of the amplifier body 302.
Is provided. Further, a P-channel type charge MOSFET 310 and N
A channel type discharge MOSFET 311 is coupled. The control of the MOSFET is performed by the control circuit 311. The control circuit inputs the power-on control signal PON and the timer signal PS and outputs internal control signals 320 to 322. In the power-down state, control signal 320 is low and control signals 321 and 322 are low, which forces the input of amplifier opposite 302 high. When the power-on is instructed, the control signal 32
0 is set to a high level, and the bias circuit 303 outputs the level of the operating point of the amplifier body 303. At this time, the control signal 3 is set for a certain period immediately after the power-on is instructed.
21 and 322 are output signals of the amplifier main body 302. As a result, the input of the amplifier main body 302 is quickly brought to a predetermined bias level. After that, the control signal 321 is set to the low level and the control signal 322 is set to the high level to bring both MOSFETs 310 and 311 into the cut-off state. Even with such fairness, it is possible to obtain the same effect as in the above embodiment.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the input interface circuit used for the interface with the transmission / reception LSI in the digital codeless signal processing LSI is taken as an example here, but the present invention is not limited to this. However, it is effective for an interface between two circuits having different power supply voltages. Further, although the embodiment shown here is a CMOS circuit, the present invention is not particularly limited to this, and for example, an NMOS,
It can also be realized using devices such as PMOS, BiP, and GaAs. Further, in this embodiment, the signal is a digital signal, but the circuit according to the present invention is also effective for an analog signal and is not particularly limited. In addition, in this embodiment, the bias circuit and the amplifier are connected by a resistance element.
On resistance, external resistance, or the like may be used and is not particularly limited. Further, also in the embodiment of FIG.
The SFET 120 can be adopted. Further, a circuit in which an input protection element (resistor or the like) is added to the input of the amplifier can be adopted.
However, this protection element may be on the input side, the amplifier side, or both of them with respect to the bias point. Further, the bias circuit can be replaced with a circuit different from the amplifier main body, for example, a circuit in which a power supply is divided by resistors. Further, the amplifier main body 106 of the above embodiment
Low power consumption can be further promoted by adding a level shift element to the power supply side to each of (212) and the bias circuit 105 (211) to limit the operating voltage of the inverter. As the level shift element, for example, a diode-connected MOSFET whose gate and drain are short-circuited can be adopted. Further, the timer signal PS in the above embodiment is not limited to a signal formed by using a so-called timer, but may be formed by a circuit using a gate delay using an appropriate combination circuit or a sequential circuit.

[0046]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the feedback resistor and the output impedance of the amplifier body can be separated by using the inverter type amplifier body and the bias circuit as separate circuits. This increases the output impedance of the inverter,
It becomes possible to reduce the current, and by connecting the two with a high impedance element, the impedance seen from the input end can be increased and a frequency characteristic in a high band can be obtained. By controlling on / off of the power down switch transistors provided in the amplifier main body and the bias circuit, the output potential of the amplifier can be fixed regardless of the potential of the input terminal of the amplifier. Contributes to power consumption. The power-on state can be achieved at a high speed by controlling the discharge element and the charge element provided at the input end of the amplifier body by negative feedback for a fixed period immediately after the power-on instruction. Furthermore, the power down state is set by turning on either the discharge element or the charge element capable of outputting the level forcing the input of the first inverter by the bias circuit at the time of power down in synchronization with the power down instruction. Can be achieved fast.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input interface circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an input interface circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an input interface circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 101 Input Interface Circuit 102 Coupling Capacitor 105 Bias Circuit 106 Inverter Amplifier Main Body 107 Resistor 110 Power Down PMOS Switch 111 Inverter PMOS 112 Inverter NMOS 113 Power Down NMOS switch 114 Power-down PMOS switch 115 Inverter PMOS 116 Inverter NMOS 117 Power-down NMOS switch 201 Input interface circuit 205 Inverter 206 Inverter 207 Switch control circuit 209 Inverter 211 Bias circuit 212 Inverter type amplifier main body 213 Resistor 216 Power on power down PMOS switch 217 Power on power down NMOS switch 218 Power dow PMOS switch 219 Inverter PMOS 220 Inverter NMOS 221 Power-down NMOS switch 222 Power-down PMOS switch 223 Inverter PMOS 224 Inverter NMOS 225 Power-down NMOS switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuro Furukawa 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (9)

[Claims] 1. An amplifier body having a first inverter and a first power-down switch transistor connected in series between a pair of operating power supplies, and a bias circuit for forming a voltage at an operating point of the amplifier body. An inverter amplifier, comprising: an impedance element arranged in a connection path between the output terminal of the bias circuit and the input terminal of the first inverter. 2. An amplifier main body having a first inverter and a first power-down switch transistor connected in series between a pair of operating power supplies, and a circuit element having substantially the same characteristics as the amplifier main body. A bias circuit having a second inverter and a second power-down switch transistor connected in series between the pair of operating power supplies, wherein the input and output of the second inverter are short-circuited; An inverter type amplifier comprising: an output element of the second inverter and an impedance element arranged in a connection path between the input terminal of the first inverter and the input terminal of the first inverter. 3. The first and second power-down switch transistors in the ON state are first and second.
3. The inverter type amplifier according to claim 2, which is a constant current source for supplying a predetermined operating current to the inverter. 4. A level shift element is provided to each of the first power supply and the second power supply and the other power supply different from the one power supply to which the first power down switch element is connected. The inverter type amplifier according to claim 2 or 3, characterized in that. 5. A charge element and a discharge element are coupled to the input terminal of the first inverter, and the input level of the first inverter is set based on the output level of the first inverter in a predetermined period immediately after power-on. The inverter type amplifier according to any one of claims 2 to 4, further comprising a control circuit for switch-controlling the discharge element and the charge element so as to perform negative feedback control. 6. The control circuit turns off the charge element and the discharge element after a lapse of a predetermined period immediately after the power is turned on, and enables the charge element and the discharge element to operate as an input protection diode. The inverter type amplifier according to claim 5, wherein the inverter type amplifier is provided. 7. A high-impedance element is connected in parallel to the high-impedance element, and a bypass transistor, which is turned on for a certain period of power-on, is provided. Inverter type amplifier described. 8. An amplifier main body composed of a first inverter arranged between a pair of operating power supplies, a second inverter having substantially the same characteristics as the amplifier main body, and a second inverter of the second inverter. A first switch transistor that selectively short-circuits the input and the output, and a second switch transistor that is switched complementarily to the first switch transistor and that is arranged between the input of the second inverter and one of the power supplies. A bias circuit including a switch element; and an impedance element arranged in a connection path between the output terminal of the second inverter and the input terminal of the first inverter. Inverter type amplifier. 9. A charge element and a discharge having different conductivity types are coupled to the input terminal of the first inverter, and the output of the first inverter is connected to the charge element and the discharge element during a predetermined period immediately after power-on. 9. The inverter type amplifier according to claim 8, further comprising a control circuit which supplies the control electrode with the control electrode and controls the charge element and the discharge element to be in an off state in other periods.