JPH07202037A - Storage device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a low consumption power type storage device capable of high speed rewriting, and its manufacturing method. CONSTITUTION:On a semiconductor layer 11, a first barrier layer 14 whose electron affinity is smaller than that of the layer 11 is formed. A channel part 15 is formed in the semiconductor layer 11 in the vicinity of the juction interface between the first barrier layer 14 and the semicondctor layer 11. A tunnel junction part 21 constituted of a first conducting layer 16, a tunnel barrier layer 17 and a second conducting layer 18, and a capacitor part 22 constituted of the second conducting layer 18, a second barrier layer 19 and a third conducting layer 20 are formed on the first barrier layer 14 between a source electrode S and a drain electrode D. A control electrode CG is formed on the third conducting layer 20. Via the tunnel barrier layer 17, electrons tunnel between the first conducting layer 16 and the second conducting layer 18, and the storage state is defined on the basis of whether electric charges are much in the first conducting layer 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device for writing and reading information and a method for manufacturing the memory device.

[0002]

2. Description of the Related Art In recent years, the storage capacity of a storage device has been remarkably increased, and a D-RA using a MOS-FET is used.
Among M, S-RAM, EEPROM, etc., those having a storage capacity of 1 Gbit are becoming targets for development.
In such a storage device, in the field of non-volatile memory, rewritable EEPROMs and flash memories of the type that accumulates charges in a floating gate have been actively developed, and replacement of hard disks is aimed at. .

[0003]

However, in the storage device of these nonvolatile memories, for example, in the case of EEPROM, the SiO ₂ layer is used as the tunnel barrier layer between the channel layer made of Si and the floating gate, for example. Therefore, the barrier height becomes high in the bonding of Si and SiO ₂ . Therefore, information cannot be rewritten unless a fairly high voltage is applied to the floating gate, and the time required for rewriting becomes long. Therefore, the limit has come to be seen in terms of low power consumption and high speed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a low-power-consumption memory device that can be rewritten at high speed and a manufacturing method thereof.

[0005]

A non-volatile memory using a compound semiconductor instead of Si or the like used in a conventional semiconductor memory device has not been researched and developed so far, but a heterojunction of a compound semiconductor is used. By forming a tunnel barrier, the energy band shape of the barrier can be changed almost freely, so it is considered promising for achieving low power consumption and high speed.

Further, it is considered that by utilizing the Coulomb blockade phenomenon in a minute tunnel junction, it is possible to realize a memory element suitable for miniaturization of the element as well as low power consumption and high speed. The Coulomb blockade phenomenon will be outlined below with reference to FIGS. 1 and 2 (LSKuzmin et.al., "Single-Electron Charging Effe.
cts in One-Dimensional Arrays of Ultrasmall Tunnel
Junctions ", Phys. Rev. Letts. 62 p. 2539 (1989)).

As shown in FIG. 1A, the voltage V is applied to the minute tunnel junction portion 1 and the charge Q is accumulated. When the junction capacitance C of the minute tunnel junction portion 1 becomes extremely small, the amount of change in electrostatic energy when one electron tunnels (up to e ² / 2C) becomes large enough to overcome the thermal disturbance. That is, the junction capacitance C is C = Aε / W, where A: junction area W: thickness of barrier layer ε: permittivity of barrier layer, and therefore one electron tunnels over the electrostatic energy. The condition is that the junction capacitance C is C <e ² / 2kT, where e: elementary charge k: Boltzmann's constant T: temperature. That is, the bonding area A must satisfy the condition of A <We2 / 2εkT.

In the minute tunnel junction portion 1 satisfying such conditions, as shown in the current-voltage characteristic graph of FIG. 1B, when the voltage V applied to the minute tunnel junction portion is small, that is, V When <e / 2C, the tunnel is an energy loss, so the current I does not flow, and when a voltage V higher than that is applied, that is, when V> e / 2C, the current I flows out. Occur. This is called the Coulomb blockade phenomenon.

Further, as shown in FIG. 2A, when two minute tunnel junctions 2 and 3 are connected in series and a voltage V is applied between them, the current I does not flow at first, and further the voltage V When the value is increased, one electron will enter the tunnel junction region, and the current I will flow. However, in order to allow another electron to enter, it is necessary to apply a larger voltage V. Holds a constant current value. Therefore, as shown in the graph of FIG. 2B, it has a step-like current-voltage characteristic. This phenomenon is also a type of Coulomb blockade phenomenon and is called the Coulomb-Staircase phenomenon.

Based on such an idea, the present inventors have
A storage device using a compound semiconductor capable of freely changing the energy band shape of the tunnel barrier by hetero coupling, and a large change in electrostatic energy can be obtained with a small change in charge amount of one or two electrons. Utilizing the Coulomb blockade phenomenon in micro tunnel junctions, we pursued the development of a memory device that uses this as a control gate, reducing power consumption, increasing processing speed,
In addition, a memory device that enables miniaturization of elements has been conceived.

The principle of the present invention will be described below with reference to FIGS.
Will be explained. 3A is a sectional view showing the first memory device according to the present invention, FIG. 3B is a circuit diagram thereof, and FIG.
5A and 5B are energy band diagrams for explaining the operation of the first memory device in FIG. 3, and FIGS. 6A and 6B are diagrams respectively. 3 is a graph showing current-voltage characteristics of the first memory device of FIG.

In FIG. 3, the semiconductor layer 1 is formed on the substrate 10.
1 is formed. A source region 12 and a drain region 13 are formed opposite to each other on the surface of the semiconductor layer 11,
Further, a source electrode S and a drain electrode D are formed on the source region 12 and the drain region 13 in ohmic contact with each other. Further, a first barrier layer 14 having an electron affinity lower than that of the semiconductor layer 11 is formed on the semiconductor layer 11. Since the semiconductor layer 11 near the junction interface between the first barrier layer 14 and the semiconductor layer 11 has conductivity, the channel portion 15 connecting the source electrode S and the drain electrode D is formed.

Further, a first conductive layer 16 is formed on the first barrier layer 14 between the source electrode S and the drain electrode D, and the first conductive layer 16 is formed on the first conductive layer 16. Tunnel barrier layer 17 having a smaller electron affinity than the conductive layer 16 of
The second conductive layer 18 is formed via. Also,
A third conductive layer 20 is formed on the second conductive layer 18 via a second barrier layer 19 having a smaller electron affinity than the second conductive layer 18.

Therefore, the tunnel barrier layer 17 and the first and second conductive layers 16 and 18 that sandwich the tunnel barrier layer 17 constitute a tunnel junction portion 21, and the second barrier layer 19 and the second and third sandwiching the barrier layer 19 therebetween. The conductive layers 18 and 20 form a capacitor section 22. Further, the control gate electrode CG is formed on the third conductive layer 20 by ohmic contact.

Next, the operation of the memory element of FIG. 3 will be described with reference to the energy band diagrams of FIGS. 4 and 5. Figure 3
As shown in (b), the source electrode S of the memory element is grounded. When a positive voltage V _CG is applied to the control gate electrode CG, the energy band diagram of the memory element is shown in FIG.
As shown in (a).

At this time, some of the electrons existing in the first conductive layer 16 tunnel through the tunnel barrier layer 17 and move to the second conductive layer 18, as shown by the arrow in the figure. Incidentally, the first and second barrier layers 14 of this memory element,
Since the layer thickness of 19 is relatively thick as shown in the drawing, the first conductive layer 16 to the second conductive layer 18 are formed.
During the tunnel to the first conductive layer 1 from the semiconductor layer 11
The tunnel to 6 and the tunnel from the second conductive layer 18 to the third conductive layer 20 are blocked.

In this state, when the voltage V _CG applied to the control gate electrode CG is returned to 0, the charge in the first conductive layer 16 decreases from the initial state, as shown in FIG. Correspondingly, the electron concentration of the channel portion 15 in the semiconductor layer 11 is increased, and an electron storage layer is newly formed or the thickness of the electron storage layer is increased. Therefore, when the voltage V _SD is applied between the source electrode S and the drain electrode D in this state, a drain current I _D larger than that in the initial state flows. And this state is stored information "1"
And

On the other hand, the source electrode S of the memory element is grounded.
The control gate electrode CG to a negative voltage V _CGIs applied,
The energy band diagram of the storage element is shown in FIG.
Become so. At this time, it was present in the second conductive layer 18.
Some of the electrons are tunneled, as shown by the arrows in the figure.
Tunnel through barrier layer 17 and move to first conductive layer 16
The first conductive layer 16 to the semiconductor layer 11.
From the third conductive layer 20 to the second conductive layer 18
The tunnel is blocked.

In this state, when the voltage V _CG applied to the control gate electrode CG is returned to 0, the charge in the first conductive layer 16 increases from the initial state, as shown in FIG. 5 (b). Corresponding to this, the electron concentration of the channel portion in the semiconductor layer 11 decreases and the electron storage layer disappears,
Alternatively, the thickness of the electron storage layer becomes thin. Therefore, in this state, when the voltage V _SD is applied between the source electrode S and the drain electrode D, the drain current I _D does not flow, or only the drain current I _D smaller than that in the initial state flows. Then, this state is set as the storage information “0”.

Next, this operation is performed according to the current-voltage characteristic of FIG.
It demonstrates using the graph which shows. As shown in FIG. 6 (a)
So that the positive voltage V_CGApplied
In this case, the source-drain voltage V_SDBy applying
A large drain current I corresponding to the stored information “1”._D
Flows. On the other hand, a negative voltage V is applied to the control gate electrode CG. _CGTo
When applied, the source-drain voltage V_SDApplication of
Also, a small drain corresponding to the stored information “0”
Current I_DOnly flows.

Further, as shown in FIG. 6B, when the relationship between the drain current _ID and the applied voltage V _CG to the control gate electrode CG is taken, the applied voltage V _CG to the control gate electrode CG is obtained.
Since a hysteresis loop is drawn with respect to the change of, the stored information "1" or "0" can be held depending on the magnitude of the drain current I _D. However, since the stored information changes depending on the tunnel that passes through the tunnel barrier layer 17, it is necessary to refresh the stored information.

From the above, the above-mentioned problem is solved by the substrate, the semiconductor layer formed on the substrate, and the source electrode and the drain electrode which are formed on the semiconductor layer so as to face each other and are in ohmic contact with the semiconductor layer. A first conductive layer formed on the semiconductor layer sandwiched between the source electrode and the drain electrode via a first barrier layer having a smaller electron affinity than the semiconductor layer; A second conductive layer formed on the first conductive layer via a tunnel barrier layer having an electron affinity lower than that of the first conductive layer;
A third conductive layer formed on the second conductive layer via a second barrier layer having an electron affinity lower than that of the second conductive layer, and ohmic-bonded on the third conductive layer. A gate electrode formed by controlling the voltage applied to the gate electrode, and controlling the voltage applied to the gate electrode via the tunnel barrier layer.
Charge between the second conductive layer and the second conductive layer,
A current flowing between the source electrode and the drain electrode is increased or decreased by increasing or decreasing the electron concentration formed in the vicinity of the junction interface of the semiconductor layer with the first barrier layer due to the change of the charge amount in the first conductive layer. Is achieved by a semiconductor memory device.

Next, the second storage device according to the present invention will be described. 7A is a sectional view showing a second memory device according to the present invention, FIG. 7A is a circuit diagram thereof, FIG.
7B is a graph showing current-voltage characteristics of the second memory device of FIG. 7, respectively. The same components as those of the first storage device shown in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 7, the semiconductor layer 1 is formed on the substrate 10.
1, a source region 12 and a drain region 13 are formed opposite to each other on the surface of the semiconductor layer 11, and a source electrode S and a drain electrode D are ohmic on the source region 12 and the drain region 13, respectively. It is formed by joining. A first barrier layer 14 having an electron affinity lower than that of the semiconductor layer 11 is formed on the semiconductor layer 11, and the first barrier layer 14 is formed.
A channel portion 15 that connects the source electrode S and the drain electrode D is formed in the semiconductor layer 11 near the junction interface with.

Further, a first conductive layer 23 is formed on the first barrier layer 14 between the source electrode S and the drain electrode D, and the first conductive layer 23 is formed on the first conductive layer 23. Tunnel barrier layer 17 having a smaller electron affinity than the conductive layer 23 of
The second conductive layer 24 is formed via. Also,
A third conductive layer 20 is formed on the second conductive layer 24 with a second barrier layer 19 having an electron affinity smaller than that of the second conductive layer 24 interposed therebetween.

Here, the first and second conductive layers 23, 24
Are extremely finely formed, and the junction area A of each of the first and second conductive layers 23 and 24 and the tunnel barrier layer 17 is A <We ² / 2εkT, where W: of the tunnel barrier layer 17. It is characterized in that it is sufficiently small to satisfy the relationship of thickness e: elementary charge ε: permittivity of tunnel barrier layer 17 k: Boltzmann constant T: temperature.

That is, the junction area A needs to satisfy the condition of e ² / 2C >> kT, and the voltage V _CG needs to be large enough to satisfy the condition of V _{CG to} e / 2C. In order to increase the operation margin and enable operation at a high temperature, it is necessary to form a fine junction with an effective junction area A of 100 nm ² or less when the operation temperature is, for example, 300K. However, for example, the temperature is 4.2K
Considering the operation at 0.1 μm ^2, about 0.1 μm ² is sufficient.

In this way, the tunnel barrier layer 17 and the first and second conductive layers 23 and 24 sandwiching the tunnel barrier layer 17 constitute an extremely fine tunnel junction 25, and the second barrier layer 19 and the second barrier layer 19 sandwiching it. The third conductive layers 24 and 20 form a capacitor section 26. Furthermore, the third
The control gate electrode CG is formed on the conductive layer 20 by ohmic junction.

Next, the operation of the memory element of FIG. 7 will be described using the graph showing the current-voltage characteristic of FIG. Figure 7
As shown in (b), the source electrode S of the memory element is grounded. Then, V _CG > e / 2C to the control gate electrode CG, where C: When a positive voltage V _CG which is the junction capacitance C of the tunnel junction 25 is applied, the electrons existing in the first conductive layer 23 due to the Coulomb blockade phenomenon. Of the first barrier layer 1 tunnels through the tunnel barrier layer 17 and moves to the second conductive layer 24.
Since the layers 4 and 19 are thick, the tunnel from the semiconductor layer 11 to the first conductive layer 23 and the second conductive layer 24 to the third conductive layer 23 are formed.
Tunnels to the conductive layer 20 are blocked. Therefore, when the applied voltage V _CG of the control gate electrode CG returned to 0, the charge in the first conductive layer 23 is reduced from the initial state, the electron concentration in the channel portion 15 in the semiconductor layer 11 corresponding thereto To increase.

Therefore, when the voltage V _SD is applied between the source electrode S and the drain electrode D in this state, as shown in FIG. 8A, the drain current I _D larger than that in the initial state is obtained.
Flows. That is, the state corresponds to the stored information “1”. On the other hand, when the source electrode S of the memory element is grounded and a negative voltage V _CG of V _CG <−e / 2C is applied to the control gate electrode CG, it is present in the second conductive layer 24 due to the Coulomb blockade phenomenon. Some of the electrons tunnel through the tunnel barrier layer 17 and move to the first conductive layer 23, and at the same time, tunnel from the first conductive layer 23 to the semiconductor layer 11 and from the third conductive layer 20 to the second conductive layer 20. The tunnel to the conductive layer 24 is blocked. Therefore, when the applied voltage V _CG of the control gate electrode CG returned to 0, the charge in the first conductive layer 23 is increased from the initial state, the electron concentration in the channel portion 15 in the semiconductor layer 11 corresponding thereto Decrease.

Therefore, when the voltage V _SD is applied between the source electrode S and the drain electrode D in this state, as shown in FIG. 8A, the drain current I _D smaller than that in the initial state is applied.
Only flows. That is, the state corresponds to the stored information “0”. The control gate electrode applied voltage V _CG to CG is, -e / 2C <when a V _CG <e / 2C is a Coulomb blockade phenomenon, electrons tunnel barrier layer present on the first conductive layer 23 17
Does not tunnel to the second conductive layer 24, and the electrons present in the second conductive layer 24 do not tunnel through the tunnel barrier layer 17 to the first conductive layer 23. Therefore, the state before that is retained.

Therefore, the relationship between the drain current I _D and the voltage V _CG applied to the control gate electrode CG is shown in FIG. 8 (b).
, The applied voltage V to the control gate electrode CG
Draw a hysteresis loop for changes in _CG . That is,
When the voltage V _CG applied to the control gate electrode CG is gradually increased from negative in the state corresponding to the stored information “0”, the voltage V _CG is changed from negative to positive in the range of V _CG <e / 2C. However, the stored information “0” is held while the drain current I _D remains small.
Then, when the applied voltage V _CG becomes V _CG > e / 2C, the drain current I _D increases and the stored information “1”
Transition to the state of.

On the contrary, when the applied voltage V _CG is gradually decreased from the state corresponding to the stored information "1", the voltage V _CG is positive to negative in the range of V _CG > -e / 2C. Even if the drain current I _D becomes large, the stored information “1” is retained. However, when the applied voltage V _CG becomes V _CG <−e / 2C, the drain current I _D decreases and the stored information “1” is stored. 0 "
Transition to the state of. Therefore, the stored information “1” or “0” can be held depending on the magnitude of the drain current I _D.

In the first and second memory devices according to the present invention, the tunnel barrier portion may be formed by reducing the layer thickness of part or all of the first barrier layer 14. The operation of the storage device at this time is, for example, the first storage device of the first storage device.
The case where the tunnel barrier portion is formed in the barrier layer 14 will be described. By grounding the source electrode S and applying a bias to the drain electrode D, the semiconductor layer 1
Electrons existing in the channel portion 15 in 1 are made into hot electrons and moved to the first conductive layer 16 through the tunnel barrier portion. The control gate electrode becomes V _CG> e / 2C the CG positive voltage V _CG, or V _CG <when a negative voltage is applied to V _CG consisting -e / 2C, the Coulomb blockade phenomenon, through the tunnel barrier layer 17 Since electrons tunnel between the first conductive layer 23 and the second conductive layer 24 to change the charge amount of the first conductive layer 23, it is possible to rewrite the stored information.

In view of the above, the above-mentioned problem is solved by the substrate, the semiconductor layer formed on the substrate, and the source electrode and the drain electrode which are formed on the semiconductor layer so as to face each other and make ohmic contact with the semiconductor layer. A first conductive layer formed on the semiconductor layer sandwiched between the source electrode and the drain electrode via a first barrier layer having a smaller electron affinity than the semiconductor layer; A second conductive layer formed on the first conductive layer via a tunnel barrier layer having an electron affinity lower than that of the first conductive layer;
A third conductive layer formed on the second conductive layer via a second barrier layer having an electron affinity lower than that of the second conductive layer, and formed on the third conductive layer. A gate electrode, controlling a voltage applied to the gate electrode, and via the tunnel barrier layer, the first conductive layer and the second conductive layer.
Electric charge is transferred between the first conductive layer and the second conductive layer to increase or decrease the electron concentration formed in the vicinity of the junction interface of the semiconductor layer with the first barrier layer. In the semiconductor memory device controlling the current flowing between the source electrode and the drain electrode, the junction area A of each of the first and second conductive layers and the tunnel barrier layer is A <We ² / 2εkT , W: thickness of barrier layer e: elementary electric charge ε: dielectric constant of barrier layer k: Boltzmann constant T: temperature, which is achieved by a semiconductor memory device.

[0036]

In the first memory element according to the present invention, the memory state is defined on the basis of the amount of charges in the first and second conductive layers 16 and 18 sandwiching the tunnel barrier layer 17, especially in the first conductive layer 16. Therefore, the stored information can be read according to the magnitude of the drain current _ID flowing between the source electrode S and the drain electrode D. In reading the data, the electrons travel in the channel portion 15 at a very high speed and the traveling time is very short, so that the reading speed is increased. Further, since the tunneling time for the electrons to pass through the tunnel barrier layer 17 is very short, the rewriting of stored information becomes very fast.

In the second memory element according to the present invention, as in the case of the first memory element, the amount of charges in the first and second conductive layers 23, 24, especially the first conductive layer 23 is large. The storage state can be defined on the basis of, and the storage information can be read according to the magnitude of the drain current _ID flowing between the source electrode S and the drain electrode D. In reading the data, the electrons travel in the channel portion 15 at a very high speed and the traveling time is very short, so that the reading speed is increased. Further, since the tunneling time for the electrons to pass through the tunnel barrier layer 17 is very short, the rewriting of stored information becomes very fast.

Moreover, since the junction area A between the first and second conductive layers and the tunnel barrier layer is sufficiently small that A <We ² / 2εkT, the Coulomb blockade phenomenon occurs and the retention of stored information. Is performed based on the amount of change in electrostatic energy (.about.e2 / 2C) when one electron tunnels through the tunnel barrier layer 17 and when it does not. Since this amount of change is larger than the thermal disturbance, The retention time of the stored information is almost semi-permanent, and refreshing for retaining the stored information is unnecessary. Further, as for power consumption, the memory holding mechanism uses an electrostatic force due to the Coulomb force, so that a small amount of current flows at the time of rewriting / reading, and power consumption is reduced.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on illustrated embodiments. First, a first embodiment and a second embodiment corresponding to the first storage device according to the present invention will be described with reference to FIGS. 9 and 10, respectively. FIG. 9 is a sectional view showing a memory device according to the first embodiment of the present invention.

The memory device according to the first embodiment is characterized in that each component except the electrode portion is formed of a semiconductor. That is, in FIG. 9, the semi-insulating InP substrate 3
On top of the non-doped i-type InGaA with a thickness of 300 nm.
The s layer 31 is formed. This i-type InGaAs layer 3
On one surface, an n ⁺ type source region 32 and an n ⁺ type drain region 33 to which n type impurities are added are formed so as to face each other.

Further, these n ⁺ type source regions 32 and n ⁺
A P layer having a thickness of 30 nm is formed on the mold drain region 33.
A source electrode S and a drain electrode D formed of a Pd / Ge / Au composite layer in which a d layer, a Ge layer having a thickness of 40 nm, and an Au layer having a thickness of 200 nm are sequentially stacked are formed by ohmic contact. The source electrode S and the drain electrode D are P
d / Ge / Au composite layer, AuGe / Au composite layer, C
It may be formed from an r / Au composite layer or the like.

On the i-type InGaAs layer 31, an N-type InAlAs barrier layer 34 having a thickness of 50 nm and having an electron affinity lower than that of the i-type InGaAs layer 31 is formed. Therefore, the electrons supplied from the donor impurity added to the N-type InAlAs barrier layer 34 are i-type InGa.
The two-dimensional electron gas moves to the As layer 31 and accumulates in the i-type InGaAs layer 31 near the junction interface with the N-type InAlAs barrier layer 34, and the source electrode S and the drain electrode D
A two-dimensional electron channel portion 35 that connects with is formed.
Instead of the N-type InAlAs barrier layer 34, a thickness of 5
A 0 nm N-type InP barrier layer may be used.

A thickness of 10 n is formed on the N-type InAlAs barrier layer 34 between the source electrode S and the drain electrode D.
An n-type InAlAs conductive layer 36 of m is formed, and the n-type InAlAs conductive layer 36 is formed on the n-type InAlAs conductive layer 36.
I having a thickness of 20 nm, which has a smaller electron affinity than the conductive layer 36
With a thickness of 1 through the InAlAs tunnel barrier layer 37.
A 0 nm n-type InAlAs conductive layer 38 is formed. An n-type InAlAs conductive layer 40 having a thickness of 100 nm is formed on the n-type InAlAs conductive layer 38 via an i-type InAlAs barrier layer 39 having a thickness of 100 nm, which has a smaller electron affinity than the n-type InAlAs conductive layer 38. Has been formed.

Therefore, the i-type InAlAs tunnel barrier layer 37 and the n-type InAlAs conductive layers 36 and 38 sandwiching the i-type InAlAs tunnel barrier layer 37.
Form a tunnel junction, and i-type InAl
The As barrier layer 39 and the n-type InAlAs conductive layers 38 and 40 that sandwich the As barrier layer 39 form a capacitor section. Further, on the n-type InAlAs conductive layer 40, a Pd layer having a thickness of 30 nm, a Ge layer having a thickness of 40 nm and a thickness of 200 are respectively provided.
The control gate electrode CG is formed by ohmic contact with the Pd / Ge / Au composite layer in which the Au layer having a thickness of 10 nm is sequentially stacked. The control gate electrode CG is Pd / Ge / A
In addition to the u composite layer, it may be formed of AuGe / Au composite layer, Cr / Au composite layer, or the like.

The operation of the memory device according to the first embodiment shown in FIG. 9 is the same as the operation described with reference to FIGS. 4 to 6 for the first memory device according to the present invention shown in FIG. Therefore, the description is omitted. Next, a method of manufacturing the memory device shown in FIG. 9 will be described. On the semi-insulating InP substrate 30, an i-type InGaAs layer 31 having a thickness of 300 nm and a thickness of 50 nm
N-type InAlAs barrier layer 34, 10-nm-thick n-type InAlAs conductive layer 36, and 20-nm-thick i-type InAl
As tunnel barrier layer 37, 10 nm thick n-type InA
lAs conductive layer 38, 100 nm thick i-type InAlAs
Barrier layer 39 and 100 nm thick n-type InAlAs
The conductive layer 40 is sequentially stacked.

Subsequently, the n-type InAlAs conductive layer 40, i
Type InAlAs barrier layer 39, n type InAlAs conductive layer 38, i type InAlAs tunnel barrier layer 37, and n
The type InAlAs conductive layer 36 is patterned into an island shape by using a normal EB (electron beam) exposure method and dry etching. In this way, a portion corresponding to the floating gate having the tunnel junction is formed.

Then, an n-type impurity is selectively added to the surface of the i-type InGaAs layer 31 to form an n ⁺ -type source region 32 and an n ⁺ -type drain region 33 opposite to each other. Then, P is further formed on the n ⁺ type source region 32, the n ⁺ type drain region 33, and the n type InAlAs conductive layer 40.
The source electrode S, the drain electrode D, and the control gate electrode CG made of the d / Ge / Au composite layer are formed by ohmic contact with each other.

As described above, according to this embodiment, i-type InA
The storage state of "0" or "1" can be defined based on the amount of charges in the n-type InAlAs conductive layers 36 and 38, particularly the n-type InAlAs conductive layer 36 sandwiching the 1As tunnel barrier layer 37, and the source electrode can be defined. "1" or "0" stored information can be read out depending on the magnitude of the drain current _ID flowing between the S-drain electrodes D. Moreover, in reading the data, since the electrons travel in the two-dimensional electron channel portion 35 at an extremely high speed, the reading speed is also increased. In addition, since the tunneling time of electrons through the i-type InAlAs tunnel barrier layer 37 is very short,
Rewriting of stored information is also very fast.

In the first embodiment, the N type I
nAlAs barrier layer 34 and n-type InAlAs conductive layer 38
Between the n-type InAlAs conductive layer 36 and the i-type InAl
As tunnel barrier layer 37 and i-type I
nAlAs tunnel barrier layer 37 and n-type In sandwiching it
Although one tunnel junction portion composed of the AlAs conductive layers 36 and 38 is formed, the n-type InAlAs conductive layers 36 and the i-type InAlAs tunnel barrier layers 37 are alternately formed for two cycles or more, and two or more tunnels are formed. A joint may be formed. In this case, the movement of electrons in the plurality of tunnel junctions becomes complicated, but the function of a multilevel memory or the like can be exerted.

Next, a memory device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 10 is a sectional view showing a memory device according to the second embodiment. It should be noted that the same components as those of the storage device shown in FIG. The memory device according to the second embodiment is characterized in that the tunnel junction portion and the capacitor portion are formed of a metal and an insulator, respectively.

That is, in FIG. 10, as in the case of the first embodiment, a thickness of 3 is formed on the semi-insulating InP substrate 30.
A non-doped i-type InGaAs layer 31 of 00 nm is formed, and an n ⁺ -type source region 32 and an n ⁺ -type drain region 33 to which an n-type impurity is added are formed on the surface of the i-type InGaAs layer 31 so as to face each other. A Pd layer having a thickness of 30 nm, a Ge layer having a thickness of 40 nm, and a thickness of 20 are formed on the n ⁺ type source region 32 and the n ⁺ type drain region 33, respectively.
A source electrode S and a drain electrode D made of a Pd / Ge / Au composite layer in which a 0 nm Au layer is sequentially stacked are formed by ohmic contact. In addition to the Pd / Ge / Au composite layer, the source electrode S and the drain electrode D are AuGe /
It may be formed from an Au composite layer, a Cr / Au composite layer, or the like.

On the i-type InGaAs layer 31, an N-type InAlAs barrier layer 34 having a thickness of 50 nm, which has a smaller electron affinity than the i-type InGaAs layer 31, is formed. A two-dimensional electron channel portion 35 connecting the source electrode S and the drain electrode D is formed in the i-type InGaAs layer 31 near the junction interface. Instead of the N-type InAlAs barrier layer 34, an N-type InP barrier layer having a thickness of 50 nm or a thickness of 1 is used.
A 0 nm CaF ₂ barrier layer may be used.

A thickness of 10 n is formed on the N-type InAlAs barrier layer 34 between the source electrode S and the drain electrode D.
CoSi ₂ metal layer 41 m is formed, the CoSi ₂
On the metal layer 41, a CaF ₂ tunnel barrier layer 4 having a thickness of ₂ nm, which has a smaller electron affinity than the CoSi ₂ metal layer 41, is formed.
A CoSi ₂ metal layer 43 having a thickness of 10 nm is formed through In addition, on this CoSi ₂ metal layer 43,
A thickness of 50 nm is provided via the CaF ₂ barrier layer 44 having a thickness of 10 nm, which has a smaller electron affinity than the CoSi ₂ metal layer 43.
A CoSi ₂ metal layer 45 of nm is formed.

Therefore, the CaF ₂ tunnel barrier layer 42 and the CoSi ₂ metal layers 41 and 43 sandwiching it form a tunnel junction, and the CaF ₂ barrier layer 44 and the CoSi ₂ metal layers 43 and 45 sandwiching it form the tunnel junction. A capacitor section is configured. Further, on the CoSi ₂ metal layer 45, a Pd layer having a thickness of 30 nm and a G layer having a thickness of 40 nm are formed.
An e-layer and a 200 nm-thick Au layer are sequentially stacked to form Pd /
The control gate electrode CG made of a Ge / Au composite layer is formed in ohmic contact. The control gate electrode CG
May be formed of AuGe / Au composite layer, Cr / Au composite layer, etc. in addition to the Pd / Ge / Au composite layer. Alternatively, it can also be used as the CoSi ₂ metal layer 45.

The operation of the memory device according to the second embodiment shown in FIG. 10 is similar to the operation described with reference to FIGS. 4 to 6 for the first memory device according to the present invention shown in FIG. Therefore, the description is omitted. Next, a method for manufacturing the memory device shown in FIG. 10 will be described. On the semi-insulating InP substrate 30, an i-type InGaAs layer 31 having a thickness of 300 nm and a thickness of 5
0 nm N-type InAlAs barrier layer 34, thickness 10 nm
CoSi ₂ metal layer 41, 2 nm thick CaF ₂ tunnel barrier layer 42, 10 nm thick CoSi ₂ metal layer 4
3, CaF ₂ barrier layer 44 with a thickness of 10 nm, and thickness 5
A 0 nm CoSi ₂ metal layer 45 is sequentially stacked.

Subsequently, the CoSi ₂ metal layer 45, CaF ₂
The barrier layer 44, the CoSi ₂ metal layer 43, the CaF ₂ tunnel barrier layer 42, and the CoSi ₂ metal layer 41 are patterned into an island shape by using a normal EB exposure method and dry etching. In this way, a portion corresponding to the floating gate having the tunnel junction is formed. Then, i-type InG
By selectively adding an n-type impurity to the surface of the aAs layer 31,
^{The +} type source region 32 and the n ⁺ type drain region 33 are formed opposite to each other. Subsequently, these n ⁺ type source regions 3
On the 2 and n ⁺ type drain regions 33 and the CoSi ₂ metal layer 45, the source electrode S and the drain electrode D made of the Pd / Ge / Au composite layer and the control gate electrode CG are formed by ohmic contact with each other.

As described above, according to this embodiment, the first
Almost the same as in the example, CaF ₂Tunnel barrier layer
CoSi sandwiching 42₂Metal layers 48, 49, especially CoSi
₂Based on the amount of charge in the metal layer 48, “0” or
Can define the memory state of "1", source electrode
Drain current I flowing between the S-drain electrode D_DBig and small
It is possible to read "1" or "0" stored information by
Therefore, the same effect as in the case of the first embodiment can be obtained.
can do.

In the second embodiment, N-type In
Even if two or more cycles of the CoSi ₂ metal layers 41 and the CaF ₂ tunnel barrier layers 42 are alternately formed between the AlAs barrier layers 34 and the CoSi ₂ metal layers 43 to form two or more tunnel junctions. Good. Next, a third embodiment and a fourth embodiment corresponding to the second storage device according to the present invention will be described with reference to FIGS. 11 and 12, respectively.

FIG. 11 is a sectional view showing a memory device according to the third embodiment of the present invention. It should be noted that the same components as those of the storage device shown in FIG.
The memory device according to the third embodiment has the same laminated structure as that of the first embodiment, but the junction area A at the tunnel junction is extremely small so that the Coulomb blockade phenomenon occurs. It is characterized in that it has become.

That is, referring to FIG. 11, the first embodiment described above is used.
In the same manner as in the above case, a thickness of 3 is formed on the semi-insulating InP substrate 30.
A 00 nm i-type InGaAs layer 31 is formed.
N-type impurities were added to the surface of the InGaAs layer 31
n⁺Mold source regions 32 and n ⁺Type drain region 33
Is formed against⁺Mold source region 32 and
n⁺Pd / Ge / A on the mold drain region 33, respectively.
The source electrode S and the drain electrode D made of the u composite layer are turned on.
It is formed by an ohmic junction. The source electrode S and
And the drain electrode D is made of Au in addition to the Pd / Ge / Au composite layer.
Formed from Ge / Au composite layer, Cr / Au composite layer, etc.
Good.

On the i-type InGaAs layer 31, an N-type InAlAs barrier layer 34 having a thickness of 50 nm, which has a smaller electron affinity than the i-type InGaAs layer 31, is formed. A two-dimensional electron channel portion 35 connecting the source electrode S and the drain electrode D is formed in the i-type InGaAs layer 31 near the junction interface. Instead of the N-type InAlAs barrier layer 34, an N-type InP barrier layer having a thickness of 50 nm may be used.

A thickness of 10 nm is formed on the N-type InAlAs barrier layer 34 between the source electrode S and the drain electrode D.
N-type InAlAs conductive layer 46, this n-type InAlAs
I having a thickness of 20 nm, which has a smaller electron affinity than the conductive layer 46
-Type InAlAs tunnel barrier layer 37, 10-nm-thick n-type InAlAs conductive layer 47, and 100-nm-thick i having a smaller electron affinity than the n-type InAlAs conductive layer 47.
-Type InAlAs barrier layer 39 and n having a thickness of 100 nm
The type InAlAs conductive layer 40 is formed by being sequentially stacked.

Here, the n-type InAlAs conductive layers 46, 4
7 is extremely finely formed, and these n-type InAl
The junction area A of each of the As conductive layers 46 and 47 and the i-type InAlAs tunnel barrier layer 37 is A <We ² / 2εkT, where: W: thickness of the i-type InAlAs tunnel barrier layer 37 e: elementary charge ε: The i-type InAlAs tunnel barrier layer 37 is characterized in that it is small enough to satisfy the relationship of dielectric constant k: Boltzmann constant T: temperature.

That is, the junction area A is, for example, the operating temperature 30.
It must be 11.3 × 11.3 nm ² or less at 0K. However, in reality, since it is affected by the depletion layer extending from the periphery, a predetermined operation is possible even with a junction area larger than this. Thus, i-type InA
lAs tunnel barrier layer 37 and n-type InAl sandwiching the same
The As conductive layers 46 and 47 form an extremely fine tunnel junction portion, and the i-type InAlAs barrier layer 39 and the n-type InAlAs conductive layers 47 and 40 sandwiching the barrier layer 39 sandwich the i-type InAlAs barrier layer 39.
A capacitor section is configured.

Further, on the n-type InAlAs conductive layer 40, a control gate electrode C made of a Pd / Ge / Au composite layer is formed.
G is formed in ohmic contact. In addition to the Pd / Ge / Au composite layer, the control gate electrode CG includes AuGe /
It may be formed from an Au composite layer, a Cr / Au composite layer, or the like. Since the operation of the storage device according to the third embodiment shown in FIG. 11 is the same as the operation described with reference to FIG. 8 for the second storage device according to the present invention of FIG. 7, description thereof will be omitted. .

Next, a method of manufacturing the memory device shown in FIG. 11 will be described. On the semi-insulating InP substrate 30, the i-type InGaAs layers 31 and N are formed in the same manner as in the first embodiment.
Type InAlAs barrier layer 34, n type InAlAs conductive layer 46, i type InAlAs tunnel barrier layer 37, n type I
nAlAs conductive layer 47, i-type InAlAs barrier layer 3
9 and the n-type InAlAs conductive layer 40 are sequentially stacked.

Subsequently, the n-type InAlAs conductive layer 40, i
Type InAlAs barrier layer 39, n type InAlAs conductive layer 47, i type InAlAs tunnel barrier layer 37, and n
The type InAlAs conductive layer 46 is patterned into an island shape by using a normal EB exposure method and dry etching to form a floating gate corresponding portion having an extremely fine tunnel junction portion.

Then, by using a mixed solution of citric acid / hydrogen peroxide water / water as an etchant, N-type In
Selective side etching of the n-type InAlAs conductive layers 46 and 47 with respect to the AlAs barrier layer 34 is performed to obtain n-type I
The cross-sectional area of the nAlAs conductive layers 46 and 47 is 11.3 × 1.
It should be 1.3 nm ² or less. As a result, these n-type In
The junction area A between the AlAs conductive layers 46 and 47 and the i-type InAlAs tunnel barrier layer 37 is 11.3 ×.
It becomes 11.3 nm ² or less, and a minute tunnel junction satisfying the relationship of A <We ² / 2εkT is formed. However, as described above, in consideration of the influence of the depletion layer extending from the periphery, the junction area may actually be larger than this.

Subsequently, an n-type impurity is selectively added to the surface of the i-type InGaAs layer 31 to form an n ⁺ -type source region 32 and an n ⁺ -type drain region 33 opposite to each other. Then, P is further formed on the n ⁺ type source region 32, the n ⁺ type drain region 33, and the n type InAlAs conductive layer 40.
The source electrode S, the drain electrode D, and the control gate electrode CG made of the d / Ge / Au composite layer are formed by ohmic contact with each other.

When an N-type InP barrier layer is used instead of the N-type InAlAs barrier layer 34, this N-type InP is used.
For selective side etching of the n-type InAlAs conductive layers 46 and 47 with respect to the barrier layer, a mixed solution of phosphoric acid / hydrogen peroxide solution / water may be used as an etchant. Further, in the above manufacturing process, when forming the floating gate corresponding portion sandwiched between the source electrode S and the drain electrode D, in consideration of mass productivity, the n-type InAlAs conductive layer 40 to the n-type InAlAs conductive layer 46 are taken into consideration. The laminated layers up to are patterned in an island shape by using a normal EB exposure method and dry etching, but the FIB method (Focused Ion Beam method;
Focused ion beam correction method) or the like may be used. In this case, correction processing up to about 10 × 10 nm ² is possible.

As described above, according to the present embodiment, the n-type InAlAs conductive layers 46 and 4 sandwiching the i-type InAlAs tunnel barrier layer 37 are formed in substantially the same manner as in the first embodiment.
7. In particular, the memory state of “0” or “1” can be defined on the basis of the amount of charges in the n-type InAlAs conductive layer 46, and the drain current I _D flowing between the source electrode S and the drain electrode _D is large or small. Can read the "1" or "0" stored information. Moreover, in reading the data, since the electrons travel in the two-dimensional electron channel portion 35 at an extremely high speed, the reading speed is also increased. Further, since the tunnel time for the electrons to pass through the tunnel barrier layer 17 is very short, the rewriting of the stored information is very fast.

Moreover, since the junction area A of each of the i-type InAlAs tunnel barrier layer 37 and the n-type InAlAs conductive layers 46 and 47 is sufficiently small to satisfy the relationship of A <We ² / 2εkT, Coulomb.
A blockade phenomenon occurs, and retention of stored information is performed based on the amount of change in electrostatic energy between one electron tunneling through the i-type InAlAs tunnel barrier layer 37 and no tunneling (up to e2 / 2C). Since this change amount is larger than the thermal disturbance, the retention time of the stored information is almost semi-permanent, and the refresh for retaining the stored information is unnecessary. Further, as for power consumption, since the memory holding mechanism uses electrostatic force due to Coulomb force, a small amount of current flows at the time of rewriting / reading, thereby reducing power consumption.

Also in the third embodiment, as in the first embodiment, an n-type I is formed between the N-type InAlAs barrier layer 34 and the n-type InAlAs conductive layer 47.
The nAlAs conductive layers 46 and the i-type InAlAs tunnel barrier layers 37 may be alternately formed in two or more cycles to form two or more tunnel junctions. Next, a memory device according to a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 12 is a sectional view showing a memory device according to the fourth embodiment. It should be noted that the same components as those of the storage device shown in FIG. In the memory device according to the fourth embodiment, the tunnel junction portion and the capacitor portion are formed of a metal and an insulator, respectively, as in the case of the second embodiment, and the same as in the case of the third embodiment. In addition, the junction area A at the tunnel junction is extremely small, and the Coulomb blockade phenomenon occurs.

That is, in FIG. 12, the second embodiment described above is used.
In the same manner as in the above case, a thickness of 3 is formed on the semi-insulating InP substrate 30.
A 00 nm i-type InGaAs layer 31 is formed.
N-type impurities were added to the surface of the InGaAs layer 31
n⁺Mold source regions 32 and n ⁺Type drain region 33
Is formed against⁺Mold source region 32 and
n⁺Pd / Ge / Au composite layer on the mold drain region 33
The source electrode S and the drain electrode D made of
It is formed by joining. The source electrode S and the drain
In addition to the Pd / Ge / Au composite layer, AuGe / A
It may be formed from a u composite layer, a Cr / Au composite layer, or the like.

On the i-type InGaAs layer 31, an N-type InAlAs barrier layer 34 having a thickness of 50 nm, which has a smaller electron affinity than the i-type InGaAs layer 31, is formed. A two-dimensional electron channel portion 35 connecting the source electrode S and the drain electrode D is formed in the i-type InGaAs layer 31 near the junction interface. Instead of the N-type InAlAs barrier layer 34, an N-type InP barrier layer having a thickness of 50 nm or a thickness of 1 is used.
A 0 nm CaF ₂ barrier layer may be used.

A thickness of 10 n is formed on the N-type InAlAs barrier layer 34 between the source electrode S and the drain electrode D.
m CoSi ₂ metal layer 48, this CoSi ₂ metal layer 48
2 nm thick CaF ₂ tunnel barrier layer 42 having a smaller electron affinity than CoSi ₂ metal layer 4 having a thickness of 10 nm
9, a CaF ₂ barrier layer 44 having a thickness of 10 nm, which has a smaller electron affinity than the CoSi ₂ metal layer 49, and a thickness 50.
A CoSi ₂ metal layer 45 having a thickness of 1 nm is formed in this order.

Here, the CoSi ₂ metal layers 48 and 49 are extremely finely formed, and the CoSi ₂ metal layer 4 is formed.
8,49 and the respective junction area A of the CaF ₂ tunnel barrier layer 42 is, A <We ² / 2εkT However, W: thickness of the CaF ₂ tunnel barrier layer 42 epsilon: dielectric constant of CaF ₂ tunnel barrier layer 42 It is characterized by being small enough to satisfy the relationship.

That is, the bonding area A is, for example, the operating temperature 30.
At 0K, it needs to be about 2 × 2 nm ² . However, in reality, since it is affected by the depletion layer extending from the periphery, a predetermined operation is possible even with a junction area larger than this. Thus, the CaF ₂ tunnel barrier layer 42 and the CoSi ₂ metal layers 48 and 49 that sandwich the CaF ₂ tunnel barrier layer 42 form an extremely fine tunnel junction portion.
An F ₂ barrier layer 44 and a CoSi ₂ metal layer 49 sandwiching the F ₂ barrier layer 44,
A capacitor section is constituted by 45.

Further, Pd is formed on the CoSi ₂ metal layer 45.
The control gate electrode CG composed of the / Ge / Au composite layer is formed in ohmic contact. The control gate electrode C
In addition to the Pd / Ge / Au composite layer, G may be formed from an AuGe / Au composite layer, a Cr / Au composite layer, or the like. Alternatively, it can also be used as the CoSi ₂ metal layer 45.

The operation of the memory device according to the fourth embodiment shown in FIG. 12 is similar to the operation described with reference to FIG. 8 for the second memory device of the present invention shown in FIG. Is omitted. Next, a method for manufacturing the memory device shown in FIG. 12 will be described. On the semi-insulating InP substrate 30, the i-type InGaAs layer 31, the N-type InAlAs barrier layer 34, the CoSi ₂ metal layer 48, the CaF ₂ tunnel barrier layer 42, and the CoSi ₂ are formed in the same manner as in the second embodiment. The metal layer 49, the CaF ₂ barrier layer 44, and the CoSi ₂ metal layer 45 are sequentially stacked.

Subsequently, the CoSi ₂ metal layer 45, CaF ₂
The barrier layer 44, the CoSi ₂ metal layer 49, the CaF ₂ tunnel barrier layer 42, and the CoSi ₂ metal layer 48 are patterned into an island shape by using a normal EB exposure method and dry etching, and have an extremely fine tunnel junction portion. A portion corresponding to the floating gate is formed. Then, as in the case of the third embodiment, a mixed solution of citric acid / hydrogen peroxide / water was used as an etchant to remove the CoSi ₂ metal layer 4 from the N-type InAlAs barrier layer 34.
Selective side etching of 8 and 49
₂ The cross-sectional area of the metal layers 48 and 49 is set to about 2 × 2 nm ² . As a result, the junction area A of each of the CoSi ₂ metal layers 48 and 49 and the CaF ₂ tunnel barrier layer 42 becomes about 2 × 2 nm ² , and a minute tunnel junction that satisfies the relationship of A <We ² / 2εkT is formed. It is formed. However, as described above, in consideration of the influence of the depletion layer extending from the periphery, the junction area may actually be larger than this.

Subsequently, an n-type impurity is selectively added to the N-type InAlAs barrier layer 34 and the i-type InGaAs layer 31 to form the n ⁺ -type source region 32 and the n ⁺ -type drain region 3.
Form 3 oppositely. Subsequently, the n ⁺ type source region 32, the n ⁺ type drain region 33, and CoSi are further added.
_{2 On the} metal layer 45, a source electrode S and a drain electrode D and a control gate electrode C made of a Pd / Ge / Au composite layer
Each G is formed by ohmic contact.

When an N-type InP barrier layer is used instead of the N-type InAlAs barrier layer 34, this N-type InP is used.
For selective side etching of the CoSi ₂ metal layers 48, 49 with respect to the barrier layer, phosphoric acid.
It suffices to use a mixture of hydrogen peroxide water and water.
When a CaF ₂ barrier layer is used instead of the nAlAs barrier layer 34, a H ₂ SO ₄ solution may be used as an etchant.

In the above manufacturing process, the source voltage is
A floating gate sandwiched between the pole S and the drain electrode D
The normal EB exposure method used to form the
The FIB method may be used instead of the etching. This
According to the present embodiment, as in the case of the second embodiment,
Almost similarly, CaF ₂Co sandwiching the tunnel barrier layer 42
Si₂Metal layers 48, 49, especially CoSi₂On the metal layer 48
Memory of "0" or "1" based on the amount of electric charge
The state can be defined and the source electrode S-drain voltage can be
Drain current I flowing between poles D_D"1" depending on the size of
Can read the "0" stored information, and
As in the case of the third embodiment, CaF₂Tunnel burr
A layer 42 and CoSi₂Each of the metal layers 48, 49
The joint area A is A <We²It is small enough to satisfy the relationship of / 2εkT and Coulomb block
In the case of the above-mentioned third embodiment, since the shade phenomenon occurs
The same effect as can be obtained.

Also in the fourth embodiment, as in the case of the second embodiment, the CoSi ₂ metal layer 48 and the CaF ₂ are provided between the N-type InAlAs barrier layer 34 and the CoSi ₂ metal layer 49. ₂ tunnel barrier layers 42 and 2 alternately
Two or more tunnel junctions may be formed by forming a period or more. Next, a storage device according to a fifth embodiment of the invention will be described with reference to FIG.

FIG. 13A is a sectional view showing a memory device according to the fifth embodiment of the present invention, and FIG. 13B is a plan view thereof. The memory device according to the fifth embodiment is characterized in that a large number of floating gate portions having tunnel junctions are arranged between the source electrode S and the drain electrode D.

That is, the i-type I is formed on the semi-insulating InP substrate 30.
nGaAs layer 31 is formed, the i-type n ⁺ -type source region InGaAs layer 31 surface and the n ⁺ -type drain region (not shown) is formed relative, further these n ⁺ -type source regions and n ⁺ -type drain Pd /
A source electrode S and a drain electrode D made of a Ge / Au composite layer are formed in ohmic contact. Further, the N-type InAlAs barrier layer 34 is formed on the i-type InGaAs layer 31, and the N-type InAlAs barrier layer 34 is formed.
The i-type InGaAs layer 31 near the junction interface with
A two-dimensional electron channel portion (not shown) that connects the source electrode S and the drain electrode D is formed.

On the N-type InAlAs barrier layer 34 between the source electrode S and the drain electrode D, n-type InA is formed.
lAs conductive layer, i-type InAlAs tunnel barrier layer, n
A type InAlAs conductive layer, an i-type InAlAs barrier layer, and an n-type InAlAs conductive layer are sequentially stacked, and a large number of island-shaped floating gate corresponding portions 50 having tunnel junctions are regularly arranged. The large number of island-shaped floating gate-corresponding portions 50 can be formed using the EB exposure method and selective etching.

Further, a control gate electrode CG made of a Pd / Ge / Au composite layer is formed on the large number of floating gate corresponding portions 50, and is in ohmic contact with each floating gate corresponding portion 50. Therefore, the control gate electrode CG can collectively control a large number of floating gate corresponding portions 50.

As described above, according to this embodiment, a large number of floating gate corresponding portions 50 having tunnel junctions are arranged in an array between the source electrode S and the drain electrode D, and a large number of floating gate corresponding portions are arranged. Since the portion 50 can be collectively controlled by the control gate electrode CG, the drain current I _D can be increased due to the multi-channel structure, and the memory retention characteristic can be favorably maintained by utilizing the Coulomb blockade phenomenon. It is possible to improve noise characteristics and reduce characteristic variations.

Next, a memory device according to a sixth embodiment of the invention will be described with reference to FIG. FIG. 14 is a plan view showing a storage device according to the sixth embodiment of the present invention. The storage device according to the sixth embodiment is characterized in that a large number of storage devices according to the first to fifth embodiments are arranged. still,
Here, a case where the storage device according to the first embodiment is arranged will be described.

That is, the storage device 5 according to the first embodiment.
1 is regularly arranged in an array on the XY plane of the substrate. A large number of source electrode wirings SL for wiring the source electrodes S of each storage device 51 in the X direction are arranged in parallel. In addition, a large number of drain electrode wirings DL that wire the drain electrodes D in the Y direction are arranged in parallel. Further, a large number of control gate electrode wirings CGL for arranging the control gate electrodes CG in the Y direction are arranged in parallel.

As described above, according to this embodiment, the storage device 5
1 is arranged in an array, and the source electrode S, the drain electrode D, and the control gate electrode CG are wired in the X and Y directions, respectively. It becomes possible to selectively read and write. That is, the storage device 51 to be selected is selected as X, Y.
In the source electrode wiring SL and the drain electrode wiring DL which are the intersections on the axis, if the source electrode wiring SL is grounded and the drain electrode wiring DL is positively biased, the specific memory device 51 is obtained depending on the amount of the current amount. Information can be selectively read. Further, by biasing the source electrode wiring SL and the control gate electrode wiring CGL to be positive or negative, it is possible to selectively rewrite the information in the specific memory device 51.

Further, it is possible to perform random rewriting by grounding all the control gate electrodes CG and wiring the source electrode S in the X-axis direction and the drain electrode D in the Y-axis direction. By the way, in order to wire the minute source electrode S, the drain electrode D and the control gate electrode CG in a state where a large number of memory devices 51 are densely arranged as shown in FIG. Control gate electrode CG sandwiched between the gate electrode and the drain electrode D
Connection between them is difficult. Therefore, a method of manufacturing a memory device in which the control gate electrode CG can be easily wired in such a dense region will be described with reference to FIGS.

FIG. 15A is a sectional view showing a step of forming a portion corresponding to the floating gate of the memory device of FIG.
(B) is a sectional view showing a wiring process of the control gate electrode CG. The same components as those of the storage device shown in FIGS. 9 and 14 are designated by the same reference numerals, and the description thereof will be omitted. On the semi-insulating InP substrate 30, the i-type InGaAs layer 31, the N-type I
nAlAs barrier layer 34, n-type InAlAs conductive layer 3
6, i-type InAlAs tunnel barrier layer 37, n-type In
AlAs conductive layer 38, i-type InAlAs barrier layer 39,
And the n-type InAlAs conductive layer 40 are sequentially stacked. Subsequently, a plurality of resists 52 patterned into a plurality of stripes parallel to the X-axis direction on the XY plane of the n-type InAlAs conductive layer 40 are formed. An insulating film made of SiO ₂ , Si ₃ N ₄ , SiON, or the like may be used instead of the resist 52.

Then, using this resist 52 as a mask
The n-type InAlAs conductive layer 40 and the i-type InAlAs layer.
Rear layer 39, n-type InAlAs conductive layer 47, i-type InA
lAs tunnel barrier layer 37 and n-type InAlAs conductor
The electric layer 46 is, for example, CH_FourAnd H ₂RIE (reaction
(Sequential ion etching)
Pattern in stripes (see Fig. 15 (a))
See).

Subsequently, the recess formed by RIE is filled with, for example, a polyimide layer 53, and the resist 52 is removed to expose the surface of the n-type InAlAs conductive layer 40, that is, so-called cueing is performed. Note that other resin materials may be used instead of the polyimide layer 53, and S
An insulating layer material such as iO ₂ may be used. After forming a metal wiring layer made of WSi or TiPtAu on the flattened entire surface in this way, the metal wiring layer is patterned into a plurality of stripes parallel to the Y-axis direction on the XY plane to form a control gate electrode. A control gate electrode wiring CGL which also serves as a CG is formed (see FIG. 15B).

Next, although not shown, the n-type InAlAs conductive layer 40, the i-type InAlAs barrier layer 39, and the n-type InAl are masked using the control gate electrode wiring CGL as a mask.
As conductive layer 47, i-type InAlAs tunnel barrier layer 3
7 and the n-type InAlAs conductive layer 46 are mesa-etched to form floating gate corresponding portions in an array. Then, the source electrode S and the drain electrode D are formed.

In this way, a large number of storage devices 51 as shown in FIG. 14 form a storage device arranged in an array, and fine control gate electrodes CG in the dense area are formed.
Wiring in the Y direction can be easily performed. Incidentally, FIG.
When the storage devices 51 arranged in an array in 4 are not the storage device according to the first embodiment but the storage device according to the third or fourth embodiment, when forming the floating gate corresponding portion, , N-type InAlAs conductive layers 46, 47
Alternatively, it is necessary to add a step of selectively side etching the CoSi ₂ metal layers 48 and 49.

Further, in the sixth embodiment, a transistor has to be formed in addition to the memory cell array in which the memory devices 51 are arranged in an array. However, in the structure of the present invention, the control gate electrode CG is directly used as the Schottky. By replacing it with a gate, it becomes possible to fabricate a FET or HEMT, and it can also be used as a switching device around the memory.

Further, in the above-mentioned first to sixth embodiments,
50-nm-thick N-type InAlA as first barrier layer
The s barrier layer 34 is partially or entirely thinned so that hot electrons from the two-dimensional electron channel portion 35 in the i-type InGaAs layer 31 serve as n-type InA as a first conductive layer.
1As conductive layers 36, 46 or CoSi ₂ metal layers 41, 4
You may form the tunnel barrier part for moving to 8.

Further, in the above first to sixth embodiments,
An i-type InGaAs layer 31 is used as a semiconductor layer that forms a channel portion connecting the source electrode S and the drain electrode D, and an N-type InAlAs barrier layer 34, an N-type InP barrier layer, or a first barrier layer on the i-type InGaAs layer 31, or A CaF ₂ barrier layer is used, but instead of these, a GaAs layer is used as the semiconductor layer forming the channel portion, and the first
AlGaAs layer may be used as the barrier layer, or an InAs layer is used as the semiconductor layer, and a GaSb system or the like that is heterojunction (including p, n junction) with the InAs layer is formed as the first barrier layer thereon. Any semiconductor layer may be used. Further, instead of these compound semiconductors, a Si layer is used as a semiconductor layer forming a channel portion, and a SiO ₂ layer, a SiGe layer, or an S layer is used as a first barrier layer on the Si layer.
It is also possible to use the iC layer. Further, at this time, n
The type semiconductor layer may be replaced with a p-type semiconductor layer.

In the second or fourth embodiment,
The tunnel junction composed of the CaF ₂ tunnel barrier layer and the CoSi ₂ metal layer sandwiching the CaF ₂ tunnel barrier layer has an Nb / AlO _x / Nb junction structure using a superconducting layer, or Si.
A heterojunction structure such as TiO ₃ / MgO can be used.

[0105]

As described above, according to the present invention,
A substrate, a semiconductor layer formed on the substrate, a source electrode and a drain electrode formed on the semiconductor layer so as to be in ohmic contact with the semiconductor layer, respectively, and between the source electrode and the drain electrode. A first conductive layer formed on the semiconductor layer sandwiched between the first conductive layer and a first barrier layer having an electron affinity lower than that of the semiconductor layer;
A second conductive layer formed on the second conductive layer via a tunnel barrier layer having an electron affinity lower than that of the first conductive layer, and a second conductive layer formed on the second conductive layer. Also has a third conductive layer formed via a second barrier layer having a small electron affinity and a gate electrode formed on this third conductive layer, so that the voltage applied to this gate electrode can be increased. Control and transfer charge between the first conductive layer and the second conductive layer through the tunnel barrier layer, and a change in the amount of charge in the first conductive layer causes a change in the charge of the semiconductor layer. Since the electron concentration formed near the junction interface with the first barrier layer can be increased or decreased to control the current flowing between the source electrode and the drain electrode,
It is possible to realize a high-speed storage device as compared with a conventional storage device using a MOSFET using Si.

Further, since the respective junction areas A of the first and second conductive layers and the tunnel barrier layer are so small that A <We ² / 2εkT, the Coulomb blockade phenomenon occurs, Since stored information is held based on the amount of change in electrostatic energy when one electron tunnels through the tunnel barrier layer 17 and when it does not tunnel, further high speed, low power consumption, and high density storage are achieved. The device can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining a Coulomb blockade phenomenon and a graph showing a current-voltage characteristic thereof.

FIG. 2 is a circuit diagram for explaining the Coulomb-Staircase phenomenon and a graph showing current-voltage characteristics thereof.

3A and 3B are a cross-sectional view and a circuit diagram showing a first memory device according to the present invention for explaining the principle of the present invention.

FIG. 4 is an energy band diagram for explaining the operation of the first storage device in FIG.

5 is an energy band diagram for explaining the operation of the first storage device of FIG.

6 is a graph showing current-voltage characteristics of the first memory device of FIG.

7A and 7B are a cross-sectional view and a circuit diagram showing a second memory device according to the present invention for explaining the principle of the present invention.

8 is a graph showing current-voltage characteristics of the second memory device of FIG.

FIG. 9 is a sectional view showing a memory device according to a first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a memory device according to a second embodiment of the present invention.

FIG. 11 is a sectional view showing a memory device according to a third embodiment of the present invention.

FIG. 12 is a sectional view showing a memory device according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view and a plan view showing a memory device according to a fifth embodiment of the present invention.

FIG. 14 is a plan view showing a storage device according to a sixth embodiment of the present invention.

FIG. 15 is a process drawing for explaining the manufacturing method of the memory device in FIG.

[Explanation of symbols]

1, 2 and 3 ... Micro tunnel junction 10 ... Substrate 11 ... Semiconductor layer 12 ... Source region 13 ... Drain region 14 ... First barrier layer 15 ... Channel part 16 ... First conductive layer 17 ... Tunnel barrier layer 18 ... 2nd conductive layer 19 ... 2nd barrier layer 20 ... 3rd conductive layer 21 ... Tunnel junction part 22 ... Capacitor part 23 ... 1st conductive layer 24 ... 2nd conductive layer 25 ... Tunnel junction part 26 ... Capacitor Part 30 ... Semi-insulating InP substrate 31 ... i-type InGaAs layer 32 ... n ⁺ type source region 33 ... n ⁺ type drain region 34 ... N-type InAlAs barrier layer 35 ... two-dimensional electron channel part 36 ... n-type InAlAs conductive layer 37 ... i-type InAlAs tunnel barrier layer 38 ... n-type InAlAs conductive layer 39 ... i-type InAlAs barrier layer 40 ... n-type InAlAs conductive layer 41 ... CoSi ₂ metal layer 42 ... CaF ₂ tunnel barrier layer 43 ... CoSi ₂ metal layer 44 ... CaF ₂ barrier layer 45 ... CoSi ₂ metal layer 46 ... n type InAlAs conductive layer 47 ... n type InAlAs conductive layer 48 ... CoSi ₂ metal layer 49. CoSi ₂ metal layer 50 ... Floating gate equivalent part 51 ... Memory device 52 ... Resist 53 ... Polyimide layer S ... Source electrode D ... Drain electrode CG ... Control gate electrode SL ... Source electrode wiring DL ... Drain electrode wiring CGL ... Control gate electrode wiring

Claims (19)

[Claims] 1. A substrate, a semiconductor layer formed on the substrate, a source electrode and a drain electrode formed on the semiconductor layer so as to face each other and making ohmic contact with the semiconductor layer respectively, the source electrode and the A first conductive layer formed on the semiconductor layer sandwiched between the drain electrode and the semiconductor layer via a first barrier layer having an electron affinity lower than that of the semiconductor layer; and on the first conductive layer. A second barrier layer formed via a tunnel barrier layer having an electron affinity lower than that of the first conductive layer.
A conductive layer, a third conductive layer formed on the second conductive layer via a second barrier layer having an electron affinity lower than that of the second conductive layer, and the third conductive layer. A gate electrode formed in ohmic contact therewith, and controlling a voltage applied to the gate electrode to connect the first conductive layer and the second conductive layer via the tunnel barrier layer. Between the source and the source by increasing or decreasing the carrier concentration of a channel formed in the vicinity of a junction interface between the semiconductor layer and the first barrier layer by changing the amount of charge in the first conductive layer by moving charges between the source and the source. A memory device characterized by controlling a current flowing between an electrode and the drain electrode. 2. The memory device according to claim 1, wherein a junction area A of each of the first and second conductive layers and the tunnel barrier layer is A <We ² / 2εkT, where W is a barrier layer. Thickness: e: elementary charge ε: barrier layer dielectric constant k: Boltzmann constant T: temperature. 3. The memory device according to claim 1, wherein the first barrier layer is a semiconductor barrier layer, and the first conductive layer is a semiconductor conductive layer having a thin layer thickness. The tunnel barrier layer is a semiconductor tunnel barrier layer, the second conductive layer is a semiconductor conductive layer, the second barrier layer is a semiconductor barrier layer, and the third conductive layer is a semiconductor conductive layer. A storage device characterized by being. 4. The memory device according to claim 3, wherein the substrate is a semi-insulating semiconductor substrate, the semiconductor layer is a non-doped semiconductor layer, and the first barrier layer is an n-type impurity. Is a doped semiconductor barrier layer, the first conductive layer is a non-doped or n-type impurity doped semiconductor conductive layer, the tunnel barrier layer is a non-doped or n-type impurity doped A semiconductor tunnel barrier layer, the second conductive layer is a semiconductor conductive layer doped with an n-type impurity, the second barrier layer is a non-doped semiconductor barrier layer, the third conductive layer Is a semiconductor conductive layer doped with an n-type impurity, and a two-dimensional electron gas is formed in the vicinity of a junction interface of the semiconductor layer with the first barrier layer. . 5. The memory device according to claim 4, wherein the substrate is a semi-insulating InP substrate, the semiconductor layer is an i-type InGaAs layer, and the first barrier layer is N-type InAlAs. Layer or N type I
an nP layer, the first conductive layer is an n-type InGaAs layer, the tunnel barrier layer is an i-type InAlAs layer, the second conductive layer is an n-type InGaAs layer, The second barrier layer is an i-type InGaAs layer, the third conductive layer is an n-type InGaAs layer, and the source electrode, the drain electrode, and the gate electrode are AuGe / Au ohmic electrodes, Pd / Ge / A
A memory device, which is a u ohmic electrode or a Cr / Au ohmic electrode. 6. The memory device according to claim 1, wherein the first barrier layer is a semiconductor barrier layer or an insulator barrier layer, and the first conductive layer is a metal layer having a thin layer thickness. The tunnel barrier layer is an insulator tunnel barrier layer, the second barrier layer is an insulator barrier layer, and the third conductive layer is a metal layer. apparatus. 7. The memory device according to claim 6, wherein the semiconductor layer is a non-doped semiconductor layer, and the first barrier layer is a semiconductor barrier layer or an insulator barrier layer doped with an n-type impurity. The two-dimensional electron gas is formed in the vicinity of the junction interface between the semiconductor layer and the first barrier layer. 8. The memory device according to claim 7, wherein the semiconductor layer is an i-type InGaAs layer, and the first barrier layer is an N-type InAlAs layer and an N-type In.
P, or CaF ₂ layer, the first conductive layer is a CoSi ₂ layer, the tunnel barrier layer is a CaF ₂ layer, the second conductive layer is a CoSi ₂ layer, The second barrier layer is a CaF ₂ layer, the third conductive layer is a CoSi ₂ layer, the source electrode, the drain electrode, and the gate electrode are AuGe / Au ohmic electrodes, Pd / Ge / A
A memory device, which is a u ohmic electrode or a Cr / Au ohmic electrode. 9. The memory device according to claim 7, wherein the semiconductor layer is a Si layer, the first barrier layer is a SiO ₂ layer, and the first conductive layer is a CoSi ₂ layer. The tunnel barrier layer is a CaF ₂ layer, the second conductive layer is a CoSi ₂ layer, the second barrier layer is a CaF ₂ layer, and the third conductive layer is , CoSi ₂ layer. 10. The memory device according to claim 1, wherein the first conductive layer and the tunnel barrier layer between the first barrier layer and the first conductive layer are alternately formed into two layers. A storage device characterized by being formed for a period or more. 11. The memory device according to claim 1, wherein a tunnel barrier portion is formed in a part or all of the first barrier layer, and the semiconductor layer is formed from the semiconductor layer through the tunnel barrier portion. First
A storage device, characterized in that electrons are transferred to the conductive layer of. 12. The memory device according to claim 1, wherein the first barrier layer sequentially stacked on the semiconductor layer,
A floating gate equivalent portion composed of the first conductive layer, the tunnel barrier layer, the second conductive layer, the second barrier layer, and the third conductive layer serves as the source electrode and the drain electrode. A storage device, wherein a large number of control gate electrodes are regularly arranged between the control gate electrodes and are ohmic-bonded over the entire third conductive layer of the floating gate corresponding portions. 13. The memory device according to claim 1, wherein a large number of memory devices are regularly arranged in an array on the X and Y planes, and the plurality of source electrodes of the memory devices are arranged. A storage device, characterized in that it is arranged in a stripe shape in the X direction, and the drain and the control gate electrode are arranged in a stripe shape in the Y direction. 14. A semiconductor layer, a first barrier layer having an electron affinity lower than that of the semiconductor layer, a first conductive layer, a tunnel barrier layer having an electron affinity lower than that of the first conductive layer, and A second conductive layer, a second barrier layer having an electron affinity smaller than that of the second conductive layer, and a third conductive layer in this order; Three
Second conductive layer, the second barrier layer, the second conductive layer, the tunnel barrier layer, and the first conductive layer are patterned into an island shape to form a floating gate corresponding portion. A method of manufacturing a storage device, comprising: 15. The method for manufacturing a memory device according to claim 14, wherein after the second step, the first conductive layer and the second conductive layer are selectively side-etched to form the first conductive layer. And the junction area A of each of the second conductive layer and the tunnel barrier layer is A <We ² / 2εkT, where: W: thickness of barrier layer e: elementary charge ε: dielectric constant of barrier layer k: Boltzmann A method of manufacturing a memory device, comprising a third step of setting a constant T: temperature. 16. The method of manufacturing a memory device according to claim 15, wherein the second barrier layer is an N-type InAlAs layer, and each of the first conductive layer and the second conductive layer is n.
Type InAlAs layer or CoSi ₂ layer, and the first conductive layer and the second layer in the third step.
The method for manufacturing a memory device, wherein the etching liquid used for the selective side etching of the conductive layer is a mixed liquid of citric acid / hydrogen peroxide water / water. 17. The method of manufacturing a memory device according to claim 15, wherein the second barrier layer is an N-type InP layer, and each of the first conductive layer and the second conductive layer is n.
Type InAlAs layer or CoSi ₂ layer, and the first conductive layer and the second layer in the third step.
The method for manufacturing a memory device, wherein the etching solution used for selective side etching of the conductive layer is a mixed solution of phosphoric acid, hydrogen peroxide solution, and water. 18. The method of manufacturing a memory device according to claim 15, wherein the second barrier layer is a CaF ₂ layer, and the first conductive layer and the second conductive layer are each C.
an oSi ₂ layer, the first conductive layer and the second conductive layer in the third step.
The method for manufacturing a memory device, wherein the etching solution used for the selective side etching of the conductive layer is H ₂ SO ₄ solution. 19. The method of manufacturing a memory device according to claim 14, wherein the second step is performed by reactive ion etching, the third conductive layer, the second barrier layer, and the second barrier layer. Patterning the conductive layer, the tunnel barrier layer, and the first conductive layer in an island shape to form a large number of floating gate corresponding portions regularly in an array, the second step or the After the third step, a recess other than the floating gate corresponding portion is filled with an insulating material to flatten the surface, and subsequently, a metal wiring for connecting the third conductive layer of the floating gate corresponding portion in a certain direction. Fourth layer forming layers in parallel stripes
A method of manufacturing a storage device, comprising: