JPH07200414A - Method and substrate for prevention against decoding of storage contents - Google Patents

Method and substrate for prevention against decoding of storage contents

Info

Publication number
JPH07200414A
JPH07200414A JP5349622A JP34962293A JPH07200414A JP H07200414 A JPH07200414 A JP H07200414A JP 5349622 A JP5349622 A JP 5349622A JP 34962293 A JP34962293 A JP 34962293A JP H07200414 A JPH07200414 A JP H07200414A
Authority
JP
Japan
Prior art keywords
substrate
integrated circuit
contents
semiconductor device
circuit chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5349622A
Other languages
Japanese (ja)
Inventor
Yasushi Uchida
靖 内田
Katsuya Tanuma
克哉 田沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP5349622A priority Critical patent/JPH07200414A/en
Publication of JPH07200414A publication Critical patent/JPH07200414A/en
Withdrawn legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

PURPOSE:To prevent the storage contents of a memory and the contents of its relative integrated circuit from illegally be copied by decoding the contents of the memory by a 3rd person. CONSTITUTION:Electric conductors 16 for the power supply of an integrated circuit chip 20 are bent and formed in the entire mount area on the substrate 10. The integrated circuit chip 20 is mounted barely in the mount area while having its top side opposite the substrate top surface, and protected by molding its top with resin, etc. The integrated circuit chip 20 which is thus mounted can not have its top side seen directly and the moment the integrated circuit chip 20 tries to be peeled off the substrate 10, the power supply is cut off, so that the contents stored in the memory in the integrated circuit chip 20 are lost. Further, even if the memory contents tried to be analyzed by holing the substrate 10 without damaging the integrated circuit chip 20 from the reverse side of the substrate 10, the conductors 16 for the power supply are disconnected, so the storage contents are lost even in this case to prevent the memory contents from being decoded.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電源を供給することに
よって記憶内容を保持できるメモリや、このようなメモ
リが内蔵されている集積回路のための記憶内容の解読防
止方法及び記憶内容の解読防止用基板に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory capable of retaining stored contents by supplying power, a method for preventing decipherment of stored contents for an integrated circuit incorporating such a memory, and a decipherment of stored contents. The present invention relates to a prevention substrate.

【0002】[0002]

【従来の技術】ゲーム機器業界などにおいては、従来か
ら、人気の高いゲームに使用されている半導体集積回路
をリバースエンジニアリングによって解析し、同様の機
能を有するものをコピーし、これを低価格で販売して不
当な利益を上げるという行為が横行している。このよう
な行為を防止するために、集積回路チップにSRAMの
ような電源が供給されている間だけ記憶内容を保持でき
るメモリを付加し、これに出荷時点で何らかの暗号を記
憶させ、その内容を読み込まないと集積回路が動作しな
いというようにして、不正なコピーを防止するという措
置が採られている。このSRAMは、例えば基板上に設
けられた専用の電池からの電源によって記憶内容を保持
しており、メモリを基板から外すと電源が遮断されて記
憶内容は消滅する。しかしながら、このような方策を講
じても、基板上に実装された集積回路のプラスチックパ
ッケージを溶剤で溶かし、集積回路に電源が供給された
状態を維持しながらメモリの記憶内容を解析するという
方法で、最終的に半導体集積回路の内容がコピーされる
ことがある。
2. Description of the Related Art In the game machine industry and the like, semiconductor integrated circuits conventionally used for popular games are analyzed by reverse engineering, and those with similar functions are copied and sold at a low price. The act of making unreasonable profits is widespread. In order to prevent such an action, an integrated circuit chip is provided with a memory such as SRAM that can hold the stored contents only while power is being supplied, and some ciphers are stored at the time of shipment to store the contents. Measures have been taken to prevent unauthorized copying by preventing the integrated circuit from operating unless it is read. This SRAM holds the stored contents by, for example, a power supply from a dedicated battery provided on the substrate, and when the memory is removed from the substrate, the power is cut off and the stored contents disappear. However, even if such a measure is taken, it is possible to dissolve the plastic package of the integrated circuit mounted on the substrate with a solvent and analyze the stored contents of the memory while maintaining the power supply to the integrated circuit. Finally, the contents of the semiconductor integrated circuit may be copied.

【0003】[0003]

【発明が解決しようとする課題】かかる事態を防止する
ために、パッケージングされていない集積回路チップを
チップの表側が基板に対向するようにして直接基板に実
装し、その上から保護のための樹脂で覆う、いわゆるベ
アチップ実装という方法が採られることがある。この方
法だと、基板に実装する際の集積度が向上するだけでな
く、基板に実装されたチップの表側を見ることができな
いため、このままの状態ではメモリ内容の解析はできな
い。そして、チップを基板から外そうとすると、チップ
が基板から放れた時点で必然的にチップに供給される電
源が遮断されて記憶内容は消滅するので、メモリがSR
AMなどの場合は、その内容の解読を防止できる。
In order to prevent such a situation, an unpackaged integrated circuit chip is directly mounted on a substrate so that the front side of the chip faces the substrate, and protection is performed from above. A so-called bare chip mounting method of covering with resin may be adopted. This method not only improves the degree of integration when mounted on the substrate, but also cannot see the front side of the chip mounted on the substrate, so the memory contents cannot be analyzed in this state. When the chip is removed from the substrate, the power supplied to the chip is inevitably cut off when the chip is released from the substrate and the stored contents are erased.
In the case of AM or the like, it is possible to prevent the content from being decrypted.

【0004】しかしながら、ベアチップ実装という方法
を採った場合であっても、チップを損傷させないように
して基板の裏側からドリル等で基板に穴を開け、チップ
に電源が供給された状態を維持したままメモリの表側を
見ることによって内容を読み取ることができる。このよ
うな方法で記憶内容の解析がなされると、やはり完全に
はメモリの記憶内容及びこれに関連する集積回路のコピ
ーを防止することはできない。
However, even when the method of bare chip mounting is adopted, a hole is made in the substrate from the back side of the substrate with a drill or the like so as not to damage the chip, and the state in which power is supplied to the chip is maintained. The contents can be read by looking at the front side of the memory. When the stored contents are analyzed in this way, it is still not possible to completely prevent copying of the stored contents of the memory and the associated integrated circuit.

【0005】本発明は上記事情に基づいてなされたもの
であり、第三者がメモリの内容を不正に解読することが
できない記憶内容の解読防止方法及び記憶内容の解読防
止用基板を提供することを目的とするものである。
The present invention has been made in view of the above circumstances, and provides a method for preventing decipherment of stored contents and a substrate for preventing decipherment of stored contents in which a third party cannot illegally decipher the contents of the memory. The purpose is.

【0006】[0006]

【課題を解決するための手段】上記の課題を解決するた
めに、請求項1記載の記憶内容の解読防止方法は、電源
の供給により記憶内容が保持される記憶手段を有する半
導体装置を実装する基板上の実装領域に、前記半導体装
置に電源を供給する導線を、前記実装領域全体にわたっ
て曲折させて配線するとともに、前記半導体装置の表側
を前記基板の表面に対向させて実装することを特徴とす
るものである。
In order to solve the above-mentioned problems, the method for preventing decipherment of stored contents according to a first aspect of the present invention mounts a semiconductor device having storage means for holding stored contents when power is supplied. In the mounting area on the substrate, a conductive wire for supplying power to the semiconductor device is bent and wired over the entire mounting area, and the front side of the semiconductor device is mounted so as to face the surface of the substrate. To do.

【0007】上記の課題を解決するために、請求項2記
載の記憶内容の解読防止用基板は、半導体装置の表側を
基板表面に対向させて実装するときに前記半導体装置の
パッドと接続される接点を備え、かつ、前記半導体装置
に電源を供給するための導線を前記半導体装置の実装領
域全体にわたって曲折して配線したことを特徴とするも
のである。
In order to solve the above problems, the memory content decoding prevention substrate according to claim 2 is connected to a pad of the semiconductor device when the semiconductor device is mounted with the front side facing the substrate surface. The present invention is characterized in that a conducting wire having a contact point and for supplying power to the semiconductor device is bent and wired over the entire mounting region of the semiconductor device.

【0008】[0008]

【作用】請求項1記載の発明は前記の構成により、半導
体装置の表側が基板に対向して実装されるので、基板の
上から見るだけでは記憶手段の内容を解析することはで
きない。また、基板上で半導体装置を実装する実装領域
全体にわたって電源用の導線を曲折させて配線すること
により、基板の裏側からドリルなどで穴を開けた場合に
電源用の導線も必然的に切断される。したがって、半導
体装置に内蔵された記憶手段がSRAMなどの場合に
は、その瞬間に記憶内容が消滅する。これにより、記憶
内容及びこれに関連する半導体装置の不正な解読を有効
に防止できる。
According to the first aspect of the present invention, since the front side of the semiconductor device is mounted so as to face the substrate with the above configuration, the contents of the storage means cannot be analyzed only by looking at it from above the substrate. Also, by bending and wiring the power supply wire over the entire mounting area for mounting the semiconductor device on the board, the power supply wire is inevitably cut when a hole is drilled from the back side of the board. It Therefore, when the storage means built in the semiconductor device is an SRAM or the like, the stored contents disappear at that moment. As a result, it is possible to effectively prevent illegal decryption of the stored contents and the semiconductor device related thereto.

【0009】請求項2記載の発明は前記の構成により、
電源用の導線を曲折させて配線した実装領域にSRAM
などの記憶手段をその表側(回路形成面又は外部接続用
領域形成面)が基板面に対向するようにして実装すれ
ば、基板の裏から穴を開けて記憶手段の内容を解読しよ
うとしても、基板に穴を開けると同時に電源用の導線が
切断され、記憶手段の記憶内容が消失するので、記憶内
容及びそれに関連する半導体装置の不正な解読を有効に
防止することができる。
According to a second aspect of the present invention, by the above configuration,
SRAM in the mounting area where the power supply wire is bent and wired
If the storage means such as is mounted so that its front side (circuit formation surface or external connection area formation surface) faces the board surface, even if a hole is punched from the back of the board and the contents of the storage means are decoded, At the same time when the hole is made in the substrate, the power supply wire is cut and the stored content of the storage means is lost, so that the stored content and the semiconductor device related thereto can be effectively prevented from being illegally decoded.

【0010】[0010]

【実施例】以下に図面を参照して本発明の一実施例につ
いて説明する。図1は集積回路チップ用の配線が形成さ
れた基板の一例の平面図、図2は基板に集積回路チップ
を実装する様子を示した斜視図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an example of a substrate on which wiring for an integrated circuit chip is formed, and FIG. 2 is a perspective view showing how the integrated circuit chip is mounted on the substrate.

【0011】図1の基板10上に破線で示した実装領域
12には、図2に示した半導体装置である集積回路チッ
プ20が、この基板に表側を対向するようにしてベアチ
ップ実装される。実装領域12の内側の周縁部には、集
積回路チップ20のパッドとバンプを介して接続される
(いわゆるバンプ実装)接点が多数形成されている。ま
た、それぞれの接点には、集積回路チップを外部の回路
と接続するために形成された配線が図示したように接続
されている。なお、集積回路チップ20は、記憶手段と
してSRAMを内蔵しているものとして説明する。
In the mounting region 12 shown by the broken line on the substrate 10 of FIG. 1, the integrated circuit chip 20 which is the semiconductor device shown in FIG. 2 is bare-chip mounted on the substrate with its front side facing. A large number of contacts (so-called bump mounting) connected to the pads of the integrated circuit chip 20 via bumps are formed on the inner peripheral edge of the mounting region 12. Further, wirings formed for connecting the integrated circuit chip to an external circuit are connected to the respective contacts as shown. It should be noted that the integrated circuit chip 20 will be described as having a built-in SRAM as a storage means.

【0012】ところで、上記多数の接点のうちの一つの
接点14は、集積回路チップの電源パッド22に接続さ
れる接点であり、接点14に接続された導線16は電源
用の配線である。導線16は、基板10上に設けられた
集積回路チップ20専用の電池(図示せず)に接続され
ている。又、この導線16は、他の導線とは異なり、実
装領域12の内側において左右を往復するように曲折
し、実装領域のほぼ全体を覆うようにして通過したあ
と、実装領域12の外側へ接続されるよう形成されてい
る。
By the way, one of the plurality of contacts 14 is a contact connected to the power supply pad 22 of the integrated circuit chip, and the conductive wire 16 connected to the contact 14 is a wiring for power supply. The conductive wire 16 is connected to a battery (not shown) dedicated to the integrated circuit chip 20 provided on the substrate 10. Also, unlike the other conductive wires, the conductive wire 16 is bent so as to reciprocate left and right inside the mounting area 12, passes through so as to cover almost the entire mounting area, and then is connected to the outside of the mounting area 12. Is formed.

【0013】集積回路20は、図2に示すように、その
表側が基板表面に対向するように、すなわち下を向くよ
うに実装される。こうして実装されたあとは、その上を
保護のために樹脂などでモールドする。このようにする
と集積回路チップ20の回路パターンが形成された表側
を見ることはできないので、そのままではSRAMの記
憶内容を解析することはできない。また、チップ20の
電源パッド22は基板に対向する側にあるので、この電
源パッドに外部から電源を接続することはできない。更
に、モールドされた樹脂を溶剤などで溶かしてチップ2
0を基板10から剥がそうとすると、チップ20が基板
から剥がされた瞬間に電源パッド22が接点14から離
れるので、その時点で電源が遮断されSRAMの記憶内
容は消失する。したがって、チップ20を基板10から
取り外してSRAMの内容を解析することはできない。
As shown in FIG. 2, the integrated circuit 20 is mounted so that its front side faces the surface of the substrate, that is, it faces downward. After being mounted in this way, a resin or the like is molded on top of it for protection. In this way, the front side of the integrated circuit chip 20 on which the circuit pattern is formed cannot be seen, and therefore the stored contents of the SRAM cannot be analyzed as it is. Further, since the power supply pad 22 of the chip 20 is on the side facing the substrate, it is not possible to connect an external power supply to this power supply pad. In addition, melt the molded resin with a solvent etc.
When 0 is peeled from the substrate 10, the power supply pad 22 separates from the contact 14 at the moment when the chip 20 is peeled from the substrate, so that the power is cut off at that point and the stored contents of the SRAM are lost. Therefore, the chip 20 cannot be removed from the substrate 10 to analyze the contents of the SRAM.

【0014】ところで従来は、このようにチップ20を
その表側を基板10に対向させて実装してあっても、チ
ップに損傷を与えないようにして基板の裏側からドリル
などで基板に穴を開けたり、何らかの方法で基板だけを
破壊することにより、チップに電源が供給された状態を
維持したままSRAMの記憶内容を解析するという方法
で、違法なコピーが行われることがあった。そこで本実
施例では、図1及び図2に示すように、電源配線となる
導線16を実装領域12を覆うよう形成したことによ
り、実装後にチップ20の表側を見るために基板10の
裏側からドリルなどで穴を開けた場合、導線16は必然
的に切断され、したがってSRAMの記憶内容は消滅す
る。したがって、SRAMの記憶内容を解析してチップ
20を不正にコピーするという行為を有効に防止するこ
とができる。
By the way, conventionally, even when the chip 20 is mounted with the front side facing the substrate 10 in this way, a hole is drilled in the substrate from the back side of the substrate with a drill or the like so as not to damage the chip. Alternatively, illegal copying may be performed by a method of analyzing the stored contents of the SRAM while maintaining the state in which power is supplied to the chip by destroying only the substrate by some method. Therefore, in this embodiment, as shown in FIGS. 1 and 2, by forming the conductive wire 16 serving as the power supply wiring so as to cover the mounting region 12, the drilling is performed from the back side of the substrate 10 to see the front side of the chip 20 after mounting. When a hole is made with, for example, the conductive wire 16 is inevitably cut off, so that the contents stored in the SRAM disappear. Therefore, it is possible to effectively prevent the act of illegally copying the chip 20 by analyzing the stored contents of the SRAM.

【0015】尚、本発明は上記実施例に限定されるもの
ではなく、その要旨の範囲内で種々の変形が可能であ
る。例えば、実装領域12の内側における電源用の導線
16の配線の仕方は、図1又は図2に示したようなもの
には限定されず、実装領域全体にわたって曲折させてあ
ればどのようなものでも同様の効果を奏することができ
る。たとえば、電源用の導線16は渦巻状に形成しても
よい。また、上記実施例ではメモリがSRAMである場
合について説明したが、本発明は、電源の供給によって
記憶内容が保持されるメモリであればどのようなものに
ついても適用することができる。
The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the invention. For example, the wiring method of the power supply conductor 16 inside the mounting area 12 is not limited to that shown in FIG. 1 or 2, and any method may be used as long as it is bent over the entire mounting area. The same effect can be achieved. For example, the power supply wire 16 may be formed in a spiral shape. Further, although the case where the memory is the SRAM has been described in the above embodiment, the present invention can be applied to any memory as long as the memory contents are held by the supply of power.

【0016】尚、本実施例では、電源パッド22と他の
パッド全てが集積回路チップ20の同一面に形成された
場合についてのみ述べたが、少なくとも電源パッド22
の形成された面が基板10に対向して実装されれば、他
のパッドについては他の面に形成されていてもよい。
In this embodiment, only the case where the power supply pad 22 and all the other pads are formed on the same surface of the integrated circuit chip 20 has been described, but at least the power supply pad 22.
The other pads may be formed on other surfaces as long as the surface on which is formed is mounted so as to face the substrate 10.

【0017】[0017]

【発明の効果】以上説明したように本発明によれば、基
板上の半導体装置の実装領域全体にわたって電源用の導
線を曲折させて形成することにより、半導体装置の表側
を基板表面に対向させてベアチップ実装すると、基板の
裏から基板を破壊したときに、電源用の導線も同時に切
断されて半導体装置への電源の供給が遮断され、半導体
装置内の記憶手段の記憶内容が消滅する。したがって、
半導体装置を解析してその記憶内容又は回路接続等を不
法にコピーする行為を有効に防止することができる記憶
内容の解読防止方法及び記憶内容の解読防止用基板を提
供することができる。
As described above, according to the present invention, the conductive wire for the power supply is formed by bending over the entire mounting area of the semiconductor device on the substrate, so that the front side of the semiconductor device is opposed to the substrate surface. When the chip is mounted on the bare chip, when the substrate is broken from the back side of the substrate, the conductive wire for the power supply is also cut off, the power supply to the semiconductor device is cut off, and the stored contents of the storage means in the semiconductor device disappear. Therefore,
It is possible to provide a method for preventing decipherment of stored content and a substrate for deciphering stored content that can effectively prevent the act of illegally copying the stored content or circuit connection of a semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である基板の一部を示した概
略平面図である。
FIG. 1 is a schematic plan view showing a part of a substrate which is an embodiment of the present invention.

【図2】本発明の一実施例である基板に集積回路チップ
を実装する仕方を示した概略斜視図である。
FIG. 2 is a schematic perspective view showing a method of mounting an integrated circuit chip on a substrate which is an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10 基板 12 実装領域 14 接点 16 電源用導線 20 集積回路チップ 22 電源パッド 10 substrate 12 mounting area 14 contacts 16 power supply wire 20 integrated circuit chip 22 power supply pad

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 電源の供給により記憶内容が保持される
記憶手段を有する半導体装置を実装する基板上の実装領
域に、前記半導体装置に電源を供給する導線を、前記実
装領域全体にわたって曲折させて配線するとともに、前
記半導体装置の表側を前記基板の表面に対向させて実装
することを特徴とする記憶内容の解読防止方法。
1. A conducting wire for supplying power to the semiconductor device is bent in a mounting area on a substrate for mounting a semiconductor device having a storage means for storing stored contents by supply of power, over the entire mounting area. A method for preventing decipherment of stored contents, comprising wiring and mounting the semiconductor device so that a front side of the semiconductor device faces a surface of the substrate.
【請求項2】 半導体装置の表側を基板表面に対向させ
て実装するときに前記半導体装置のパッドと接続される
接点を備え、かつ、前記半導体装置に電源を供給するた
めの導線を前記半導体装置の実装領域全体にわたって曲
折して配線したことを特徴とする記憶内容の解読防止用
基板。
2. A semiconductor device having a contact that is connected to a pad of the semiconductor device when the front side of the semiconductor device is mounted so as to face the substrate surface, and a conductive wire for supplying power to the semiconductor device. A board for preventing decoding of stored contents, which is formed by bending and wiring over the entire mounting area.
JP5349622A 1993-12-28 1993-12-28 Method and substrate for prevention against decoding of storage contents Withdrawn JPH07200414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5349622A JPH07200414A (en) 1993-12-28 1993-12-28 Method and substrate for prevention against decoding of storage contents

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5349622A JPH07200414A (en) 1993-12-28 1993-12-28 Method and substrate for prevention against decoding of storage contents

Publications (1)

Publication Number Publication Date
JPH07200414A true JPH07200414A (en) 1995-08-04

Family

ID=18404987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5349622A Withdrawn JPH07200414A (en) 1993-12-28 1993-12-28 Method and substrate for prevention against decoding of storage contents

Country Status (1)

Country Link
JP (1) JPH07200414A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072328A (en) * 1997-09-25 2000-06-06 Rohm, Co., Ltd. IC devices with a built-in circuit for protecting internal information
KR100365726B1 (en) * 1999-12-23 2002-12-26 한국전자통신연구원 Tamper resistant mechanism for cryptoprocessor package
EP2426616A1 (en) 2010-09-02 2012-03-07 Canon Kabushiki Kaisha Semiconductor integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072328A (en) * 1997-09-25 2000-06-06 Rohm, Co., Ltd. IC devices with a built-in circuit for protecting internal information
KR100365726B1 (en) * 1999-12-23 2002-12-26 한국전자통신연구원 Tamper resistant mechanism for cryptoprocessor package
EP2426616A1 (en) 2010-09-02 2012-03-07 Canon Kabushiki Kaisha Semiconductor integrated circuit device

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