JPH07199871A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To realize an image display capable of reducing a flicker phenomenon. CONSTITUTION:The difference of lengths of voltage impressing times at the times of AC. driving of odd number and even number fields caused by an interlaced scanning is eliminated by delaying a video signal at the time of the odd number field by an 1/2 H with an 1/2 H delay line 11 by providing a synchronization processing circuit 15 discriminating odd number and even number fields from a video signal and outputting a field discrimination signal, the 1/2H delay line 11 delaying the video signal of the odd number fields by the 1/2H, an analog multiplexer 12 switching an input signal so as to pass through the video signal as it is or pass an 1/2H delayed signal based on the field discrimination signal, a polarity inverting circuit 13 inverting the polarity of the video signal so that voltage impressing times of positive and negative sides become equal according to the field discrimination signal and a controller 16 controlling a source driver 22 and a gate driver 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for a liquid crystal projector, a liquid crystal television, etc., and more particularly to a liquid crystal display device using an active matrix panel.

[0002]

2. Description of the Related Art In a conventional NTSC television, it is specified that a screen having 525 scanning lines and an aspect ratio of 3: 4 is formed and 30 screens are produced in one second. Also,
As a method of scanning when creating a screen, interlace scanning is specified, and horizontal / vertical scanning is performed twice for every 262.5 lines. In this interlaced scanning, one vertical scanning is called a field scanning, and a scanning for displaying the entire one screen by two field scanning is called a frame scanning. Since one screen is displayed by scanning two fields of the video signal during this frame scanning period, the screen display cycle (frame frequency) is 1/60 second.

In the NTSC system television, the TFT is
When the number of effective scan electrodes of the liquid crystal display panel is 220, the same scan electrode is scanned in two field scans within one frame.

Further, the TFT liquid crystal display panel is driven and controlled by a scanning electrode drive circuit (not shown) 220.
Scanning electrodes X1 to X220, and 280 signal electrodes Y1 to be driven and controlled by a signal electrode driving circuit (not shown).
Y280 is provided, and these scan electrodes X1 to X are provided.
At each intersection of 220 and each of the signal electrodes Y1 to Y280, as shown in FIG.
R21 and TR22 are arranged and each transistor TR1
The gate electrodes G of 1, TR12, TR21 and TR22 are
Connected to the scan electrodes X1 and X2, the source electrode S is connected to the signal electrodes Y1 and Y2, the drain electrode D is connected to the capacitor Cs and the liquid crystal display element LCD, and the capacitor Cs and the liquid crystal display element LCD are connected to each other. VC of the same potential
S and VCOM are applied.

Each transistor T connected to each intersection
R11, TR12, TR21, and TR22 are turned on by the scan signal sequentially input to the scan electrodes X1 and X2 by the scan electrode drive circuit 7 for each horizontal scan, and the signal electrode drive circuit 8 sequentially outputs signals according to the horizontal scan. Electrode Y
Color video signals input to the Y1 and Y2 are transistor TR
When the capacitors Cs connected to the drain electrode D through the source electrodes S of 11, TR12, TR21 and TR22 are sequentially accumulated, the liquid crystal display element LCD is displayed.

FIG. 2 is a timing chart of signal waveforms for driving the TFT-LCD.

In FIG. 2, VG and VID are signals of the scanning line and the signal line, which are applied to the gate and the source of the TFT. NTSC video signal is interlaced 2
It consists of two fields, and the first field and the second field are combined into one frame to form one picture.

When the TFT is turned on, the pixel electrode potential VP becomes equal to the potential VID of the signal line, the TFT is turned off and the signal written in the liquid crystal capacitance and the storage capacitance is held, but TF
At the moment when T is turned off, the pixel electrode potential VP shifts by a certain voltage ΔV. This is due to the parasitic capacitance between the gate and drain of the TFT and the capacitive coupling between the liquid crystal capacitance and the storage capacitance.

Since this shift voltage always lowers the pixel electrode potential VP regardless of the polarity of the video signal, the common electrode potential VCOM on the color filter side is set lower than the center potential VC of the signal line by this shift amount. To do. As a result, the voltage VLC applied to the liquid crystal becomes a region shown by the hatched portion in FIG.

[0010]

However, in reality, since the liquid crystal has anisotropy of dielectric constant, the liquid crystal capacitance changes depending on the amplitude of the video signal, and the shift voltage ΔV also changes. Therefore, even if the common electrode potential VCOM is optimized, the voltage VLC applied to the liquid crystal cannot have a completely symmetrical waveform. The resulting asymmetrical component becomes an optical component and is recognized as flicker (flicker on the screen).

As one of the causes for generating the asymmetrical component, attention is paid to the difference in voltage application time between fields due to the interlaced scanning of the television.

That is, as shown in the video signal waveform of each field in FIG. 3, the length T1 of the odd field is 263H in the NTSC system because of the interlaced scanning.
(H: 1 horizontal scanning period), and the length T2 of the even field is 262H. That is, the times T1 and T2 during which the voltage is applied to the liquid crystal do not become exactly the same on the positive side and the negative side, and the relationship is T1 = T2 + 1H.

As described above, in addition to the cause of the imbalance in the value of the shift voltage ΔV, imbalance due to time also occurs, which is one of the causes of flicker.

Therefore, an object of the present invention is to provide an image display device capable of reducing the flicker phenomenon.

[0015]

The invention according to claim 1 is
In order to achieve the above object, one interlaced two fields are combined into one frame to form one screen, and a liquid crystal display device for displaying an image by driving a liquid crystal panel by alternating current driving which is inverted for each field. In the above, the voltage application time during AC driving of the odd field and the even field is made equal.

According to a second aspect of the present invention, two interlaced fields are combined into one frame to form one picture, and a liquid crystal panel is driven by alternating current driving for reversing each field to display an image. In the liquid crystal display device for displaying, the difference in the length of the voltage application time during the AC drive between the odd field and the even field due to the interlace scanning is removed by delaying the video signal in the odd field. There is.

The delay of the video signal is performed by a delay means for delaying the video signal in the odd field by 1 / 2H (H: 1 horizontal scanning period), for example. There is.

[0018]

According to the first, second and third aspects of the present invention, for example, a delay circuit for delaying the video signal in the odd field is provided in the preceding stage of the polarity inversion circuit for inverting the video signal for each field. The difference in the length of the voltage application time during the AC driving of the odd field and the even field due to the scanning is removed by delaying the video signal in the odd field.

Therefore, the DC imbalance can be eliminated and the flicker phenomenon can be alleviated by equalizing the voltage application time during the AC driving of the odd field and the even field.

[0020]

EXAMPLES Examples will be described below with reference to FIGS. 1 and 2.

1 and 2 are views showing an embodiment of a liquid crystal display device.

FIG. 1 is a circuit diagram of a video signal processing section of a liquid crystal display device. In this figure, the video signal processing section is (1
/ 2) H delay line 11, analog multiplexer 12, polarity inversion circuit 13, LCD driver circuit 14, synchronization processing circuit 15, and controller 16.

The LCD driver circuit 14 is used for the liquid crystal panel 2
1, a source driver 22 in the horizontal direction and a gate driver 23 in the vertical direction. The liquid crystal panel 21 is driven for gradation display by the source driver 22, the gate driver 23 and the controller 16 which controls these drivers.

The synchronization processing circuit 15 is a circuit for outputting a synchronization signal for controlling the timing of the controller 16 from the composite video signal (composite video signal), and specifically, a vertical synchronization signal and a horizontal synchronization signal from the composite video signal. It separates and transmits to the controller 16.

The (1/2) H delay line 11 is a delay circuit which delays and outputs the video signal of the odd field by (1/2) H.

The analog multiplexer 12 passes the video signal as it is based on the field discrimination signal from the synchronous processing circuit 15 (1/2) H delay line 11
Is a switching circuit for switching and outputting the input signal so as to pass the (1/2) H delay signal passing through.

The polarity reversing circuit 13 is a circuit for reversing the polarity of the video signal output from the analog multiplexer 12 according to the field discrimination signal from the synchronization processing circuit 15 so that the voltage application times on the positive side and the negative side become equal. .

In this case, the video signal is (1/2) when the odd field is selected from the odd field and the even field.
By delaying H, the voltage application times on the positive side and the negative side are made equal.

The controller 16 outputs a control signal to each section based on the synchronization signal or the like input from the synchronization processing circuit 15 to control each section and the entire apparatus.

The controller 16 uses the source driver 2
2. Other control signals are output to the gate driver 23 to control these drivers, and the synchronous processing circuit 1
Other control signals to be output to these drivers based on the synchronizing signal or the like input from the circuit 5 are also delayed by (1/2) H for the video signal in the odd field in synchronization with the inverted output of the polarity inversion circuit 13. Control to output.

That is, in the liquid crystal display device of this embodiment, the polarity inversion circuit 13 which inverts the video signal for each field.
In the preceding stage, a (1/2) H delay line 11 and an analog multiplexer 12 for delaying a video signal in an odd field are added.

Next, the operation of this embodiment will be described.

As shown in FIG. 1, the composite video signal is (1 /
2) H delay line 11, analog multiplexer 1
2 and the synchronization processing circuit 14.

The composite video signal input to the (1/2) H delay line 11 is (1/1)
2) It is delayed by H and output to the input terminal B of the analog multiplexer 12.

Further, the composite video signal is directly input to the input terminal A of the analog multiplexer 12,
The analog multiplexer 12 and the video signal input to the input terminal A based on the field discrimination signal from the synchronization processing circuit 15 and the (1/2) H delay line 11 (1 /
2) select a signal delayed by H, specifically, in the case of an odd field video signal, select a signal delayed by (1/2) H from the (1/2) H delay line 11. Also, in the case of an even field, the input signal is switched and output so that the input video signal is directly output as it is.

The video signal from the analog multiplexer 12 is input to the polarity inverting circuit 13, and the polarity inverting circuit 1
In 3, the polarity of the video signal output from the analog multiplexer 12 is inverted and output according to the field determination signal from the synchronization processing circuit 15 so that the positive side voltage application time and the negative side voltage application time become equal.

In the horizontal source driver 22 and the vertical gate driver 23, the video signal from the controller 16 (1 in the case of an odd field on the side of the horizontal source driver 22 and the vertical gate driver 23) is also used. / 2) A drive signal for delaying H is output.

The liquid crystal panel 21 is driven for display by a source driver 22, a gate driver 23 and a controller 16 which controls these drivers.

As described above, the time T1 and T2 during which the voltage is applied to the liquid crystal as shown in FIG. 2 by delaying the video signal by (1/2) H in the odd field is: T1 = T2 = 262. It becomes 5H and the factor of DC imbalance is reduced.

As described above, the liquid crystal display device of this embodiment discriminates an odd field and an even field from the video signal and outputs the field discrimination signal to the synchronization processing circuit 15 and the video signal of the odd field to (1 / 2) H delay line 11 which outputs with a delay of H, and
An analog multiplexer 12 that switches and outputs the input signal so that the video signal is passed through as it is or the (1/2) H delay signal is passed through the (1/2) H delay line 11 based on the field discrimination signal. A polarity inversion circuit 13 that inverts the polarity of the video signal output from the analog multiplexer 12 so that the voltage application times on the positive side and the negative side are equal according to the field determination signal, and other control signals to the source driver 22 and the gate driver 23. And a controller 16 for controlling these drivers by outputting the difference between the odd-numbered field and the even-numbered field due to the interlace scanning. By delaying the video signal in the odd field by (1/2) H by 11, Since followed by removal, can odd field and the voltage application time during the AC drive of the even field to eliminate DC imbalance by equalizing, it is possible to reduce the flickering.

Although the (1/2) H delay line 11 is used as the (1/2) H delay circuit in this embodiment, the present invention is not limited to this, and for example, an A / D converter + line memory + D / Even if it is realized by an A converter, the same effect can be obtained.

Further, in the present embodiment, the video display system has N
Although the TSC system is used, it goes without saying that the same method can be applied to any system that performs interlaced scanning (PAL system or the like).

Further, although the liquid crystal display device is applied to the TFT active matrix in the present embodiment, the present invention is not limited to this, and the kind, the number and the arrangement of the liquid crystal panels are arbitrary, for example, MIM (Metal). Insulator Metal)
LC driven by active matrix using diodes
It goes without saying that D can be similarly changed.

Further, it goes without saying that the circuits and matrixes constituting the video signal processing section, the number of gates, their types, etc. are not limited to those in the above-mentioned embodiments.

[0045]

According to the first, second and third aspects of the present invention, since the voltage application time during the AC driving of the odd field and the even field is made equal, the AC application of the odd field and the even field is performed. By making the voltage application times equal, DC imbalance can be eliminated, flicker can be reduced, and reduction in image sticking can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a video signal processing section of a first embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart of signal waveforms of voltages applied to the liquid crystal panel of the liquid crystal display device of the same example.

FIG. 3 is a timing chart of a video signal waveform of each field of the liquid crystal display device of the same example.

FIG. 4 is a detailed configuration diagram of a conventional TFT liquid crystal display panel.

[Explanation of symbols]

 11 (1/2) H delay line 12 analog multiplexer 13 polarity inverting circuit 14 LCD driver circuit 15 synchronization processing circuit 16 controller 21 liquid crystal panel 22 source driver 23 gate driver

Claims (3)

[Claims] 1. A liquid crystal display device in which two interlaced fields are combined to form one screen as one frame, and a liquid crystal panel is driven by alternating current driving for inverting each field to display an image. A liquid crystal display device characterized in that the voltage application time during alternating current driving of the odd field and the even field is made equal. 2. The two interlaced fields are combined into one frame to form one picture, and
In a liquid crystal display device that displays an image by driving a liquid crystal panel by alternating-current driving that inverts every one field, the difference in the length of voltage application time during alternating-current driving of odd fields and even fields caused by interlace scanning A liquid crystal display device characterized in that a video signal in an odd field is removed by delaying it. 3. The delay of the video signal is performed by delay means for delaying the video signal in an odd field by 1 / 2H (H: 1 horizontal scanning period). Liquid crystal display device.