JPH07198771A - Device for detecting fault of signal line - Google Patents

Abstract

PURPOSE:To discriminate the disconnection of a signal line and the short- circuiting of the signal line to two common power lines by connecting a fault detecting resistor to a negative-side common power line in series to an output means and judging the faulty state of the signal line in accordance with the electrical variable to the fault detecting resistor. CONSTITUTION:The voltage level applied across a fault detecting resistor 43 is created in accordance with three fault modes by means of a transmitting-side resistor 37 and receiving-side resistor 41 which are respectively incorporated in a sensor 21 and converter 23 and connect a signal line 25 to a positive-side power line 27 by connecting a negative-side power line to the resistor 43 in series with a transistor 33 incorporated in the sensor 21. When the signal line 25 short-circuits to the positive-side power line 27, consequently, the voltage across the resistor 43 becomes the difference between the power supply voltage and the voltage drop at the transistor 33 and, when the signal line 25 is disconnected, the voltage becomes the difference between the power supply voltage and the voltage drops at the transmitting-side resistor 37 and transistor 33. When the signal line 25 short-circuits to the negative-side power line 29, the voltage becomes 0V.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal line failure detecting device for detecting a failure state of an output signal line from a state detecting means for outputting an electric signal in response to a physical or scientific change in state.

[0002]

2. Description of the Related Art As a conventional signal line failure detecting device of this type, there is one disclosed in, for example, Japanese Patent Laid-Open No. 5-107292. As shown in FIG. 5, this failure detection device inputs a sensor 1 that outputs an electrical signal in response to a physical or chemical state change and an output signal of this sensor 1 to convert it to another signal form. And a converter 3 for

The sensor 1 and the converter 3 are connected by a harness 11 composed of two common power lines 5 and 7 and a signal line 9. The sensor 1 includes a transistor 13 that outputs a variable as a current change. When the transistor 13 increases or decreases the current flowing due to its physical or chemical change,
The voltage drop of the resistor 15 connected in series with the transistor 13 changes, and the signal transmitted to the converter 3 becomes a signal corresponding to the physical / chemical change.

The converter 3 is an A / D converter 17 for converting an analog signal sent from the sensor 1 into a digital signal.
6, the sensor output signal input to the A / D converter 17 changes in accordance with the amount of physical / chemical displacement, as shown in FIG. Is determined by.

In FIG. 6, when the signal input to the A / D converter 17 is normal, the A / D converter 17
The voltage V _o applied to is between V ₃ and V ₄ and has a value proportional to the amount of change. When any of the power supply lines 5 and 7 or the signal line 9 is broken, the voltage V _o is
The value deviates from V ₄ ≦ V _o ≦ V _{3 in the} normal range and becomes V _o ≧ V ₂ or V _o ≦ V _{5 in} the abnormal voltage range, and the CPU 19 determines that the wire breakage abnormality has occurred in the harness 11.

[0006]

However, although such a conventional failure detection device can detect a failure when any of the power supply lines 5 and 7 or the signal line 9 is broken, the signal line 9 is the power supply line. 5 and 7 have a problem that it is not possible to discriminate when a short circuit occurs due to a solder bridge or a broken coating.

Therefore, the present invention is directed to disconnection of the signal line and
The purpose is to be able to identify a short circuit between two common power lines of a signal line.

[0008]

In order to achieve the above object, the present invention provides a state detecting means for outputting an electric signal in response to a physical or scientific state change, and an output signal of the state detecting means. Of the output signal from the state detecting means, and two common power lines for supplying power to both the converting means and the state detecting means. Connected by a signal line for sending to the conversion means, the positive side common power supply line on the state detection means side and the signal output terminal are connected by a transmission side resistance, and the positive side common power supply on the conversion means side. The line and the signal input terminal are connected by a resistance on the receiving side, and the state detecting means is provided with an output means for outputting a variation as a current change, and a failure detecting resistance is connected in series with the output means to the negative common power supply line. However, this fault detection There a structure in which a failure determination means for determining a fault condition in response to the electrical variable according to.

[0009]

According to the signal line failure detection device having such a configuration, when the signal line is connected to the positive power supply line, the voltage at the failure detection resistor is a voltage drop at the output means from the power supply voltage. If the signal line is disconnected, the same voltage will be the value obtained by subtracting the voltage drop at the transmission side resistance and the output means from the power supply voltage, and the signal line will be shorted to the negative power supply line. The same voltage is 0V
Becomes The change in the electrical variable in the failure detection resistance is taken in by the failure determination means, and the above three failure states can be determined.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the overall structure of a signal line failure detection apparatus according to an embodiment of the present invention. This failure detection device includes a sensor 21 as a state detection unit that outputs an electrical signal in response to a physical or scientific state change, and a conversion unit that receives a signal from the sensor 21 and converts it into another signal form. And a converter 23 as The sensor 21 and the converter 23 have a signal line 25.
And two common power lines 2 from a constant voltage power source (not shown)
7, 29 are connected, and these constitute a harness 31.

The sensor 21 is provided with a transistor 33 as an output means for outputting the variable as a current change.
A clock signal is input to the base of the transistor 33 via the resistor 34, and one end of the power supply line 2 has a positive side.
The other end of the pull-up resistor 35 connected to 7 is connected. In the pull-up resistor 35, the signal line 25 is the power supply line 27.
Even when short-circuited, the transistor 33 functions to operate reliably. The collector of the transistor 33 is connected to the other end of the transmission side resistor 37, one end of which is connected to the power supply line 27.

In the converter 23, an interface circuit 39 having a high input impedance for receiving a signal from the sensor 21 via the signal line 25 is provided, and a receiving side resistor 41 is connected between the signal line 25 and the power supply line 27. Has been done.

A failure detection resistor 43 is connected to the emitter of the transistor 33 in the sensor 21. An A / D converter 45 is connected to the transistor 33 side of the failure detection resistor 43, and the A / D converter 45 monitors the voltage across the failure detection resistor 43 and the on / off state of the output signal to the signal line 25. A CPU 47 is connected as a failure determination unit including a microcomputer for determining failure detection in the harness 31.

On the other hand, the base of the transistor 33 is connected to a level conversion circuit 49 for converting a signal level into an acceptance level of the CPU 47 when the CPU 47 monitors the output signal to the signal line 25.

FIG. 2 shows output waveforms of the clock signal S _i input to the transistor 33 and the sensor signal S ₀ output from the transistor 33 to the signal line 25. According to this, for the clock signal S _i , the transistor 33
There in V ₁ voltage when turned on the voltage 0V at the time of off, for the sensor signals S _0, the transistor 33 is the voltage V ₃ at the time of ON voltage with respect to V ₂ (= V ₁₎ in the OFF , V ₃ V _CE + R _x × (V ₁ −V _CE ) / (R _y // R _z ), where V ₁ : power supply voltage V _CE : collector-emitter voltage drop of transistor 33 R _x : failure detection resistance The resistance value of 43 is R _y : the resistance value of the transmission-side resistor 37 R _z : The resistance value of the reception-side resistor 41 is R _y // R _z = 1 / (1 / R _y + 1 / R _z ). As a result, the output voltage V ₃ when the transistor 33 is turned on, that is, the sensor signal S ₀ becomes an output according to the displacement amount, and the sensor function is exhibited.

During such a sensor operation, three failure modes will be described, in which the signal line 25 is disconnected, the signal line 25 is short-circuited to the power line 27, and the signal line 25 is short-circuited to the power line 29. To do.

FIG. 3 is a flow chart showing the control operation of the CPU 47 when the above three failure modes occur. According to this, immediately after the rise of the monitor signal S _m output from the level conversion circuit 49 (step 101), the A / D
The output signal from the converter 45 is taken in (step 1
03). FIG. 4 shows a state in which the A / D converter 45 is activated immediately after the transistor 33 is turned on, that is, immediately after the monitor signal S _m rises, and a waveform of the voltage across the resistor R _x . Next, after determining the three failure modes (step 105), the failure modes are recorded in a memory such as a built-in RAM (step 107).

Although the level conversion circuit 49 inverts the signal S _i in FIG. 4, it may be non-inverted. However,
In this case, the A / D converter 45 is activated immediately after the monitor signal S _m falls.

Next, the voltage V _x across the fault detection resistor 43 when the transistor 33 is on and in the normal state and in the three fault modes will be described.

(1) Normal state V _x = R _x × (V ₁ −V _CE ) / (R _y // R _z + R _x ) R _x × (V ₁ −V _CE ) / (R _y // R _z ) However, R _y // R _z >> R _x (2) When the signal line 25 is short-circuited to the power line 27 V _x = V ₁ −V _CE (3) When the signal line 25 is broken V _x = R _x × (V ₁ −V _CE ) / (R _y + R _x ) R _x × (V ₁ −V _CE ) / R _y However, R _y >> R _x (4) When the signal line 25 is short-circuited to the power supply line 29 V _x = 0 The magnitude relation of V _{x in} the above (1) to (4) is (2)>(1)>(3)> (4).

As described above, the transmission-side resistor 37 and the reception-side resistor 41 have the failure detecting resistor 4 depending on the three failure modes.
3 creates the voltage level applied to
It is possible to determine the above three failure modes due to the difference in the voltage level.

The internal impedance of the interface circuit 39 may be a low impedance as long as the value is known and there is no problem in distinguishing the failure modes.

[0024]

As described above, according to the present invention, the failure detecting resistor is connected to the negative power supply line in series with the output means provided in the state detecting means, and the state detecting means and the converting means are respectively connected. The signal line is disconnected, the signal line is disconnected to the positive side power line, and the negative side power source is connected to the power line by the transmission side resistance and the reception side resistance that connect the signal line and the positive side power supply line. Since the signal level appearing in the failure detection resistor is created according to the three failure modes of short to the line,
The above three failure modes can be determined, and the failure mode can be identified with certainty.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an overall configuration of a signal line failure detection apparatus according to an embodiment of the present invention.

2 is a waveform diagram of an input signal and an output signal of a transistor in the failure detection device of FIG.

3 is a flowchart showing a control operation of a CPU in the failure detection device of FIG.

FIG. 4 is a waveform diagram of various signals in the failure detection circuit of FIG.

FIG. 5 is a circuit diagram showing an overall configuration of a signal line failure detection device according to a conventional example.

6 is a characteristic diagram showing a relationship between a displacement amount and a sensor output signal in the failure detection device of FIG.

[Explanation of symbols]

 21 sensor (state detecting means) 23 converter (converting means) 25 signal lines 27, 29 power supply line 33 transistor (output means) 37 transmission side resistance 41 reception side resistance 43 failure detection resistance 47 CPU (failure determination means)

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[Procedure amendment]

[Submission date] June 14, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

FIG. 2 shows output waveforms of the clock signal S _i input to the transistor 33 and the sensor signal S ₀ output from the transistor 33 to the signal line 25. According to this, for the clock signal S _i , the transistor 33
There in V ₁ voltage when turned on the voltage 0V at the time of off, for the sensor signals S _0, the transistor 33 is the voltage V ₃ at the time of ON voltage with respect to V ₂ (= V ₁₎ in the OFF , V ₃ ≈V _CE + R _x × (V ₁ −V _CE ) / (R _y // R _z ), where V ₁ : power supply voltage V _CE : collector-emitter voltage drop of transistor 33 R _x : failure detection The resistance value R _y of the resistor 43: the resistance value of the transmission side resistor 37 R _z : the resistance value of the reception side resistor 41 R _y // R _z = 1 / (1 / R _y + 1 / R _z ). As a result, the output voltage V ₃ when the transistor 33 is turned on, that is, the sensor signal S ₀ becomes an output according to the displacement amount, and the sensor function is exhibited.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

(1) Normal state V _x = R _x × (V ₁ −V _CE ) / (R _y // R _z + R _x ) ≈R _x × (V ₁ −V _CE ) / (R _y // R _z ) However, R _y // R _z >> R _x (2) When the signal line 25 is short-circuited to the power line 27 V _x = V ₁ −V _CE (3) When the signal line 25 is broken V _x = R _{x × (V 1 -V CE) /} (R y + R x) ≒ R x × (V 1 -V CE) / R y However, if R _y »R _x (4) signal line 25 is shorted to the power supply line 29 V _x = 0 The magnitude relation of V _{x in} the above (1) to (4) is (2)>(1)>(3)> (4).

Claims (1)

[Claims] 1. A state detecting means for outputting an electrical signal in response to a physical or scientific state change, and a converting means for receiving an output signal of the state detecting means and converting the signal into another signal form. The conversion means and the state detection means are connected by two common power supply lines for supplying power to the two and a signal line for sending an output signal from the state detection means to the conversion means. The common power line on the positive side and the signal output terminal are connected by the resistance on the transmitting side, and the common power line on the positive side and the signal input terminal are connected by the resistance on the receiving side on the conversion means side. The detection means includes an output means for outputting the variable as a current change, and a failure detection resistor is connected in series with the output means to the common power supply line on the negative side,
A failure detecting device for a signal line, comprising failure judging means for judging a failure state according to an electrical variable applied to the failure detecting resistor.