JPH07193607A - Bpsk demodulation circuit - Google Patents

Bpsk demodulation circuit

Info

Publication number
JPH07193607A
JPH07193607A JP33232293A JP33232293A JPH07193607A JP H07193607 A JPH07193607 A JP H07193607A JP 33232293 A JP33232293 A JP 33232293A JP 33232293 A JP33232293 A JP 33232293A JP H07193607 A JPH07193607 A JP H07193607A
Authority
JP
Japan
Prior art keywords
bpsk
signal
circuit
inversion
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33232293A
Other languages
Japanese (ja)
Inventor
Sachikazu Kita
祥和 喜多
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP33232293A priority Critical patent/JPH07193607A/en
Publication of JPH07193607A publication Critical patent/JPH07193607A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To prevent the inversion at BPSK demodulation by having only to add a simple configuration component to a receiver side. CONSTITUTION:An input BPSK signal is demodulated by a BPSK demodulator 2. Furthermore, the input BPSK signal is detected by a carrier detection circuit 3, compared with a detection level set by resistors 34, 35 at a comparator 36, which provides a carrier detection output. A one-shot pulse circuit 4 generates a negative pulse having a predetermined pulse width at the leading of the detection output and gives the pulse to an inversion correction circuit 5. A D flip-flop 51 of the inversion correction circuit 5 latches a demodulation signal at said leading of the pulse. The latched high level signal and the demodulation signal are given to an exclusive OR circuit 52, from which a correct demodulation signal with corrected inversion is outputted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、復調時の反転現象を防
止することができるBPSK復調回路に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BPSK demodulation circuit capable of preventing an inversion phenomenon during demodulation.

【0002】[0002]

【従来の技術】デジタル通信の一つに送信データを任意
のキャリアで2相変調して得た2相PSK(以下BPS
Kという)信号を送信するBPSK通信がある。
2. Description of the Related Art Two-phase PSK (hereinafter referred to as BPS) obtained by two-phase modulation of transmission data with an arbitrary carrier is one of digital communications.
There is a BPSK communication that sends a signal (K).

【0003】このBPSK信号を復調するBPSK復調
回路においては、基準位相が0かπかを確定できないた
め、復調信号の反転現象が起こる場合がある。従来、こ
の反転現象を防止するためには、送信機側で図6に示す
ような加算器10と遅延回路11を用いた符号化器であ
らかじめ差動符号化し、受信器側で復調されたビット系
列を図7に示すような同様に加算器10と遅延回路11
を用いた復号器で復号する方法が採用される。
In the BPSK demodulation circuit for demodulating the BPSK signal, it is not possible to determine whether the reference phase is 0 or π, so that the demodulation signal inversion phenomenon may occur. Conventionally, in order to prevent this inversion phenomenon, a bit previously demodulated on the transmitter side by an encoder using an adder 10 and a delay circuit 11 as shown in FIG. 6 and demodulated on the receiver side is used. Similarly, as shown in FIG. 7, the series is added by an adder 10 and a delay circuit 11.
A method of decoding with a decoder using is adopted.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記方
法では、送信側及び受信側でそれぞれ符号化器及び復号
器が必要となりコストアップの原因となっていた。
However, in the above method, an encoder and a decoder are required on the transmitting side and the receiving side, respectively, which causes a cost increase.

【0005】本発明は上記欠点を解消するものであり、
受信器側で簡単な構成を付加するだけで反転現象が防止
できるBPSK復調回路を提供するものである。
The present invention solves the above drawbacks,
It is an object of the present invention to provide a BPSK demodulation circuit capable of preventing an inversion phenomenon by simply adding a simple configuration on the receiver side.

【0006】[0006]

【課題を解決するための手段】本発明は、BPSK信号
を復調するBPSK復調器と、前記BPSK信号のキャ
リアが所定レベル以上であることを検出するキャリア検
出回路と、前記キャリア検出回路出力に基づき少なくと
も前記BPSK信号のプリアンブル期間よりも短いパル
ス幅のパルスを発生するパルス発生回路と、このパルス
のタイミングで前記BPSK信号のプリアンブル期間の
BPSK復調信号のレベルにより前記BPSK復調信号
に反転が発生しているか否かを判別し、反転が発生した
ときには反転を訂正する反転訂正回路とを備えてなるB
PSK復調回路である。
The present invention is based on a BPSK demodulator for demodulating a BPSK signal, a carrier detection circuit for detecting that the carrier of the BPSK signal is above a predetermined level, and an output of the carrier detection circuit. A pulse generation circuit for generating a pulse having a pulse width shorter than at least the preamble period of the BPSK signal, and the inversion of the BPSK demodulated signal depending on the level of the BPSK demodulated signal in the preamble period of the BPSK signal occurs at the timing of this pulse. An inversion correction circuit that determines whether or not there is an inversion and corrects the inversion when an inversion occurs.
It is a PSK demodulation circuit.

【0007】[0007]

【作用】本発明では、BPSK信号のプリアンブル期間
の復調信号のレベルが1か0かによって反転が発生して
いるか否かを判別し、反転が発生している場合、この反
転を訂正して出力することにより、受信器側で簡単に反
転が訂正できる。
According to the present invention, it is determined whether or not the inversion has occurred depending on whether the level of the demodulated signal in the preamble period of the BPSK signal is 1 or 0. If the inversion has occurred, the inversion is corrected and output. By doing so, the inversion can be easily corrected on the receiver side.

【0008】[0008]

【実施例】以下、図面に従って本発明の一実施例を説明
する。図1は本実施例回路のブロック図であり、1はB
PSK変調されたBPSK信号が入力される入力端子、
2はこのBPSK信号を復調するBPSK復調器、3は
BPSK信号のキャリアの有無を検出するキャリア検出
回路、4はこのキャリア検出出力に基づいて任意のパル
ス幅のパルスを1回発生するワンショットパルス回路、
5はDフリップフロップ51及びエクスクルーシブOR
回路52からなる反転訂正回路、6は反転が訂正された
BPSK復調信号が出力される出力端子である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the circuit of this embodiment, where 1 is B
An input terminal to which a PSK-modulated BPSK signal is input,
Reference numeral 2 is a BPSK demodulator for demodulating this BPSK signal, 3 is a carrier detection circuit for detecting the presence or absence of carriers of the BPSK signal, and 4 is a one-shot pulse for generating once a pulse having an arbitrary pulse width based on this carrier detection output. circuit,
5 is a D flip-flop 51 and an exclusive OR
An inversion correction circuit composed of the circuit 52, and 6 is an output terminal for outputting the inverted BPSK demodulated signal.

【0009】次に、上記回路の動作を図3と共に説明す
る。まず、送信データaのプリアンブル部(立ち上がり
部)をローと規定するものとする。この送信データが数
10MHzのキャリアで2相変調されたBPSK信号b
が入力端子1に入力される。このBPSK信号はBPS
K復調器2で復調される。その際にデータの反転が発生
したとすると図3cのようになる。
Next, the operation of the above circuit will be described with reference to FIG. First, the preamble part (rising part) of the transmission data a is defined as low. This transmission data is a two-phase modulated BPSK signal b with a carrier of several tens of MHz
Is input to the input terminal 1. This BPSK signal is BPS
Demodulated by the K demodulator 2. If data inversion occurs at that time, the result is as shown in FIG. 3c.

【0010】一方、キャリア検出回路3は図2に示す様
にコンデサー30、32、ダイオード31及び抵抗23
で検波され(図3d)、抵抗34、35で設定される検
波レベルと比較器36で比較され、キャリア検出出力e
を出力する。
On the other hand, as shown in FIG. 2, the carrier detection circuit 3 includes capacitors 30, 32, a diode 31, and a resistor 23.
(FIG. 3d), the detection level set by the resistors 34 and 35 is compared with the comparator 36, and the carrier detection output e
Is output.

【0011】そして、この出力dの立ち上がりでワンシ
ョットパルス回路4は所定のパルス幅の負のパルスfを
発生し、反転訂正回路5へ供給する。この反転訂正回路
5では、まず、Dフリップフロップ51でパルスfの立
ち上がりにおける復調信号cがラッチされる。このラッ
チされたハイの信号と復調信号cをエクスクルーシブO
R回路52に通すことによって、反転が訂正された正し
い復調信号gが出力される。
At the rising edge of the output d, the one-shot pulse circuit 4 generates a negative pulse f having a predetermined pulse width and supplies it to the inversion correction circuit 5. In the inversion correction circuit 5, the demodulation signal c at the rising edge of the pulse f is first latched by the D flip-flop 51. The latched high signal and demodulated signal c are exclusively O
By passing the signal through the R circuit 52, the correct demodulated signal g whose inversion has been corrected is output.

【0012】尚、BPSK復調器2出力に反転が発生し
ていないときは、Dフリップフロップ51出力はローと
なるため反転訂正回路6は復調出力を訂正することなく
そのまま出力する。
When the output of the BPSK demodulator 2 is not inverted, the output of the D flip-flop 51 is low, so the inversion correction circuit 6 outputs the demodulated output as it is without correction.

【0013】また、送信データaのプリアンブル部がハ
イと規定されている場合の実施例を図4及び図5に示
す。図4において図1と異なる点はエクスクルーシブO
R回路52出力にインバータ53が接続されている点の
みであり、反転訂正回路6は図5cのような復調信号の
場合に、図5hの様に訂正する。
An embodiment in which the preamble part of the transmission data a is defined to be high is shown in FIGS. 4 and 5. 4 is different from FIG. 1 in that the exclusive O
The only difference is that the inverter 53 is connected to the output of the R circuit 52, and the inversion correction circuit 6 corrects the demodulated signal as shown in FIG. 5c as shown in FIG. 5h.

【0014】[0014]

【発明の効果】上述の如く本発明によれば、受信器側で
簡単な構成を付加するだけで反転現象が防止できる。
As described above, according to the present invention, the inversion phenomenon can be prevented only by adding a simple structure on the receiver side.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例におけるBPSK復調回路の
ブロック図である。
FIG. 1 is a block diagram of a BPSK demodulation circuit according to an embodiment of the present invention.

【図2】キャリア検出回路の回路図である。FIG. 2 is a circuit diagram of a carrier detection circuit.

【図3】図1の要部波形図である。FIG. 3 is a waveform diagram of a main part of FIG.

【図4】本発明の他の実施例におけるBPSK復調回路
のブロック図である。
FIG. 4 is a block diagram of a BPSK demodulation circuit according to another embodiment of the present invention.

【図5】図4の要部波形図である。FIG. 5 is a waveform diagram of a main part of FIG.

【図6】従来の符号化器を示す図である。FIG. 6 is a diagram showing a conventional encoder.

【図7】従来の復号器を示す図である。FIG. 7 is a diagram showing a conventional decoder.

【符号の説明】[Explanation of symbols]

2 BPSK復調器 3 キャリア検出回路 4 ワンショットパルス回路 5 反転訂正回路 2 BPSK demodulator 3 Carrier detection circuit 4 One-shot pulse circuit 5 Inversion correction circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 BPSK信号を復調するBPSK復調器
と、 前記BPSK信号のキャリアが所定レベル以上であるこ
とを検出するキャリア検出回路と、 前記キャリア検出回路出力に基づき少なくとも前記BP
SK信号のプリアンブル期間よりも短いパルス幅のパル
スを発生するパルス発生回路と、 このパルスのタイミングで前記BPSK信号のプリアン
ブル期間のBPSK復調信号のレベルにより前記BPS
K復調信号に反転が発生しているか否かを判別し、反転
が発生したときには反転を訂正する反転訂正回路とを備
えてなるBPSK復調回路。
1. A BPSK demodulator for demodulating a BPSK signal, a carrier detection circuit for detecting that the carrier of the BPSK signal is at a predetermined level or higher, and at least the BP based on the output of the carrier detection circuit.
A pulse generation circuit for generating a pulse having a pulse width shorter than the preamble period of the SK signal, and the BPS according to the level of the BPSK demodulated signal in the preamble period of the BPSK signal at the timing of this pulse.
A BPSK demodulation circuit including an inversion correction circuit that determines whether or not inversion occurs in a K demodulation signal and corrects the inversion when inversion occurs.
JP33232293A 1993-12-27 1993-12-27 Bpsk demodulation circuit Pending JPH07193607A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33232293A JPH07193607A (en) 1993-12-27 1993-12-27 Bpsk demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33232293A JPH07193607A (en) 1993-12-27 1993-12-27 Bpsk demodulation circuit

Publications (1)

Publication Number Publication Date
JPH07193607A true JPH07193607A (en) 1995-07-28

Family

ID=18253671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33232293A Pending JPH07193607A (en) 1993-12-27 1993-12-27 Bpsk demodulation circuit

Country Status (1)

Country Link
JP (1) JPH07193607A (en)

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