JPH07193446A - Automatic predictive gain switching circuit - Google Patents

Abstract

PURPOSE:To provide an automatic predictive gain switching circuit for switching and setting a gain at real time corresponding to excessive or insufficient input signals. CONSTITUTION:The level of an input signal Si is set to 1/m by an attenuating amplifier 1, the level of an input signal (Si/m) is turned into a digital signal by a level deciding circuit 2, and this digital signal is stored in a recording memory 3 at prescribed time intervals. Based on the digital signals in the recording memory 3, a predictive arithmetic circuit 4 previously predicts the level of the input signal Si after the lapse of prescribed time at real time. Based on the value of this predicted level, the gain of a gain switching circuit 6 is automatically switched. With this circuit, the gain can be optimumly set before the level of the input signal Si exceeds the dynamic range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a predictive gain automatic switching circuit, which is used in, for example, image and audio measuring devices, recording devices, broadcasting devices, etc., and automatically performs optimum gain setting for an input signal level. Regarding the circuit.

[0002]

2. Description of the Related Art An example of a conventional predictive gain automatic switching circuit is shown in FIG.
Shown in. Here, the predictive gain automatic switching circuit predicts the input signal level in advance and automatically adjusts the gain so that the dynamic range of the currently set gain will be an appropriate level for the next input signal. It is a circuit for switching and setting the value of. The main purpose of providing this kind of circuit is
This is a preventive measure against an excessively small input and / or an excessively large input, and is particularly aimed at preventing generation of a distortion signal when an excessively large signal is input. The predictive gain automatic switching circuit shown in FIG. 3 is configured for such a purpose.

In the above-mentioned conventional example, the attenuation amplifier 1 also serving as a buffer amplifier for inputting the input signal Si to the level determination circuit 2, the level determination circuit 2 for determining the state of the signal level, and the gain switching circuit 6 for switching the gain are provided. The gain is switched according to the magnitude of the input signal Si and the dynamic range is set to the optimum value.

Further, as an open publication similar in purpose to the above-mentioned conventional example, there is an "output level control device" (Japanese Patent Laid-Open No. 1-23).
1510). This is related to a digital reproducing apparatus, and a reproducing level is recorded in advance, and a gain is appropriately set based on the recorded reproducing level, and a signal level monitor and a signal output time are digitally recorded on the assumption of digital recording. It is a method of delaying the gain and setting the gain so as not to exceed the dynamic range.

[0005]

However, in the above-described conventional automatic gain switching circuit, the signal level temporarily exceeds the dynamic range due to the delay in the timing from the determination of the signal level to the switching of the gain. The phenomenon is accompanied by problems that cannot be avoided. Further, the above-mentioned publication discloses delaying and processing a digital signal, and is not suitable for application to an analog signal processing device for the purpose of responding to an input signal in real time.

It is an object of the present invention to provide a predictive gain automatic switching circuit which performs gain switching setting in real time with respect to an excessively large and / or excessively small input signal.

[0007]

In order to achieve such an object, the predictive gain automatic switching circuit of the present invention comprises a predicting means for predicting in advance the level of an input signal after a predetermined time has elapsed, and a predicting means. A gain switching unit that switches the gain of an amplifier that amplifies or attenuates the input signal based on the predicted level value is provided, and the gain is automatically switched.

[0008]

According to the predictive gain automatic switching circuit of the present invention, the level of the input signal after a predetermined time has elapsed is preliminarily predicted in real time, and the gain of the amplifier is switched according to the predicted level. . Therefore, it becomes possible to process an excessive input signal that exceeds the dynamic range and / or an inappropriately small signal in real time.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the predictive gain automatic switching circuit according to the present invention will be described in detail with reference to the accompanying drawings. 1 and 2, there is shown an embodiment of the predictive gain automatic switching circuit of the present invention.

FIG. 1 shows the circuit configuration of the predictive gain automatic switching circuit according to the first embodiment, which roughly has two parts: an input signal level predicting circuit 10 and a gain switching circuit 6. The input signal level prediction circuit 10 includes an attenuation amplifier 1, a level determination circuit 2, a recording memory 3, a prediction calculation circuit 4 and a control circuit 5.

The attenuation amplifier 1 is for taking the input signal Si into the input signal level prediction circuit 10. The specific value of the gain 1 / m is set to an appropriate value that can cover the dynamic range with respect to the expected level of the input signal Si. This attenuation amplifier 1 outputs the input signal Si
Is output as an attenuation signal (Si / m).

The level judgment circuit 2 is provided with an attenuation signal (Si /
m) is divided into N levels and converted into N values or N digital signals Hj (Hj; H1 to HN). Since the level determination circuit 2 is required to have high speed, it is composed of N stages of analog comparators. However, an A / D converter may be used. The number of stages N is determined by the desired prediction accuracy and the like.

The recording memory 3 is a circuit for temporarily storing the digital signal Hj output from the level determination circuit 2. The time interval at which the digital signal Hj is taken in for storage is a predetermined cycle time T based on the storage command signal from the control circuit 5. The recording memory 3 stores and holds a predetermined number of digital signals (Hj (t-k) to Hj (t-1) to Hj (t0)) before k samples, which is a predetermined number from the present time t0. The predetermined number k is determined by the desired prediction accuracy, the frequency of the input signal, and the like.

The predictive calculation circuit 4 is a circuit section for performing a predictive calculation of the level of the next input signal based on the level data of the input signal stored in the recording memory 3. The content of the prediction calculation is, for example, to predict the level of the next signal from the amount of change in the input signal level. The relationship between the input signal Si (t0) at the current sampling time and the predicted input signal Si (t + 1) at the next sampling time is expressed by the following formula. Si (t + 1) = Si (t0) + T · dF (t) / dt (1) However, F (t) is a function based on sampling; F (t) = f
(Hj (t)).

A specific example of the equation (1) will be described below.
Now, it is assumed that the level differences between the N stages of the level determination circuit 2 are P equal intervals and the sampling time intervals are equal intervals.
The signal levels Si (t + 1) at the next sample time point t + 1 are predicted with the time points of three samples taken as t, t-1 and t-2. This prediction formula becomes the following formula (2). Si (t + 1) = Si (t0) + P · Hj (t0) {(Hj (t0) -Hj (t-1)) / (Hj (t-1) -Hj (t-2))} (2)

In the above prediction calculation circuit, the level intervals between the stages may be ununiform. For example, the intermediate region is wide and the region close to the upper limit is finely divided into levels, and the coefficient of the prediction formula is changed corresponding to the division. According to this method, it is possible to make a more precise determination in the upper limit region of the signal level with a small number of steps.

The control circuit 5 is a circuit section for controlling the timing of the entire processing. The sampling time interval T is determined by the prediction accuracy, the frequency of the input signal, and the like.

The output of the predictive calculation circuit 4 is output to the gain switching circuit 6 as a gain switching signal at an appropriate timing, and the gain of the gain switching circuit 6 is set to an appropriate value.
Based on this gain setting, the gain of the input signal with respect to the non-input signal level is analyzed, an appropriate response is automatically applied to the input signal of the excessive input exceeding the dynamic range, and the output signal S0 is secured as a normal signal. It becomes possible.

FIG. 2 is a circuit showing a second embodiment of the present invention. The predictive gain automatic switching circuit of this embodiment is composed of two parts, an input signal level predicting circuit 20 and a gain switching circuit 6. The input signal level prediction circuit 20 includes an attenuation amplifier 1, a differentiation circuit 11, a level determination circuit 12, a prediction calculation circuit 14 and a control circuit 5.

The feature of the second embodiment is that, as compared with the first embodiment, a differentiating circuit 11 is newly inserted between the attenuation amplifier 1 and the level judging device 12, and the recording memory 3 is deleted. It was done. In the above circuit configuration, the attenuation amplifier 1, the control circuit 5 and the gain switching circuit 6 are basically the same as the circuit parts having the same names in the first embodiment.
A description of these circuit units will be omitted.

The differentiating circuit 11 is a circuit section for differentiating the attenuation signal (Si / m) output from the attenuation amplifier 1 and outputting the analog signal after the differentiation processing. This output signal is an amount proportional to the time variation amount (ΔSi / m) of the attenuation signal (Si / m) and is represented by the following equation (3). ΔSi / m = d (Si / m) / dt (3)

The circuit configuration of this differentiating circuit can be obtained, for example, simply by a configuration circuit of a so-called high-pass filter, which is a configuration of a capacitor C and a choke L.

The level determination circuit 12 determines the time variation amount (ΔS
i / m) is divided into N levels and converted into N values or N digital signals gj (gj; g1 to gN). The level determination circuit 12 is different from the level determination circuit 2 of the first embodiment in processing signals, but may have the same circuit configuration. The output signal of the level determination circuit 12 classifies the magnitude of the time variation amount of the input signal Si and outputs it as a variation level signal 121.

The predictive calculation circuit 14 uses the attenuation signal (Si /
m) and the fluctuation level signal 121 based on the input signal, it is a circuit unit that performs a prediction calculation of the next input signal level.
The content of the prediction calculation is to predict the level of the next signal from the classified level of the fluctuation level signal and the magnitude of the attenuated signal. An example of the theoretical formula of this prediction is shown in the following formula (4).
In the following equation, the relationship between the input signal Si (t0) at the current time point and the predicted input signal Si (t + 1) after the predetermined time T has been expressed. Si (t + 1) = Si (t0) {1 + Gj} (4) where Gj is a coefficient value corresponding to the level of the digital signal gj.

In this embodiment, as can be seen from the comparison between the equations (4) and (2), the prediction calculation is simplified. The reason is that the differentiating circuit 11 performs a part of the differentiating process of the calculating process in the predictive calculating circuit 4 of the first embodiment. The second embodiment is advantageous in simplifying the circuit configuration and high-speed processing.

Although the above-described embodiment is an example of a preferred embodiment of the present invention, the present invention is not limited to this and various modifications can be made without departing from the gist of the present invention. For example, in the above embodiment, the gain adjustment is made for an excessive input signal exceeding the dynamic range, but the amplification degree of the amplifier may be adjusted for an excessively small input. Further, it is also possible to configure it as a predictive gain automatic switching circuit corresponding to an excessively large or too small input signal.

[0027]

As is apparent from the above description, the predictive gain automatic switching circuit of the present invention predicts the level of an input signal after a predetermined time elapses in advance, in accordance with the magnitude of the predicted level. To switch the gain of the amplifier. Therefore, it is possible to switch the gain of the amplifier in real time with respect to an excessively large input signal and / or an inappropriately small signal. By this processing, it is possible to prevent the generation of distortion in the input signal and the generation of an inappropriately small signal in measurement or the like.

[Brief description of drawings]

FIG. 1 is a circuit configuration block diagram showing a first embodiment of a predictive gain automatic switching circuit of the present invention.

FIG. 2 is a circuit configuration block diagram showing a second embodiment of the predictive gain automatic switching circuit of the present invention.

FIG. 3 is a block diagram showing a circuit configuration example of a conventional automatic gain switching circuit.

[Explanation of symbols]

 1 Attenuation amplifier 2 Level determination circuit 3 Recording memory 4 Prediction calculation circuit 5 Control circuit 6 Gain switching circuit 10 Input signal level prediction circuit

Claims (5)

[Claims] 1. A predicting means for predicting a level of an input signal after a predetermined time has elapsed in advance, and a gain of an amplifier for amplifying or attenuating the input signal based on the value of the level predicted by the predicting means. A predictive gain automatic switching circuit, characterized in that it automatically switches the gain. 2. The predicting means includes first level determining means for determining the level of the input signal, storage means for temporarily storing a determination result of the first level determining means, and storage for the storage means. The predictive gain automatic switching circuit according to claim 1, further comprising: first predictive calculation means for calculating a level magnitude after the lapse of the predetermined time by using the determination result. 3. The predicting means includes a differentiating means for extracting the time change amount of the level of the input signal, and a second level determining means for judging the magnitude of the time change amount extracted by the differentiating means. The predictive gain automatic switching according to claim 1, further comprising: second predictive calculation means for calculating the magnitude of the level after the lapse of the predetermined time by using the judgment result of the second level judgment means. circuit. 4. The predictive gain automatic switching circuit according to claim 2, wherein the first level determining means is an analog comparator. 5. The predictive gain automatic switching circuit according to claim 3, wherein the second level determining means is an analog comparator.