JPH07192405A - Maximum liklihood decoder for digital signal - Google Patents

Abstract

PURPOSE:To perform maximum liklihood decoding with a low frequency when a digital signal having (d) limit in the NRZL rule is decoded by (d) frequency- dividing a bit clock. CONSTITUTION:A signal regenerated from a magnetic tape T by a ring head 1 is equalized by a waveform equalizer 3, and the bit clock is generated from the equalized signal by a PLL circuit 4. The bit clock is (d) frequency-divided by a (d) frequency divider 5, and (d) pieces of sample clocks successively delayed only by one bit clock are generated. After the signal regenerated by a reproducing amplifier 2 is equalized again by a waveform equalizer and ALU 6, (d) pieces of equalization signals successively delayed by the period of the bit clock are generated to be added, and are sampled respectively at every sample clock by A/D converters 71-7d to be A/D converted, and respective A/D conversion values are maximum liklihood-decoded by ML decoders 81-8d based on respective sample clocks, respectively. A synthesis process circuit 9 synthesizes a decode system from (d) pieces of the decoded data.

Description

Detailed Description of the Invention

[0001]

The present invention relates to NRZL (Non Return)
The present invention relates to a digital signal maximum likelihood decoding device that decodes a digital signal having a d constraint in the Zero to Zero Level rule, and to a maximum likelihood decoding device suitable for a playback device such as a digital VTR or an optical disc.

[0002]

2. Description of the Related Art Generally, a binary digital signal usually has a possibility of changing its value every clock. However, once the value changes, at least d (> 1) clocks are required until the next change occurs. Signals that maintain the same level are said to have d constraints. By selecting the value of d using such a constraint, information can be transmitted at a lower frequency than the signal before modulation.

As a modulation method having a constraint of d = 2,
New 8-14 modulation ("New 8-14 modulation system and its application to small digital VTRs", The Institute of Television Engineers of Japan Vo
l. 14. No. 20, VIR 90-15, Mar., 1990, and "Development of Digitally Recorded VTR System", Research Institute of Television Society Material VIR 92-70), 2-7 RLL code modulation, 8-12
Modulation ("Digital VTR using 8-12 conversion recording code
Basic Study of ", The Institute of Television Engineers of Japan Material VIR 90-6
9) etc. are known. In such a method, decoding is generally performed by converting an isolated reproduction waveform into a Nyquist waveform and then performing an integral detection method or an amplitude detection method.

Further, the partial response class 4 (P
As a method of decoding by the R4) system, a code is precoded and recorded on a medium so that a signal sampled every other bit at the time of reproduction satisfies the NRZL rule, and a data series to be recorded and a data series to be reproduced. The characteristic of the waveform equalizer is determined so that the PR characteristic is established between the two, and the output of the equalizer is subjected to maximum likelihood (ML: Maximum Like) by the Viterbi decoder.
lihood) Decoding method is known. Due to its peculiar property, it is possible to divide the bit clock by two and divide it into two systems for sample and maximum likelihood decoding.

[0005]

By the way, in general, d
When the restriction is applied, the frequency of the recording signal becomes low, but the frequency of the bit clock for extracting the data becomes high. For example, the bit clock of a D3 format digital VTR using the new 8-14 modulation system is about 110 MHz.
Is 1.75 times the clock before modulation (= 14
/ 8).

On the other hand, recently, Viterbi decoding is known as maximum likelihood decoding for decoding the most probable sequence from past data without instantaneously determining the data, and for example, Viterbi decoding is also possible for a reproduced signal of the NRZL rule. However, in this case, if the frequency of the bit clock becomes high, it becomes difficult to realize the Viterbi decoder, which has many addition and comparison operations, by hardware. When the reproduced signal of the NRZL rule is decoded by the integral detection method or the amplitude detection method, there is a problem that the integration detection method increases noise in the low frequency range, and the amplitude detection method is vulnerable to fluctuations in the signal level.

In addition, the method of precoding a recording signal in the PR4 system is not preferable because the propagation of an error due to precoding (in the case of PR4, if one bit is wrong, the succeeding bit will always be an error).

In view of the above-mentioned conventional problems, the present invention provides a maximum likelihood decoding apparatus for a digital signal capable of decoding a digital signal having a d constraint in the NRZL rule by using a Viterbi decoder whose hardware can be easily realized. The purpose is to provide.

[0009]

In order to achieve the above object, the present invention divides a bit clock by d to generate d sample clocks having different phases, and d maximum likelihood decoding means outputs the bit clocks. The maximum likelihood decoding of the digital signal is performed with a sample clock having a period of d times the clock. That is, according to the present invention, the bit clock generating means for generating the bit clock of the digital signal having the d constraint in the NRZL rule and the bit clock generated by the bit clock generating means are frequency-divided by d to have different phases. Sample clock generating means for generating a plurality of sample clocks, d maximum likelihood decoding means for sampling a digital signal with each sample clock generated by the sample clock generating means and performing maximum likelihood decoding, and the maximum likelihood decoding means. A maximum likelihood decoding apparatus for a digital signal is provided, which has a synthesizing means for synthesizing a desired decoded sequence from the data decoded by.

[0010]

In the present invention, d sample clocks obtained by dividing the bit clock by d are generated, the digital signal is sampled by each sample clock and maximum likelihood decoding is performed. Calculation of addition and comparison is performed with a sample clock having a double cycle. Therefore, a Viterbi decoder can be used to decode a digital signal having a d constraint in the NRZL rule. Here, since the Viterbi decoding divides the clock by d, it is possible even if the operation speed of the IC is slow, and it can be said that the Viterbi decoder can easily realize hardware.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a first embodiment of a maximum likelihood decoding apparatus for digital signals according to the present invention, FIG. 2 is a timing chart showing main signals in the maximum likelihood decoding apparatus of FIG. 1, and FIG. 3 is a case where d = 3. Is a timing chart showing the bit clock and the sample clock of FIG. 4, and FIG. 4 is a block diagram showing the (1 + D) × (d−1) times arithmetic unit in the case of d = 3.

FIG. 1 shows, as an example, a case where data is recorded and reproduced on the magnetic tape T, and FIG.
Data having a d constraint as shown in (a) is recorded. This recorded data is converted into an electric signal by the ring head 1 and then by the reproduction amplifier 2, as shown in FIG.
At the trailing edge, it is reproduced as a negative level differential signal.

Next, this reproduced signal is equalized by the waveform equalizer 3, and the PLL circuit 4 uses this equalized signal as shown in FIG.
A bit clock having a frequency as shown in is generated. This bit clock is divided by d by the d divider 5 to generate d clocks which are sequentially delayed by one bit clock. The respective clocks are applied as sample clocks to the d A / D converters 71 to 7d and the maximum likelihood (ML) decoders 81 to 8d, respectively.

The signal reproduced by the reproducing amplifier 2 is also equalized by the waveform equalizer and the arithmetic unit 6, and then d equalized signals which are sequentially delayed by the period of the bit clock (= 1 + D) are generated. , The d equalized signals are added (d-
Once), a signal as shown in FIG. 2D is obtained.
This signal is output by the A / D converters 71 to 7d as shown in FIG.
As shown in (e) to (g), each sample clock is sampled, that is, sampled at a period of d times the bit clock and A / D converted. Then, each A / D conversion value is based on each sample clock. That is, the maximum likelihood decoding is performed by the ML decoders 81 to 8d at a period of d times the bit clock, and d pieces of decoded data as shown in FIGS. 2 (h) to 2 (j) are obtained. Next, the synthesizing processing circuit 9 detects the data which rises fastest and the data which falls slowest out of the d pieces of decoded data, and outputs a set pulse from each of them.
A reset pulse is generated and combined into a decoded sequence as shown in FIG.

FIG. 3 shows a bit clock and a sample clock when d = 3. The three sample clocks have a frequency of 1/3 of the bit clock and each cycle is sequentially delayed by one bit clock. . Also, in FIG. 4, d =
3 shows the waveform equalization in the case of 3 and the configuration of the computing unit of the computing unit 6. 1 + D means that the analog signals are shifted by the period τ of the bit clock and added, and when d = 3, this addition is performed only d-1 = 2 times.

FIG. 5 shows a second embodiment, and FIG. 5 (a) shows that the waveform equalizer 3 shown in FIG. 1 also serves as an equalization circuit portion of the waveform equalizer 6, and the arithmetic unit 6a performs waveform equalization. (1 + D) × (d−1) operations are performed from the signal equalized by the device 3. Also,
As an example, FIG. 5B shows a partial response (1,
1, 0, -1, -1), and 3D delay circuits 11 to 13 are configured to delay an input signal by a time that is three times as long as a bit clock.

The 3D delay circuit 11 delays the output signal A of the computing unit 6a, and the delayed signal and the output signal A of the computing unit 6a are added by the adding circuit 14. 3D delay circuit 1
2 delays the output signal of the adder circuit 14, and the 3D delay circuit 1
3 delays the output signal of the 3D delay circuit 12. The adder circuit 15 outputs the output signal of the adder circuit 14 and the 3D delay circuit 12,
A signal B obtained by adding the respective output signals of 13 is output to d A / D converters 71 to 7d as shown in FIG.

Then, similarly to the first embodiment, the A / D converters 71 to 7d sample and sample A / D conversion at every sample clock as shown in FIGS. 2 (e) to 2 (g), respectively. The A / D converted values are subjected to maximum likelihood decoding by the ML decoders 81 to 8d based on the respective sample clocks to obtain d pieces of decoded data as shown in FIGS. The circuit 9 synthesizes the decoded sequence as shown in FIG.

Therefore, according to the above embodiment, the NRZ
A Viterbi (ML) decoder 81 generates a clock obtained by dividing the bit clock of a digital signal having d constraint in the L rule by d.
Since it is used as a sample clock of ~ 8d, it is possible to realize a Viterbi decoder having many addition and comparison operations by hardware regardless of the value of d (> 1). Also 1+
Since the calculation of D plays the role of a low-pass filter that removes high-frequency components, the discrimination point noise power of each input signal of the A / D converters 71 to 7d is reduced and errors can be reduced.

Furthermore, it is possible to lower the frequency of the digital signal having the d constraint in the NRZL rule and perform maximum likelihood decoding, and also it is possible to perform decoding without error propagation like precoded PR4. . Further, various partial responses can be detected even though the bit clock is divided by d.

In the above embodiment, the case where the ring head 1 having the differential characteristic is used to reproduce from the magnetic tape T has been described. However, in addition to the magnetic tape T, a PSK modulated wave used in communication or the like is received. When converting to a baseband signal of the NRZL law, the present invention can be applied by differentiating this baseband signal.

[0022]

As described above, according to the present invention, d number of sample clocks obtained by dividing the bit clock by d are generated, the digital signal is sampled by each sample clock, and maximum likelihood decoding is performed. The maximum likelihood decoding means performs addition and comparison operations with a sample clock having a period d times the bit clock, and therefore a Viterbi decoder whose hardware is easy to implement is used to convert a digital signal having a d constraint in the NRZL rule. Can be decrypted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a maximum likelihood decoding apparatus for digital signals according to the present invention.

FIG. 2 is a timing chart showing main signals in the maximum likelihood decoding device in FIG.

FIG. 3 is a timing chart showing a bit clock and a sample clock when d = 3.

FIG. 4 is a block diagram showing a (1 + D) × (d−1) times arithmetic unit when d = 3.

FIG. 5 is a block diagram showing a maximum likelihood decoding device according to a second exemplary embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ring head 2 reproduction amplifier 3 waveform equalizer 4 PLL circuit (bit clock generation means) 5 d frequency divider (sample clock generation means) 6 waveform equalization and arithmetic unit 71 to 7d A / D converter 81 to 8d Likelihood (ML) Decoder (Maximum Likelihood Decoding Means) 9 Compositing Processing Circuit (Combining Means) T Magnetic Tape

Claims (1)

[Claims] 1. A bit clock generation means for generating a bit clock of a digital signal having a d constraint in the NRZL rule, and the bit clock generated by the bit clock generation means is divided by d to obtain d pieces of different phases. Sample clock generating means for generating a sample clock, d maximum likelihood decoding means for performing maximum likelihood decoding by sampling a digital signal with each sample clock generated by the sample clock generating means, and decoding by the maximum likelihood decoding means Maximum likelihood decoding apparatus for a digital signal, which has a synthesizing means for synthesizing a desired decoded sequence from the obtained data.