JPH0719228B2 - Buffer memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory device, and more particularly, when an error occurs in read data of a buffer memory that holds a copy of the storage contents of a main storage device in block units. Regarding the processing of.

[Conventional technology]

In the conventional device, as described in JP-A-60-235262, only one block data is invalidated by one error level register.

[Problems to be Solved by the Invention]

The above prior art does not consider the case where a plurality of errors are detected in the read data from the buffer memory data section or the read address information from the directory section, and N (N = 1,2,3 ... There is a problem that N error level registers are required to invalidate () block data.

An object of the present invention is to solve such a conventional problem and to solve a failure of a directory section or a buffer memory data section by using a small number of hardware resources and simultaneously finding a plurality of failure occurrence points in a plurality of blocks (one block). To the maximum number of blocks that can be stored in the buffer memory data section) can be disabled as necessary, and the buffer memory data section and directory section areas can be variably and effectively used. It is to provide a memory device.

[Means for Solving the Problems]

The present invention relates to a buffer memory data section of a plurality of levels in which a copy of the storage content of a main storage device is stored in block units, and a block provided corresponding to the level of the buffer memory data section and stored in the buffer memory data section. It is applied to a buffer memory device in which a block address corresponding to information has a directory part of a plurality of levels registered in block units as address information, and a directory search is performed by indexing the directory part with a column address in a memory address. To be done.

According to the present invention, the buffer memory device includes an error detecting unit for detecting whether or not there is an error in the address information that is the target of the directory search and the presence or absence of a data error in the block information extracted from the buffer memory data section, and an error detecting unit. Of the divided error level registers for storing the error level information, the compulsory signal indicator flag indicating the effectiveness of each of the divided registers, the column address in the memory address for the directory index, and the error level register. It has a control circuit with a built-in comparison circuit.

[Action]

The address of the block to be invalidated is stored in the error level register according to the error result retrieved by the error detecting means.

According to the present invention, when an error is detected at one or more locations in the directory portion and the buffer memory data portion, a partial or whole comparison result of the comparison circuits corresponding to the divided error level registers is instructed by a compulsory degree instruction. By ignoring it with a flag, it is possible to invalidate multiple errors at the same time.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of the present invention.
That is, the buffer memory data unit 50 and the directory unit 40 for storing the block address of the block data stored in the buffer memory data unit 50 and the effective bit thereof.
An error detector 51 for detecting an error in the read data 11 from the buffer memory data section 50, and the directory section 40.
Error detector that detects an error in the data 12 read from the
42, buffer memory control unit 60, error detection control circuit 20
Etc.

The buffer memory data section 50 and the directory section (address array) 40 are each divided into A column × B level (bank). 1 of the buffer memory data section 50
1 transferred from the main memory (not shown) to one area
Block data is stored, and address information (block address) indicating the storage area of the block data in the main storage device and its valid bit are stored in the corresponding area of the directory unit 40. The address information 08 is stored in the address register 30, and the address of the buffer memory data part, that is, the block address, the column address, and the level (bank) address is specified by the address information 10. On the other hand, the directory section 40 is indexed by block address and specified by the address information 09.

The directory unit 40 includes an error detector 42 for detecting an error (parity error, etc.) in the information of the storage area address in the main storage device read from the directory unit 40, and a storage in the main storage device read from the directory unit 40. A comparator 41 is connected to compare the area address with the address information 03 sent from the buffer memory control unit 60 to detect a match. The buffer memory data unit 50 is connected to an error detector 51 that detects an error (parity error or the like) in the data information 11 read from the buffer memory data unit, and a buffer memory control unit 60.

Data information read from the buffer memory data section 50
Reference numeral 11 is connected to the buffer memory control unit 60, and is connected to the buffer memory control unit 60. The error detector 51, the detection signals 52 and 43 of the error detector 42, and the comparator 41 when the coincidence detection is performed.
Using the coincidence detection signal 44, the buffer memory control unit 60 determines its effectiveness, and the CPU (central information processing device:
(Not shown).

The buffer memory control unit 60 to which the error detectors 42 and 51 are connected has a built-in retry processing circuit for a block in which an error has occurred. The address information (block address) 04 of the block in which the error is confirmed by the series of retry processes in the buffer memory control unit 60 is the error detection control circuit.
20 divided error level registers 20-1, 20-2,
..., 20-N (number of bits of N block address).

The same address as the block address information 09 for indexing the directory section 40 is supplied to the error detection control circuit 20, and the comparison circuits 23-1, 23-2, ... Corresponding to each of the divided error level registers. , 23-N are provided corresponding to the bits. The coincidence detection signals output from the comparison circuits 23-1, 23-2, ..., 23-N are OR gates 24-1, 24-
2, ..., 24-N, and the output signals of those OR gates are supplied to the AND gate 25. The output signal 26 of the AND gate 25 is supplied to the buffer memory control unit 60 and used as the data read from the buffer memory data unit 50 or the invalidation signal of the comparison result signal 44 of the comparator 41.

Divided error level registers 20-1, 20-2, ..., 20-
Each N has a compulsory degra instruction flag 21-1, 21-2, ..., 21-N indicating the validity of the corresponding error level register. Each flag is a direct OR gate 24-1, 24-2, ..., 24-
Supplied to N. Further, the error detection control circuit 20 has a flag 22 for the entire divided error level register, and this flag is connected to the AND gate 25.

Next, the features of the present invention will be described with reference to the operation of FIG. 1 which is an embodiment.

Address register 30 for memory access by CPU
When the address is set to, the buffer memory data section
The entries in 50 and the directory section 40 are read at the same time. By searching the directory section 40, it is determined whether or not the read data from the buffer memory data section 50 is the relevant data. That is, the comparison circuit 41 compares the address information 12 indicating the storage area in the main storage device of the block data read from the directory unit 40 with the address information 03 sent from the buffer memory control unit 60, and the match detection signal 44 is obtained. If it is true, the data 11 read from the buffer memory data unit 50 is supplied to the CPU as the relevant data, and if the match signal 44 is false, the transfer of the read data 11 to the CPU is suppressed or the data sent to the CPU is sent. Reports that this is not the data.

Now, when the error detector 51 or the error detector 42 detects an error in the read data of the buffer memory data unit 50 or the read data from the directory unit 40,
The retry processing circuit built in the buffer memory control unit 60 executes the retry. After that, the address information of the block determined to be in error is output from the buffer memory control unit 60 as address information 04 to the error detection control circuit 20.
Error level registers 20-1, 20-2, ..., 20
Stored in -N. Thereafter, when the memory access from the CPU is made to the block indicated by the address stored in the error level register, the comparison circuits 23-1, 23-2, ... A match is detected by N, and the data of the block is invalidated by the match detection signal 26.

The address of the block in which the error is detected is once stored in the error level register, and then read data of a different block from the buffer memory data unit 50,
Alternatively, when an error is detected in the read data of different blocks from the directory section 40, a predetermined retry process is executed. After that, when it is determined that an error has occurred, the buffer memory control unit 60 forcibly applies the corresponding one bit or several bits of the compulsory degra instruction flags 21-1, 21-2, ... Turn on according to degradation information 05. As a result, the comparison circuit 23-1,
The corresponding comparison result of 23-2, ..., 23-N is forcibly turned on (coincidence detection), and the already error-occurring block and the post-detection error-occurring block can be invalidated at the same time. The flag 22 of the entire error level register determines whether or not degradation occurs. When the flag 22 is on, the coincidence detection signal 26 of the error detection control circuit 20 is forcibly turned off and data is not invalidated.

Next, the specific operation of one embodiment of the present invention will be described in detail with reference to FIG.

A specific degradation function of the embodiment described with reference to FIG. 1 will be described by taking as an example the case where four pieces of block information are stored in the directory section 40 and the buffer memory data section 50.

FIG. 2A shows an error detection control circuit when the block address is 2 bits, that is, when the number of blocks that can be stored in the directory section and the buffer memory data section is four. Error level registers 70-1 and 70-2, corresponding forced degra instruction flags 71-1 and 71-2, invalidity indication flag 72 of the entire error level register, comparison circuits 73-1 and 73-2, OR gate 74-1 , 74-2 and AND gate 75. When no error is detected in the directory section and the buffer memory data section, the invalidity instruction flag of the error level register is in the ON state.

(B), (c), and (d) of FIG. 2 are three cases in which an error is detected (X display) in the block address (memory address) of the directory portion or the buffer memory data portion and the corresponding block, respectively. Indicates.

In the case of (b), when an error is detected at the memory address 10, "1" and "0" are registered in the error level registers 70-1 and 70-2 in the error detection control circuit (a), respectively. To be done.
When an access request is issued again to the memory address 10, the comparison circuits 73-1 and 73-2 compare the error level registers 70-1 and 70-2 with the block address information 79, and the match signal 76 is used. , Invalidates the data of the block. At this time, the invalidity instruction flag 72 and the forced degree instruction flags 71-1 and 71-2 of the error level register are in the off state.

Next, the case (c) will be described. (C) is (b)
The transition case from Error level register 70-1,
In the 70-2, "1" and "0" are registered respectively, and when an error is detected at the memory address 00 in this state, the forced degra instruction flag 71-1 is set to "1" (on state). . As a result, the comparison result of the comparison circuit 73-1 is forcibly set to the coincident state (ignoring the comparison result), and the memory address 10 or the memory address 00
On the other hand, when the access request is made again, the comparison match signal 76 is turned on, and the block data is invalidated.

The case of (d) is also a transition case from (b) like (c). When an error is detected at memory address 11 while "1" and "0" are registered in the error level registers 70-1 and 70-2 respectively, the compulsory degra instruction flag 71-2 is set to "1".
(ON state). This makes it possible to invalidate the block data when there is an access request to the memory address 10 or 11 again.

〔The invention's effect〕

As described above in detail, according to the present invention, with respect to the failure of the directory section or the buffer memory data section, a small number of hardware resources are utilized to simultaneously find a plurality of failure occurrence points in a plurality of blocks (from one to the buffer memory data section). (Up to the maximum number of blocks that can be stored in a section) can be disabled as needed, so the areas of the buffer memory data section and the directory section can be variably used,
Effective use becomes possible.

[Brief description of drawings]

1 and 2 are block diagrams showing an embodiment of the present invention. 20-1 to 20-N ... Error level register, 21-1 to 21-
N, 22 ... Forced degra instruction flag, 23-1 to 23-N, 41 ... Comparison circuit, 24-1 to 24-N ... OR circuit, 25 ... AND circuit, 50
… Buffer memory data part, 40… Directory part, 60…
Buffer memory control unit, 42, 51 ... Error detector.

Claims (1)

[Claims] 1. A buffer memory data unit (50) of a plurality of levels in which a copy of the stored contents of a main memory is stored in a unit of a block, and a buffer memory data unit is provided corresponding to the levels of the buffer memory data unit. A block address corresponding to the block information stored in the directory has a multi-level directory section (40) registered as address information in block units, and the directory section is indexed by the column address in the memory address. In a buffer memory device to be searched, an error detecting means (42,51) for detecting the presence or absence of an error in the address information to be searched for in the directory and the presence or absence of a data error in the block information fetched from the buffer memory data section. ) And one column of the directory section (40) A comparator (41) that compares the read block addresses of several levels with the accessed address information and holds the matched level information, and the read data from the buffer memory data section (50) or the directory section. When an error is detected in the read address information from (40), in order to invalidate the output of the address comparison circuit (41), a divided error level register (20 -1 to 20-N) and the above-mentioned divided error level registers (20-1 to 20-N) are forcibly made effective, and the compulsory degra instruction flags (21-1 to 21-).
A buffer memory device comprising: an error detection control circuit (20) incorporating N);