JPH07191932A - Dma transfer device - Google Patents

Abstract

PURPOSE:To efficiently control a bus to increase the processing speed of the whole of a system by determining whether a device should acquire the use right of the bus from another bus master or should wait till release of the bus by the classification of DMA(direct memory access) CONSTITUTION:Each input/output device transmits a DMA request signal for the purpose of acquiring the use right of the data bus from a bus master, and a DMA request holding means 1 receives this signal to hold a DMA flag. A first sampling means 2 samples this flag to hold the DMA request, and a priority giving means 3 selects a request having the highest priority from plural DMA requests held in the first sampling means 2. A preferential selection means 4 discriminates whether the use right of the bus should be acquired even at the time of the use of the bus by another bus master or the bus should be used at the time of release of the bus from another bus master with respect to the selected DMA request, and a DMA cycle is generated from a second sampling means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer device used for data transfer, and more particularly to a D transfer device having improved bus usage efficiency.
It relates to an MA transfer device.

[0002]

2. Description of the Related Art As a data transfer system of a microprocessor used in a personal computer or the like, a direct memory access system (DMA: Direct Memory Access) in which a memory and an input / output device directly transfer data.
(ss) is generally used to increase the processing speed. In the past, when trying to execute a DMA while the bus was being used by another I / O device, there was no choice but to perform an arbitration requesting the bus use right or to wait for the bus to become available. In addition, JP-A-63
No. 55656 discloses a bus usage time and data corresponding to the type of device requesting use of the bus and the type of device to be accessed only when the microprocessor (bus master) gives permission to use the bus. A method for selectively determining access timing is disclosed.

[0003]

However, when it is necessary to perform arbitration for requesting the bus right or to wait for the bus to become free, some commonly used DMAs have a fixed time within a certain time. DMA as many as
There are some types of DMA that need to be executed, or there is a DMA that only needs to be executed a certain number regardless of time. In the former case, the system will fail if it is not completed even if the work of another bus master is taken. There is a risk that it will end up.

On the other hand, in the bus control circuit disclosed in Japanese Patent Laid-Open No. 63-55656, the microprocessor (bus master) has the initiative to use the bus control circuit. Since the master uses the bus with the highest priority, there is a problem in that the bus usage efficiency is low.

[0005]

It is an object of the present invention to provide efficient bus control by providing means for determining whether to take the right to use the bus or to wait until the bus is unused depending on the type of DMA, thereby improving the processing speed of the entire system. It is an object to provide a DMA transfer device that can be improved.

[0006]

To achieve this object, a first invention in a DMA transfer apparatus according to the present invention is
A DMA request holding device, a first sampling device, a prioritizing device, and a second sampling device are provided, and in the case of a DMA having a predetermined high priority among a plurality of DMAs, another bus master uses the bus. Even if the bus is used, the bus usage right is acquired, and in the case of other DMAs, it is possible to use the bus when another bus master is not using the bus.

In the second invention of the present application, the DMA request holding means holds the DMA requests when there are a plurality of DMA requests, and when the respective DMAs are serviced, the DMA requests held corresponding to the DMA requests are held. It is something to clear. Third
According to the invention, the first sampling means stores each DMA request by sampling the plurality of DMA requests held by the DMA request holding means at the first clock. In a fourth aspect of the present invention, the prioritizing means has a plurality of DMs held by the first sampling means.
The feature is that the DMA request with the highest priority is selected from the A requests.

According to a fifth aspect of the present invention, the priority selection means takes away the bus use right from the bus using a bus use signal indicating that another bus master is using the bus or is about to use the bus. It is to decide whether to wait until the right to use is abandoned. A sixth means is to hold the DMA cycle by the second sampling means sampling the DMA request selected by the priority selecting means at the second clock. A seventh means consists in that the first and second clocks are clocks synchronized with the bus cycle and are out of phase with each other. The eighth means is characterized in that it is set for each DMA whether to take the right to use the bus or to wait until the bus is released.

A ninth aspect of the invention is to output a bus use request signal in order to steal the bus use right. A tenth invention comprises a DMA request holding device, a first sampling device, a priority ordering device, and a second sampling device, and in the case of a DMA having a predetermined high priority among a plurality of DMAs, another A bus master acquires the right to use the bus even if it is using the bus, and in the case of other DMAs, it has a priority selection device that allows the bus to be used when another bus master is not using the bus. It is characterized by

[0010]

By constructing the DMA transfer means and device in this way, the bus can be used efficiently because the first and tenth inventions are provided with the priority selection means or the priority selection device, and the DMA request is made in the second invention. Since the holding unit holds the DMA request, the DMA request is held even when the DMA request signal becomes inactive, so that useless signal processing can be eliminated. In the third invention, since the first sampling means samples the DMA flag, the output state to the prioritizing means is not changed even if the DMA flag having a high priority becomes active after sampling. Further, in the fourth invention, the priority ordering means selects the DMA having the highest priority order from the plurality of DMA requests output by the first sampling means, so that the bus can be used efficiently.

According to the fifth aspect of the invention, the priority selection means acquires the right to use the bus even if another bus master is using the bus in the case of the high priority DMA, and the other DMs.
In the case of A, the bus is used efficiently when another bus master is not using the bus, so that the bus can be used efficiently and the possibility that the system will fail can be eliminated. In the sixth invention, since the second sampling means samples and holds the selected DMA request,
It becomes possible to continuously maintain the cycle, and in the seventh aspect, the phases of the first clock and the second clock are shifted, so that separate sampling can be performed.
In the eighth invention, the priority selection of the DMA can be dynamically changed, so that the DMA control can be facilitated. Further, the ninth means can output the bus use request signal. It is possible to forcibly remove the usage right.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A DMA transfer device according to the present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a system block diagram of a control unit of a DMA transfer apparatus according to the present invention, in which 1 is a DMA request holding unit, 2 is a first sampling unit, 3 is a prioritizing unit, 4 is a priority selecting unit,
Reference numeral 5 denotes a second sampling means, a DMA request signal is input to the DMA request holding means 1, and first and second clock signals are input to the first and second sampling means 2 and 4, respectively. A bus use signal is input to the priority selection means 5.

The operation of the DMA transfer device thus configured will be described with reference to the timing chart shown in FIG. Each input / output device transmits a DMA request signal to the DMA request holding means 1 in order to acquire the right to use the data bus from the bus master, and the DMA request holding means 1 receiving the DMA request signal holds the DMA flag. The first sampling means 2 holds the DM held by the DMA request holding means 1.
The A flag is sampled at the first clock to hold the DMA request, and the prioritizing means 3 at the next stage selects the highest-order DMA from the plurality of DMA requests held by the first sampling means 2.

The priority selecting means 4 is the priority ordering means 3
The DMA selected in step 2 deprives the bus master of the bus usage right from the bus master even when another bus master is using the bus during DMA execution. If the bus master uses the bus, the bus master or the bus usage right is abandoned, and then it is determined which group belongs to the group which does not execute the DMA until the usage right is acquired. The second sampling means 5 secondizes the DMA determined by the priority selection means 4.
The DMA is performed by sampling with the clock of (1) to generate a DMA cycle. The DMA cycle signal generated by the second sampling means 5 is a signal used for actual DMA execution, and at the same time, as a signal for resetting the DMA flag of the D request supply holding means 1 holding the DMA request. It is used.

The first clock and the second clock used in the first and second sampling means are synchronized with the clock that determines the timing of the bus cycle. In the DMA controller configured as described above, various methods are conceivable as a method of acquiring the bus use right from another bus master, such as a method of performing arbitration and performing the arbitration procedure, or a method of suddenly depriving the bus use right. However, any method may be used in the bus control method according to the present invention.

FIG. 2 shows a timing chart when another bus master is using the bus at the time of executing the DMA and the DMA is executed after outputting the bus use request signal, and FIG. 3 is the DMA execution. FIG. 11 is a diagram showing a timing chart in the case where another bus master is using the bus at some time and the bus master currently using the bus waits until the bus is released and executes the DMA. In addition, D
As a form of receiving the MA request signal, a form of holding the DMA request signal as described above or a form of holding the DMA request signal itself can be considered, but especially in the case of a school building, the DMA request holding means is not necessary. Needless to say, the structure of the control unit can be further simplified.

[0017]

Since the present invention is constructed and functions as described above, the bus utilization efficiency can be improved, and a high priority DMA uses the bus prior to a low priority DMA. In the case of the type of DMA in which a certain number of DMAs must be performed within a certain period of time, the bus is forcibly used, and the system has a remarkable effect in preventing the system from breaking down.

[Brief description of drawings]

FIG. 1 is a system block diagram of a control unit of a DMA transfer device according to the present invention.

FIG. 2 is a timing chart showing a case where DMA is executed after outputting a bus use request signal in the DMA transfer device according to the present invention.

FIG. 3 is a diagram showing a timing chart when the DMA transfer device according to the present invention waits until another bus master releases the bus and executes DMA.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... DMA request holding means, 2 ... 1st sampling means, 3 ... Priority ordering means, 4 ... Priority selection means, 5 ... 2nd sampling means

Claims (10)

[Claims] 1. A DMA request holding means, a first sampling means, a priority ordering means, and a second sampling means, and in the case of a DMA having a predetermined high priority among a plurality of DMAs, another DMA is stored. Even if the bus master is using the bus, it acquires the right to use the bus. For other DMA,
A DMA transfer device having a priority selection unit that enables a bus to be used when another bus master is not using the bus. 2. The DMA request holding means comprises a plurality of DMAs.
When a request is made, the DMA request is held and each D
When the MA was serviced, the corresponding D was held
The DMA transfer device according to claim 1, wherein the MA request is cleared. 3. The first sampling means stores each DMA request by sampling a plurality of DMA requests held by the DMA request holding means at a first clock. DMA transfer device. 4. The DMA transfer device according to claim 1, wherein the priority ordering means selects the DMA request having the highest priority from the plurality of DMA requests held by the first sampling means. 5. The priority selection means takes away the bus use right or the bus use right by a bus use signal indicating that another bus master is using the bus or is about to use the bus. 2. The DMA transfer device according to claim 1, wherein it is determined whether to wait until it is abandoned. 6. The DMA transfer device according to claim 1, wherein the second sampling means holds the DMA cycle by sampling the DMA request selected by the priority selecting means at a second clock. 7. The DMA transfer device according to claim 1, wherein the first and second clocks are clocks synchronized with a bus cycle and are out of phase with each other. 8. The DMA transfer device according to claim 5, wherein it is possible to set, for each DMA, whether to take the right to use the bus or to wait until the bus is released. 9. The DMA according to claim 5, wherein a bus use request signal is output to deprive the bus use right.
Transfer device. 10. A DMA request holding device, a first sampling device, a priority ordering device, and a second sampling device, and in the case of a DMA having a predetermined high priority among a plurality of DMAs, another DMA is held. A bus master acquires the right to use the bus even if it is using the bus, and in the case of other DMAs, it has a priority selection device that allows the bus to be used when another bus master is not using the bus. A DMA transfer device characterized by the above.