JPH07191874A - In-circuit emulator - Google Patents

Abstract

PURPOSE:To provide a developing tool for improving the efficiency of program development by exactly debugging a program in a short time by using a host computer and the in-circuit emulator connected to that host computer. CONSTITUTION:The in-circuit emulator is provided with a disassembly processing means 24 for providing a code table and a text table by disassembling an assemble list 22 generated from the program of a target system on the host computer, check processing means 25 for detecting errors based on these tables, analysis execution control means 26 for transmitting the instruction codes of the code table to a main body part 1 of the emulator one by one and receiving the executed result of the emulator, display processing means 27 for performing processing to display the error detected result of the check processing means 25 and the executed result of the analysis execution control means 26 on a monitor 28, and command processing means 29 for processing command instructions to the disassembly processing means, check processing means, analysis execution control means and display processing means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-circuit emulator for debugging a computer program with a host computer and an emulator body.

[0002]

2. Description of the Related Art In recent years, a one-chip microcomputer (one-chip microcomputer) in which a processor, a memory, an input / output control device, etc. are integrated on one chip is a general-purpose CPU.
A number of products with comparable performance have been developed, and the price is low, and they are widely used in industrial and home electric appliances.

The development procedure of the software part of such a microcomputer system is, for example, as follows.
(1) Create a flowchart by dividing it into functional units according to the specifications, (2) Coding from this flowchart, (3) Assemble when all program modules have been coded, and (4) Until there are no assemble errors. Review the program, (5) perform a unit test of the program with an in-circuit emulator, etc., (6) write it in the ROM and check the operation for each function on the stand, and (7) list it if it does not operate according to the specifications I followed (8) and revised the program and repeated from (4).

Development tools such as in-circuit emulators and debuggers have been mainly used for debugging conventional computer programs. The in-circuit emulator connects to the target system instead of the microprocessor to allow arbitrary execution / stop of programs,
It has a read / write function for memory resources, and a trace function for execution. Further, usually, a debugger is a so-called machine code debugger which analyzes a machine language and displays a line of a source list corresponding to the instruction.

[0005]

When debugging a program, it is necessary to confirm the state of the program by repeatedly executing the program, displaying the memory, and displaying the register. However, in the conventional in-circuit emulator, since these scroll screens are displayed, these screens cannot be viewed at the same time. Further, in order to know each information, it is necessary to input each command, and the operation is complicated and inefficient.

Further, since the execution program is displayed by disassembling the execution program, information such as comments on the source program is not displayed. It is necessary to display the source program for efficient debugging. Conventionally, in order to display the source program, a line number is added to the object code at the time of assembly, and the line of the source program corresponding to the line number is displayed when the program is displayed. This is limited to the case where the assembler and in-circuit emulator are one system. If the line number is not added to the object code due to the use of another cross assembler, the source program cannot be displayed.

Further, the execution start address of the program has to be calculated by the program allocation address at the time of linking + the relative address of the program. this is,
It was complicated because it had to be done each time a link was made. In order to solve this problem, a symbolic debug was devised, but it is necessary to create a symbol file at the time of assembling.

In the conventional in-circuit emulator, the operation check of the machine code could be performed, but the operand value does not take any value. The error could not be detected due to the difference in the size, and it seemed to work correctly. Conventionally, such debugging has only been visually checked on a desk. All checks can be done on the desk, but the detection ability was uneven because it was checked by a person.

In other words, the conventional program development tools have to rely on a chip maker to some extent, and there is not much choice, and the development of a microcomputer system is often done by hand, especially ,
The debugging process is a continuous work that requires only hands and eyes, and it has been difficult to shorten the system development cycle.

Therefore, the present invention provides a development tool capable of accurately and quickly debugging a microcomputer program on a host computer and a main body of an in-circuit emulator connected to the host computer and improving the efficiency of system development. The purpose is to

[0011]

In order to achieve the above object, the in-circuit emulator of the present invention is an assembler generated from a source program of a target system.
Decomposition processing means for decomposing the list on the host computer to obtain a code table and a text table, a check processing means for detecting an error based on the code table and the text table, and an instruction of the code table. Interpretation execution control means for transmitting a code to the emulator main body one instruction at a time and receiving a result executed by the emulator main body, and processing for displaying an error detection result of the check processing means and an execution result of the interpretation execution control means on a monitor. And a command processing means for processing a command instruction to the disassembly processing means, the check processing means, the interpretation execution control means, and the display processing means.

The code table of the disassembling processing means has an executed flag for each instruction line which sets the executed state according to the instruction execution result by the interpretation execution control means, and a break point by a command for each instruction line. It has a break flag for setting and canceling.

The check processing means includes an access control table for setting attribute information of the memory of the target system in advance by a command, and an error detection section for performing error detection processing based on the code table, text table, and access control table. , And a flag set when an error is detected. Then, the error detection unit detects whether the instruction fetched from the code table is a pseudo instruction. The error detection unit calculates the jump destination address from the operation code when the instruction fetched from the code table is a jump instruction, and detects the presence or absence of the corresponding address on the table. When the instruction fetched from the code table is an immediate data instruction, the error detection unit obtains the operation code length on the table and determines the data length flag of the CPU status. The error detector obtains the operation code length on the table when the instruction fetched from the code table is the immediate index instruction, and judges the index length flag of the CPU status. The error detection unit reads the type of the instruction code fetched from the code table from the memory,
It is judged whether it is a memory write or other, and it is judged whether or not the memory attributes of the access management table corresponding to the respective access addresses match.

The interpretive execution control means includes an operation code table, an address function routine for obtaining an address of an operand of a machine code, a RAM table for reading and writing by executing an instruction corresponding to a target system, and a machine code of the code table. To compare the match with the machine code in the operation code table, call the corresponding execution routine of the matched machine code, obtain the address by the address function corresponding to the addressing mode in this execution routine, and execute the instruction And an execution processing unit. Then, the execution processing unit provides a nest as a pointer for managing the call instruction, adds 1 to the nest at the time of the call instruction, subtracts 1 from the nest at the time of the return instruction, and executes the next instruction when the call instruction is not executed. To execute. When the no-operation command is keyed in, the execution processing unit advances the current cursor line by one line and then skips the value of the program counter to the next instruction without executing the instruction. The execution processing unit determines whether the break flag of the code table is on or off when the instruction is executed, and if it is on, the break is generated. The execution processing unit turns on the execution completion flag of the code table.
It is determined to be off, and if it is off, 1 is added to the execution line count, the executed flag is turned on, and the debug ratio is calculated based on the value of the execution line count.

The display processing means displays on the monitor the data provided from the symbol table in which the symbols and the addresses of the data generated from the error detecting section, the execution processing section and the symbol file of the assemble list are associated with each other. A display processing unit that performs display processing for Then, the display processing unit turns on the execution flag of the code table set by the instruction execution of the execution processing unit.
It is determined to be off, and the display of that line is displayed in different colors depending on whether it is on or off. The display processing unit obtains an addressing function by searching a table from the operation code of the cursor, calls an addressing function routine to obtain a memory address, and displays the content of the memory from the RAM address. The display processing unit saves the current nest, compares the saved nests when returning after executing the instruction, and skips the display when the saved value is smaller than the nest value. The display screen displayed on the monitor by the display processing unit is the RAM display unit for displaying the symbol name of the RAM table, its address and the contents of the address, and the contents of the text table and the underline for the current display. It has a trace display section for displaying the cursor position and a register display section for displaying the contents of registers on one screen. The display screen displayed on the monitor by the display processing unit has an execution status display unit that displays the ratio of the number of execution steps to the total number of execution steps.

[0016]

In the in-circuit emulator according to the present invention, the decomposition processing means decomposes the assemble list on the host computer to obtain the code table and the text table, and the check processing means the code table and the text table. And the interpretation execution control means translates the instruction code in the code table into an instruction sequence of the host computer and executes the instruction sequence,
The display processing means displays the error detection result of the check processing means and the execution result of the interpretation execution control means on the monitor, and the command processing means processes the command instruction to each means, so that the program of the microcomputer and the host computer It is possible to provide a development tool that enables accurate and short-time debugging on the main body of the connected in-circuit emulator and improves the efficiency of system development.

By setting the executed flag for each instruction line of the code table of the disassembling means to "executed" by the instruction execution by the interpretive execution control means, it is possible to grasp how long the instruction has been executed, and the break A break can be generated at any position by setting / clearing the break flag of the point.

In the access management table of the check processing means, the attribute information of the memory of the target system is set in advance by a command, and the error detection unit, based on the code table, the text table and the access management table, the pseudo instruction execution error and the jump. Error detection such as instruction jump destination error, immediate data length error, immediate / index length error, memory access error, etc.
By setting a flag when this error is detected, powerful error checking can be performed regardless of human eyes.

In the execution processing section of the interpretation execution control means, the machine code in the code table is taken out, the match with the machine code in the operation code table is compared, the corresponding execution routine of the matched machine code is called, and this execution routine is called. At, the address is obtained by the address function corresponding to the addressing mode and the instruction is executed. Also, manage the nesting with the pointer that manages call instructions,
1 at the current cursor line with no operation command
Advances the line and skips the instruction, judges whether the break flag is on or off, and if it is on, generates a break, judges whether the executed flag is on or off, and if it is off, adds 1 to the line count and executes it By turning on the done flag and calculating the debug ratio based on the value of the execution line count, accurate and efficient debugging can be performed.

In the display processing section, the processing of displaying the data given from each section on the monitor, in particular, turning on the execution flag
It judges whether the line is off and displays the line according to whether it is on or off by color-coded display processing, memory content display processing, display skip processing, etc., and the RAM display section on one screen is addressed to the monitor. And its address, the contents of the text table and the underline in the trace display area to display the current cursor position, the contents of the registers in the registers display area, or the total execution step in the execution status display area. By displaying the ratio of the number of execution steps to, it is possible to know the changes in the RAM and registers at the same time as the instruction is executed, and it is possible to check the executed lines and grasp the completeness of debugging.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment shown in the drawings. FIG. 1 is a diagram for explaining the overall system configuration of an in-circuit emulator according to the embodiment of the present invention.

In the figure, the in-circuit of the present invention
The emulator 20 is directly connected to the target system and has an emulator main body 1 having arbitrary execution / stop of a program, reading / writing of memory resources, etc., execution trace function, etc., and controls the emulator main body 1 by sending commands. In addition, the personal computer side system 2 performs display processing based on the execution result transferred from the emulator main body 1. The emulator body 1 includes a target CPU 3, an input / output device (I / O) 4, a memory 5, and an in-circuit emulator (ICE) control CPU.
It consists of 6. The personal computer side system unit 2 constitutes a host computer, and includes an ICE controlling CPU 6 and an RS232C.
A personal computer (personal computer) 7 having a display software connected by an interface, and a target memory 8, a target register 9, a command file 10, a printer (PRN) file 11, hexadecimal (connected to it) HEX) file 12, symbol (SYM) file 13, keyboard 15, CRT 15, printer 1 for printing execution results, etc.
It consists of 6 mag. The target memory 8 and the target register 9 store data transferred to the personal computer side system 2 each time the emulator main body 1 executes the data.
It is read and displayed on the CRT 15.

FIG. 3 is a block diagram for explaining the overall configuration of the in-circuit emulator according to the embodiment of the present invention.

In the figure, the in-circuit of the present invention
The emulator 20 uses a host computer to generate an assemble list (print file) 22 generated by inputting a source program 21 for a target system created by using an editor or the like into an assembler.
This is an interpreter system in which the machine language instructions of the target CPU are interpreted one by one, and an error is judged and then executed by the emulator main body unit 1. The assemble list 22 input via the input / output interface 23 is a text table and a code. .Disassembly processing means 24 for disassembly processing into a table
And a check processing means 25 for performing check processing accompanying various error detections based on the text table and code table decomposed by the disassembly processing means 24, and one instruction is translated into an instruction string of the host computer and executed. Interpretation execution control means 26 for controlling and check processing means 25
Display processing means 27 for displaying the check result and the execution result of the interpretation execution control means 26, a monitor 18 for outputting and displaying the processing result of the display processing means 27 via the input / output interface 23, and each disassembling processing. Command processing means 19 for instructing various processing to the means 24, the check processing means 25, the interpretation execution control means 26, the display processing means 27, etc., and various input / output devices 30 etc. connected to the input / output interface 23. Composed of.

FIG. 2 is a block diagram for explaining a concrete structure of the in-circuit emulator according to the embodiment of the present invention. The corresponding parts in FIG. 2 are designated by the same reference numerals.

In the figure, the host of the personal computer side system section 2 which constitutes the in-circuit emulator 20
As a computer (personal computer), for example, a microcomputer equipped with a 32-bit or 16-bit microprocessor, equipped with a general-purpose operating system (OS), and having a memory capacity with a user usable capacity of 256 Kbytes or more is used. . The operation specifications of the microcomputer used in the target system depend on the specifications of the ICE. For example, the maximum number of symbols in the RAM table is 1024 and the RAM table is 6 in the single chip mode.
4K bytes, maximum debug program file size is 240K bytes, maximum number of debug program lines is 5
For example, 000 lines.

The assemble list 22 is a source file in advance.
A print file (PRN file 11 in FIG. 1) obtained by inputting the program 21 into the assembler,
For example, as shown in FIG. 4, it comprises a line number, a load address portion, an object program portion, an assembly source program portion, and the like. For example, in the figure, the load address part of the line number "66" is "00".
0018 ”, the object program part is“ A9C
7 ", the assembly source program part is" LDA
A, # 199 ". Such an assemble list 22 is the one prepared by modifying the source program 21 and reassembling if there is an error at the time of assembling. It is created by the host computer of this embodiment, or created by another computer. It was done.

The disassembly processing means 24 includes a disassembly processing section 31 and
The assemble list 22 which is composed of the code table 32 and the text table 33 and is input through the input / output interface 13 is coded by the disassembly processing unit 31.
It has a function of decomposing into a table 32 and a text table 33. As shown in FIG. 5, the code table 32 includes, for example, a load address portion and an object program portion of the assemble list 22, a break flag area secured for each instruction line, which will be described in detail later, and an execution completion portion. And a flag area. This break flag area is an area for setting / releasing a breakpoint of an instruction by a command, and the executed flag area is an area for setting an executed flag when an instruction is executed. The text table 33 is an assembly source program part.

The check processing means 25 includes an error detection unit 34 for performing various error detection processes, and an access management table 35 in which attribute information of the memory is set in advance by a command.
And a flag 36 and the like set when the error detection unit 34 detects an error.
It has a function of performing various kinds of error detection processing based on the table 32, the text table 33, and the access management table 35 as necessary, and setting a flag 36 when an error is detected. The access management table 35 is, for example, as shown in FIG. 6, in which the attribute information of the memory of the target system is preset in units of 256 bytes, and the readable area displayed by “R” is displayed by “W”. A writable area, a readable / writable area displayed by “RW”, and the like are set. Such attribute information of the memory is set by a command regarding memory protect described later. For the error detection by the error detection unit 34, check items are determined for each instruction. Table 1 shows a part of the check summary for each instruction. For each instruction, one or more of the nine check items shown by symbols A to I (double circles in the figure are attached. ing)
Check. The commands in Table 1 are a part of the transfer commands, and items such as A, D, and I are checked for each command. As shown in Table 2, the check items have a certain check content corresponding to the check items such as symbols A to E. For example, in the examples of Table 1 and Table 2, the transfer instruction “LDA A, dd” is subjected to the memory access check (read check) of the error check item D, and the access check of the memory read address is performed before the instruction execution. Be seen.

[0030]

[Table 1]

[Table 2]

The interpretation execution control means 26 includes an execution processing section 37.
And an opcode table 38, an address function routine 39, a RAM table 41 and the like. The operation code table 38 is a table that associates the object programs (codes) of the code table 32 with each other. For example, as shown in FIG. 7, all 1-byte or 2-byte machine codes provided in the target CPU. About the number of machine cycles (number of clocks) required for one instruction, the type of memory access such as read, write, etc., the instruction code type classified by the length of the operand, the addressing mode for the address function, etc. The logical configuration is shown. Address function routine 39
Is a routine part for obtaining the address of the machine code operand. The relationship between the address function and the execution routine is shown in FIG. 8, for example. Assembler instructions are divided into mnemonics and operands. The machine code is determined by the combination of the two. That is, for example, in the case of "LDA # 64H", the machine code is
It becomes "32, 64". On the contrary, the mnemonic and the type of operand can be known from the machine code. Prepare a function for each mnemonic and operand type. From the machine code, the address function can be known by looking at the upper side of FIG. 8, and the execution routine can be known by looking at the left side. FIG. 7 shows the machine codes arranged in the order shown in FIG. The RAM table 41 corresponds to a RAM installed in the target system, is a storage area portion that secures a memory area of a required size, and a predetermined value is written or read by execution.
The execution processing unit 37 is a unit having a function of performing various processes associated with execution. That is, the execution processing unit 37 fetches the machine code of the code table 32 at the start of execution, compares the machine code with the machine code of the operation code table 38, and after the instruction is executed, the RS232C causes the memory at a necessary location to emulate the emulator. It is transferred from the main body 1 and written in the RAM table 41.

The display processing means 27 includes an error detecting section 34,
The execution processing section 37, the display processing section 43 for displaying the data given from the symbol table 42, and the like.
The symbol table 42 is a symbol (name) of data.
Symbol file attached to the assemble list 22 (SY in FIG. 1).
Input / output interface 2 from M / file 13) 44
3 and is generated by the generation unit 45. Note that this symbol table 42 may be externally generated in advance.

The command processing section 29 inputs a predetermined command from the input / output device 30 such as a keyboard through the input / output interface 23, and thereby the disassembly processing means 24,
It has a function of processing various commands for the check processing means 25, the interpretation execution control means 26, the display processing means 27, etc., and for example, executes, skips, stops, or breaks instructions.
Setting / releasing points, changing the contents of various registers, RA
The attributes of the M table 41 are displayed and set, various initialization processes, and various display-related instructions are performed. Table 3 is an example of a command list prepared for the in-circuit emulator of the present embodiment. The command in the left column is provided with the function in the right column. For example, the command "B" sets a breakpoint. Set / reset, the command “C” sets the cursor on the program counter (PC) line, the command “M” sets the contents of the RAM table 41, the command “O” sets and displays the protect attribute of the memory, The command "RA" changes the contents of accumulator A. When a command is entered, the message for this command is displayed in the message line, the cursor is displayed, and the next input command waits for parameter input. There are direct commands that are executed immediately after a message is displayed. "*" In the list in Table 3
Indicates that it is a direct command. Also,
[] Indicates that it can be omitted. If omitted, the default value is used.

[0034]

[Table 3]

Further, in FIG. 2, a PC (program counter) 46 is a register for holding an address where an instruction exists, and can be set by a command.
The pointer 47 is composed of two registers for execution and display, and can be set by a command. further,
The trace file 48 is a part for recording the history of execution results and can be output at the end of the program.
The content of the trace file 48 is, for example, "RAM
Value ”,“ error count ”,“ number of executed lines ”,“ debug ratio ”,“ file name ”,“ date time ”and the like.

The input / output device 30 comprises a keyboard 49, a floppy disk device 50, a hard disk device 51, a printer 52 and the like.

FIG. 9 shows a sample display screen by the display processing unit according to the embodiment of the present invention.

In the figure, the display screen 60 is the monitor 2
8 is an example of a standard screen displayed in FIG. 8, and the title display section 60a at the top and the RAM display section 60b at the bottom thereof are
It is composed of a trace display section 60c in the substantially central portion, an execution status display section 60d and a register display section 60e on the right side thereof, and a command instruction section 60f at the bottom. The title display section 60a includes a title "in-circuit emulator",
A warning display "JSR skip trace" to skip without displaying the jump destination due to a jump instruction, and the date of execution "19
93/5/10 ”etc. are displayed. RAM display unit 60b
Displays the symbol name of the RAM table 41, its address, and the contents of the address in hexadecimal display, decimal display, and binary display. For example, the address of the symbol name "RAM001" is "(0001 ) ”, The hexadecimal display of the contents of the address is“ 34 ”, the decimal display is“ 52 ”, and the binary display is“ 00110100B ”. The "*" before the symbol name indicates the memory address pointed to by the operand of the instruction at the current cursor position. The trace display portion 60c displays the contents of the assembly source program, and the underlined portion shows the current cursor position. The execution status display unit 60d displays, in a vertically long display area, the ratio of the number of executed steps to the total number of steps in a bar graph.
The length of the bar towards the 0% position indicates the percentage. The register display unit 60e displays the contents of each register, the address of the cursor position and its data, the total number of steps,
The number of execution steps and its ratio, the number of accumulated machine cycles of execution steps, and the like are displayed. For example, A
The value of the register (accumulator) is “FFFFH”, the bit corresponding to “NVmxDIZC” of the flag register is “00001010B”, the address of the cursor line is “(0005)”, the content is “0045H”, and the total step is “STEP”. "123" line, executed line "EXE
The number of “C” is “12”, the ratio thereof is “23%”, and the cumulative machine cycle is “12345”. Command instruction section 6
0f is the “COMM which displays the part to input the command.
AND> ”and the command execution result“ ME
SSAGE> ”. In addition, a number indicating nesting is displayed for “NEST”.

Next, a specific processing example centering on the execution processing of the in-circuit emulator having the above-mentioned configuration will be described with reference to the flowcharts of FIGS.

FIG. 10 is a flow chart for explaining the main processing at the time of execution of the embodiment of the present invention.

In the figure, first, the assemble list 22 in which the assemble error is corrected is the in-circuit
It is read into the host computer that constitutes the emulator 20 through the input / output interface 23 (ST
1). Next, in the disassembling processing section 31, the read assemble list 22 is divided into a text portion and a code portion and tabulated, and a text table 33 and a code table 32 are generated (ST2). Next, the execution processing unit 37 reads the execution program (ST3), and then the execution program is transmitted to the emulator body 1 via the input / output interface 23 (ST4). Next, the execution address is obtained from the execution line (ST5), and this execution address is set in the emulator body 1
(ST6). And the emulator body 1
It is judged whether the execution is completed (ST7), and when the execution is completed, the process returns to the step (ST5) of obtaining the execution address again.

Since the instructions can be executed step by step by inputting the assemble list 22, it becomes possible to execute even if there is no execution format file as in the past, and even if all the program modules are not completed, the development can be performed. Debugging in program module units is possible from the initial stage of.

FIG. 11 is a flow chart for explaining the nest processing of call instructions according to the embodiment of the present invention.

In the figure, first, in the execution processing unit 37, the nest is set to "0" as a pointer for managing the call instruction (ST11), and then it is judged whether or not the instruction is a call instruction (ST12). When the instruction is a call instruction, 1 is added to the nest (ST13). When the instruction is not a call instruction, it is judged whether or not it is a return instruction (ST14). When the instruction is a return instruction, 1 is subtracted from the nest (ST15). When it is not a return command, nest display is performed (ST16). Then, the next command is executed (ST17), and the step of determining the call command again (S
Return to T11).

When the call instruction is continued, the nest becomes deeper, but it can be confirmed whether the nest is deeper than the program design. Conventionally, the calculation was performed using a stack pointer or the like, but the processing was complicated.

FIG. 12 is a flow chart for explaining the NOP processing for skipping the instruction execution of the embodiment of the present invention.

In the figure, first, the NOP (no operation) command "N" is keyed in (ST2
1), then advance the current cursor line by one line (ST22),
The value of the PC (program counter) 46 is advanced to the next instruction (ST23), and if it is a blank line, the step (ST) is performed again.
23) (ST24), and if it is not a blank line, shifts to the next processing (ST24).

When it is desired to skip the execution of an instruction, the instruction is skipped by advancing the cursor by one line by inputting a command, so the operation of the skip processing is simplified. When it is desired to skip a predetermined instruction with a conventional debugger, the operation of changing the PC has to be performed, and the operation is complicated.

FIG. 13 is a flow chart for explaining the break processing of the embodiment of the present invention.

In the figure, first, the break command "B" is keyed in (ST31), and then a break point is set at the current cursor position to set / clear (turn on / off) the break flag. (ST32).
That is, the code table 3 is generated by the break command.
Set a break point for each line in the break flag area of 2. Next, the execution processing unit 37 determines whether the break flag of the code table 32 is on or off when the instruction is executed (ST33), and if it is on, a break occurs (ST).
34) If it is off, the process returns to the break flag determination step when the next instruction is executed.

In the code table 32, a break flag area is provided for each line, and a break point is set / released by a break command, so that there is no limit to the number of breaks and the setting is easy. In the conventional debugger, set the address of the instruction you want to generate a break,
Since the break was generated when the address and the program counter reached the same value, the setting was complicated,
In addition, a table for managing break addresses is required, and the number of settings is limited.

FIG. 14 is a flow chart for explaining the debug rate grasping process of the embodiment of the present invention.

In the figure, first, the execution processing section 37 counts the total number of executed rows in the table (ST41),
Next, after each instruction is executed (ST42), it is judged whether the execution flag of the code table 32 is on or off (ST4).
3) If it is off, add 1 to the execution count (ST4
4) After turning on the executed flag (ST45),
The execution current is displayed by the processing of the display processing unit 43 (ST
46) If it is off, the execution current is displayed without changing the execution count and the executed flag, and the process returns to the step of branch execution of the next instruction. As the execution current display, the register display unit 60e in the monitor 28 display screen displays the execution line count value, the debug rate calculated by dividing the execution line count value by the total execution line number, and the like. The debug rate is displayed as a bar graph on the execution status display unit 60d.

By setting the executed flag for each line, counting the executed lines after execution, and turning on the executed flag, it is possible to grasp the debug ratio indicating how many of the executed lines are currently executed. Yes, debug rate is 10
If it becomes 0%, it means that all steps have been passed, efficient debugging can be achieved, and omission of test can be eliminated. With conventional development tools, it was not possible to know the debug rate during execution.

FIG. 15 is a flow chart for explaining the PC setting process of the embodiment of the present invention.

In the figure, first, the cursor is moved to the line to be executed (ST51), and then the command "P" is keyed in (ST52), and the address of the current cursor line is set in the PC46. (ST53),
Then, the instruction at that address is executed (ST54).

The cursor is moved to the line to be executed, and the address of the cursor position is set to PC46 by the command.
By setting it to and executing it, the user can execute it from the necessary place without being aware of the program address. In the conventional development tool, it is necessary to set an address in the program counter or an address or a symbol by an execution command, which makes the operation complicated.

Next, a specific processing example centered on the error detection processing of the in-circuit emulator having the above-mentioned configuration will be described with reference to the flowcharts of FIGS.

FIG. 16 is a flow chart for explaining the pseudo instruction execution error detection processing of the embodiment of the present invention.

In the figure, first, the error detection unit 34 extracts an instruction code from the table (code and text) (ST61), and then determines whether this instruction code is a pseudo instruction (ST62). If it is a pseudo instruction, the display processing unit 33 performs error display processing (ST6
3) If it is not a pseudo instruction, no error is displayed and the process proceeds to the next step.

When there is a pseudo instruction in the instruction code,
Can detect errors. Conventionally, in an in-circuit emulator or the like, for example, a DB pseudo-instruction that defines data in 1-byte units, and D that specifies data in 2-byte units
Even if there is a W pseudo-instruction or the like, it is executed as it is as an instruction code.

FIG. 17 is a flow chart for explaining the jump instruction jump destination error detection processing of the embodiment of the present invention.

In the figure, first, the error detecting section 34 judges whether the instruction code fetched from the code table 32 is a jump instruction (ST71). Is calculated (ST72), then the presence or absence of the corresponding address on the table is determined (ST73), and only when there is no address, the display processing unit 43 performs an error display process (ST74) and proceeds to the next process to jump command. If not, the process directly proceeds to the next process.

When a jump instruction does not use a symbol or uses an index, the jump destination may change other than the instruction, and an error can be detected at that time. Conventional development tools have been unable to detect such errors.

FIG. 18 is a flow chart for explaining the immediate data length error detection processing of the embodiment of the present invention.

In the figure, first, the error detector 34 judges whether the instruction code fetched from the code table is an immediate data instruction (ST8).
1). If it is an immediate data instruction, the operation code length on the table is obtained (ST82), then the CPU
It is determined whether the data length flag of the status is 1-byte data or 1-byte data (ST83). When it is 1 byte data, it is judged whether the opcode length on the table is 1 byte (ST84), and when it is not 1 byte, the display processing unit 43 performs error display processing (ST85) and proceeds to the next processing. Also, for 2-byte data,
It is determined whether the opcode length on the table is 2 bytes (ST86), and when it is not 2 bytes, the display processing unit 4
In step 3, an error display process (ST85) is performed and the process proceeds to the next process. When not an immediate data command,
The process proceeds as it is.

The immediate data length changes to 1 byte length or 2 bytes length depending on the CPU status. When assembling, specify with a pseudo instruction as a temporary value. When the CPU actually operates, if the CPU statuses do not match, it becomes a bug. In the conventional debugging, it was detected visually.

FIG. 19 is a diagram showing the immediate of the embodiment of the present invention.
It is a flow chart explaining index length error detection processing.

In the figure, first, the error detector 34 determines whether the instruction code fetched from the code table 32 is an immediate index instruction (ST91). If it is an immediate index instruction, the operation code length on the table is obtained (ST9
2) Next, it is determined whether the index length flag of the CPU status is 1-byte data or 1-byte data (ST9).
3). When the data is 1-byte data, it is determined whether the opcode length on the table is 1 byte (ST94), and when it is not 1 byte, the display processing unit 43 performs error display processing (ST95) and proceeds to the next processing. If the data is 2 bytes, the opcode length on the table is 2
If it is not 2 bytes, it is judged whether it is a byte (ST96).
T95) is performed and the process proceeds to the next step. If it is not the immediate index instruction, the process directly proceeds to the next processing.

The immediate index length is CP
Depending on the state of the U status, the length changes to 1 byte length or 2 bytes length. When assembling, specify with a pseudo instruction as a temporary value. When the CPU actually operates, if the CPU statuses do not match, it becomes a bug. In the conventional debugging, it was detected visually.

FIG. 20 is a flow chart for explaining the memory access error detection processing according to the embodiment of the present invention.

In the figure, first, the error detection unit 34 determines whether the type of the instruction code fetched from the code table is memory read, memory write, or the like (ST101). Such a determination is made, for example, in the access type column of the memory of the opcode table 38. When the instruction code is memory read, it is judged from the access management table 35 whether or not the attribute of the memory corresponding to the access address is readable (R) (ST102), and only when it is not readable, the display processing unit 43. In step S103, an error display process is performed and the process proceeds to the next process. When the instruction code is memory write, it is determined whether or not the attribute of the memory corresponding to the access address is writable (W).
5 (ST104), error display processing is performed in the display processing unit 43 only when writing is not possible (ST1).
03) and proceed to the next processing. When the instruction code is other than that, the processing directly proceeds to the next processing.

By setting the attribute information of the memory in the access management table 35 in advance, judging the kind of the instruction, and detecting the error of the memory access, for example, the access to the address which is not the program area and the memory are mounted. An error can be detected when there is an unauthorized access to an area that does not exist. Conventionally, memory access error detection is a function of the in-circuit emulator. This is because the attributes of memory are written in the map table in advance,
When there is a memory access, it is detected by hardware.

When an address where the memory is not mounted or an address which is not the program area is to be executed, the instruction fetch address error can be detected in the same manner.

Next, a specific processing example centering on the display processing of the in-circuit emulator having the above-mentioned configuration will be described with reference to the flowcharts of FIGS.

FIG. 21 is a flow chart for explaining the execution display processing of the embodiment of the present invention.

In the figure, first, in the execution processing unit 37, the execution flag by the instruction execution is set in the code table 32.
(ST111). Next, the display processing unit 43 determines whether the program execution flag of each line is on or off (ST112), performs white display processing for that line when it is off (ST113), and displays that line in green when it is on. The process is performed (ST113) and the process proceeds to the next process.

By detecting ON / OFF of the execution flag by the instruction execution of the code table 32 and displaying it in white or green in accordance with the color, it is possible to grasp whether or not the program has been executed. You can check the completeness of the so-called white box test. In the past, such comprehensiveness could not be easily visually checked.

FIG. 22 is a flow chart for explaining the cursor RAM display processing of the embodiment of the present invention.

In the figure, first, the display processing unit 43 obtains an addressing function by table search from the operation code of the cursor (ST121), and then calls the addressing function to obtain a memory address (ST12).
2) Then, the contents of the memory are displayed from the RAM address (ST123).

The value of the RAM pointed to by the instruction to be executed can be easily confirmed simply by moving the cursor. Conventionally, R required for the memory dump command
Since AM is displayed or only the place where the program counter is present is displayed, the operation is complicated.

FIG. 23 is a flow chart for explaining the skip processing of the embodiment of the present invention.

In the figure, first, the current nest is saved (ST131), and then the instruction is executed (ST132).
After that, when the return is returned, the saved nests are compared (ST133). When the save value is smaller than the nest value, the operation is returned to the instruction execution. When the save value is larger than or equal to the nest value, the next processing is performed. move on. When the save value is smaller than the nest value, the display processing is not performed.

The tested routine does not need to be traced and confirmed at each step, and only needs to be processed so that the time is shortened. Conventionally, a breakpoint is placed at the instruction next to the call instruction, and execution is continued up to that address.

In the case of an instruction execution error, it is counted for each error type, and the result is displayed at the end of the program and written in the trace file 48. The displayed error messages include, for example, incorrect instruction code, data length selection flag and object code, jump destination is in the middle of instruction line, read-protected memory is read, write-protected memory is written,
An address is not defined is displayed.

Next, the linkage between the emulator main unit 1 side and the personal computer side system unit 2 side will be described with reference to FIGS. 24 and 25.

FIG. 24 is a flow chart for explaining the execution of instructions according to the embodiment of the present invention.

In the figure, first, the personal computer side system section 2 obtains an execution address from the execution line (ST141), and then transmits the execution address to the emulator main body section 1 side (ST142). Then, the completion of execution in the emulator main body 1 is judged (ST143), and the process is terminated by the completion of execution.

FIG. 25 is a flow chart for explaining the linkage between the emulator body (ICE) and the personal computer (PC) according to the embodiment of the present invention.

In the figure, first, on the ICE side, a PC
Whether or not the command is received from the side (ST151), when the command is received, the process proceeds to the command execution routine (ST152), after completion, the data of the execution result is transmitted from the ICE to the PC (ST153), and the command is received again or not. Return to the judgment step. Next, on the PC side, a CRT display (ST154), which is a monitor screen, is performed, and it is determined whether or not there is a key input (ST155). When there is a key input, command execution and command transmission to the ICE side (ST).
156), subsequently, it is judged from the ICE side whether or not the execution result data is received (ST157), and when the data is received, the process returns to the CRT display step. Where ICE and P
The communication format with the C side is, as shown in Table 4,
Its format is a header code, transmitted data, and finally an error control checksum. For example, from ICE side to PC
Sending the register contents to the
0 ”, transmission data“ register A ”,“ register B ”,
The checksum follows the "register PCL", and when transmitting the memory contents, the checksum follows the header code "01" and the transmission data "transmission memory with address 0" to "transmission memory with sequentially incremented address". Further, in the transmission from the PC side to the ICE side, the checksum follows the header code “80”, the transmission data “command”, the “transmission memory address”, the “data”, and the “program counter”. Examples of commands are register setting / display, memory setting / display, program save / display, execution 1 step / continuous, and the like.

[0091]

[Table 4]

According to the in-circuit emulator having the above-mentioned configuration, the disassembling processing means 24, the check processing means 25, the interpretation execution control means 26, which are function realizing means by software configured on the PC of the host computer,
By providing the display processing means 27, the command processing means 29, etc., the assemble list (list file) created at the time of assembly can be read and executed by the emulator main body (ICE) 1 one instruction at a time.
By performing various error checks that cannot be done by the assembler, debugging, which could not be done by human eyes and hands, can be done mechanically accurately and in a short time, and the efficiency of system development can be improved.

Further, the execution processing section 37 counts the execution lines, and the display processing section 43 displays the number of executions on the display screen of the monitor 28. Can be understood.

Further, since the error detecting section 34 checks the RAM access using the access management table, the RAM access status can be grasped.

The display processing unit 43 performs display processing, and the RAM display unit 60b is displayed on the display screen 60 of the monitor 28.
Since the contents of the RAM table 41, the contents of the source program with the cursor on the trace display unit 60c, and the contents of various registers on the registers display unit 60e are displayed on one screen, the instruction is executed. However, changes in RAM and registers can be checked at the same time, and efficient debugging can be performed. Further, in the display processing unit 43, the display color is changed by executing the command, and the executed line can be confirmed. Therefore, when the internal processing function is clear, the input that passes through all the paths of this processing routine is performed. The so-called white box that gives the data and checks the result
You can grasp the completeness of the test.

Since the test result of the program is stored in, for example, the trace file 48, it is possible to check the test result later on the desk. Further, an input command can be given from the log file by automatic operation, which allows a person who does not know the contents of the program to easily handle it.

In the above embodiment, the microcomputer is taken as an example, but it can be applied to the program development of a system equipped with various microcomputers, and the host computer can be a workstation or personal computer having the required performance and capacity. Can be used.

Further, the operation code table 38 and the address function routine 39 are arbitrarily set according to the instruction of the target CPU and the type of the host computer. The error detection in the check processing means 25 of the embodiment is a typical example, and any other error detection can be added. Further, the display screen of the monitor 28 is an example, and the display screen is not limited to the embodiment.

[0099]

As described above, the present invention is provided with the disassembling processing means 24, the check processing means 25, the interpretation execution control means 26, the display processing means 27, the command processing means 29, etc. By reading the list and executing it one instruction at a time in the emulator main unit, and performing various error checks that cannot be done by the assembler or conventional in-circuit emulator, the program can be debugged accurately and quickly, improving the development efficiency. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an overall system configuration of an in-circuit emulator according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a specific configuration of the in-circuit emulator according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating an overall configuration of an in-circuit emulator according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a specific example of an assemble list according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a specific example of a code table according to the embodiment of this invention.

FIG. 6 is a diagram illustrating a specific example of an access management table according to the embodiment of this invention.

FIG. 7 is a diagram illustrating a specific example of an operation code table according to the embodiment of this invention.

FIG. 8 is a diagram illustrating a relationship between an address function and an execution routine according to the embodiment of this invention.

FIG. 9 shows a sample display screen by the display processing unit according to the embodiment of the present invention.

FIG. 10 is a flowchart illustrating main processing at the time of execution of the embodiment of the present invention.

FIG. 11 is a flowchart illustrating nest management processing of call instructions according to the embodiment of this invention.

FIG. 12 is a flowchart illustrating NOP processing that skips execution of an instruction according to the embodiment of this invention.

FIG. 13 is a flowchart illustrating break processing according to the embodiment of this invention.

FIG. 14 is a flowchart illustrating a debug rate grasping process according to the embodiment of this invention.

FIG. 15 is a flowchart illustrating a PC setting process according to an embodiment of the present invention.

FIG. 16 is a flowchart illustrating a pseudo instruction execution error detection process according to the embodiment of this invention.

FIG. 17 is a flowchart illustrating a jump instruction jump destination error detection process of the embodiment of the present invention.

FIG. 18 is a flowchart illustrating an immediate data length error detection process of the embodiment of the present invention.

FIG. 19 is a flowchart illustrating an immediate index length error detection process according to the embodiment of this invention.

FIG. 20 is a flowchart illustrating a memory access error detection process according to the embodiment of this invention.

FIG. 21 is a flowchart illustrating an execution display process according to the embodiment of this invention.

FIG. 22 is a flowchart illustrating cursor RAM display processing according to the embodiment of the present invention.

FIG. 23 is a flowchart illustrating skip processing according to the embodiment of this invention.

FIG. 24 is a flowchart illustrating execution of instructions according to an embodiment of the present invention.

FIG. 25 is an emulator main body (ICE) according to an embodiment of the present invention.
3 is a flowchart illustrating a linkage between a computer and a personal computer (PC).

[Explanation of symbols] 1 emulator main unit 2 personal computer side system unit 20 in-circuit emulator 21 source program 22 assemble list 23 input / output interface 24 disassembly processing unit 25 check processing unit 26 interpretation execution processing unit 27 display processing unit 28 monitor 29 Command processing unit 30 Input / output device 31 Disassembly processing unit 32 Code table 33 Text table 34 Error detection unit 35 Access management table 36 Flag 37 Execution processing unit 38 Operation code table 39 Address function routine 41 RAM table 42 Symbol table 43 Display processing Part 44 symbol file 45 generation part 46 program counter 47 pointer 48 trace file 60 display screen 23 input / output interface 24 disassembly Processing means 25 Check processing means 26 Interpretation execution means 27 Display processing means 28 Monitor 29 Command processing means 30 Input / output equipment 31 Disassembly processing section 32 Code table 33 Text table 34 Error detection section 35 Access control table 36 Flag 37 Execution processing section 38 Opcode table 39 Address function routine 40 Execution routine 41 RAM table 42 Symbol table 43 Display processing unit 44 Symbol file 45 Generation unit 46 PC (program counter) 47 Pointer 48 Trace file 49 Keyboard 50 Floppy disk device 51 Hard disk device 52 Printer 60 display screen

Claims (21)

[Claims] 1. A disassembling means for disassembling an assemble list generated from a source program of a target system on a host computer to obtain a code table and a text table, and the code table and the text table. A check processing means for detecting an error based on the above, an interpretation execution control means for transmitting the instruction code of the code table to the emulator main body one instruction at a time and receiving a result executed by the emulator main body, and an error of the check processing means. Display processing means for performing processing for displaying the detection result and the execution result of the interpretation execution control means on a monitor; and command processing means for processing command instructions for the disassembly processing means, check processing means, interpretation execution control means, and display processing means. In-circuit emulator equipped with. 2. The code table of the disassembling processing means has an execution flag for each instruction line, which sets execution completion by instruction execution by the interpretation execution control means.
In-circuit emulator described. 3. The in-circuit emulator according to claim 1, wherein the code table of the disassembly processing unit has a break flag for setting / clearing a break point by a command for each instruction line. 4. The error check processing means performs error detection processing based on an access management table in which the attribute information of the memory of the target system is set in advance by a command, and the code table, text table, and access management table. 4. The in-circuit emulator according to claim 1, further comprising a detection unit and a flag set when an error is detected. 5. The in-circuit emulator according to claim 4, wherein the error detection unit detects whether the instruction fetched from the code table is a pseudo instruction. 6. The error detecting section according to claim 4, wherein when the instruction fetched from the code table is a jump instruction, the jump destination address is calculated from the operation code and the presence or absence of the corresponding address on the table is detected. In-circuit emulator. 7. The error detecting section according to claim 4, wherein when the instruction fetched from the code table is an immediate data instruction, the error detecting section obtains an operation code length on the table and judges a data length flag of the CPU status. In-circuit emulator. 8. The error detecting section obtains an opcode length on a table when the instruction fetched from the code table is an immediate index instruction, and C
The in-circuit emulator according to claim 4, wherein the index length flag of the PU status is determined. 9. The error detecting unit reads the type of the instruction code fetched from the code table from the memory,
5. The in-circuit emulator according to claim 4, wherein it is judged whether it is a memory write or the like, and it is judged whether the memory attributes of the access management table corresponding to the respective access addresses match. 10. The interpretation execution control means corresponds to an operation code table for associating with an object program of the code table, an address function routine for obtaining an address of an operand of a machine code, and a target system. RA that reads and writes by executing instructions
The machine code in the M table and the code table is fetched, the match between the machine code in the operation code table is compared, the corresponding execution routine of the matched machine code is called, and the address function corresponding to the addressing mode is executed in this execution routine. And an execution processing unit that acquires an address and executes an instruction.
In-circuit emulator according to item 2, 3 or 4. 11. The execution processing unit is provided with a nest as a pointer for managing a call instruction, adds 1 to the nest at the time of a call instruction, subtracts 1 from the nest at the time of a return instruction, and next at the time of a call instruction. 11. The in-circuit emulator according to claim 10, which executes the instructions of. 12. The execution processing unit, when a no-operation command is keyed in, advances the current cursor line by one line and then skips the value of the program counter to the next instruction without executing the instruction. An in-circuit emulator according to item 10. 13. The in-circuit emulator according to claim 10, wherein the execution processing unit determines whether a break flag of the code table is turned on or off at the time of executing an instruction, and generates a break if the break flag is turned on. 14. The execution processing unit determines whether the execution flag of the code table is on or off. If the execution flag is off, the execution line count is incremented by 1, and the execution flag is turned on. The in-circuit emulator according to claim 10, wherein the debug rate is calculated based on the value of the line count. 15. The display processing means monitors data provided from a symbol table in which symbols and addresses of data generated from the error detection unit, the execution processing unit and the symbol file of the assemble list are associated with each other. 11. The in-circuit emulator according to claim 1, further comprising a display processing unit that performs display processing for displaying on the screen. 16. The display processing unit determines whether the execution flag of the code table set by the instruction execution of the execution processing unit is turned on or off, and displays the line by color according to on or off. 16. The in-circuit emulator according to claim 15, which processes the display of. 17. The display processing unit obtains an addressing function by performing a table search from an operation code of a cursor,
The in-circuit emulator according to claim 15, which performs a process of calling an addressing function routine to obtain an address of a memory and displaying a content of the memory from a RAM address. 18. The display processing unit saves the current nest, compares the saved nest when returning after execution of an instruction, and skips display when the saved value is smaller than the nest value. The in-circuit emulator according to claim 11 or 15. 19. The display screen displayed on the monitor by the display processing unit includes a RAM display unit for displaying the symbol name of the RAM table, its address and the contents of the address, and the contents and underline of the text table. 16. The in-circuit emulator according to claim 15, further comprising a trace display unit for displaying the current cursor position with a mark and a register display unit for displaying the contents of the registers on one screen. 20. The display screen displayed on the monitor by the display processing unit has an execution status display unit for displaying the ratio of the number of executed steps to the total number of executed steps.
The in-circuit emulator described in 5 or 19. 21. The in-circuit emulator according to claim 15, 19 or 20, wherein the display screen displayed on the monitor by said display processing unit has a register display unit for displaying the contents of registers.