JPH07184376A - Inverter - Google Patents

Abstract

PURPOSE:To minimize a switching time and reduce a loss in switching in an inverter. CONSTITUTION:When an output current signal from an inverter is reduced and the voltage is lowered than a reference voltage (Va), a comparator 16a starts to operate and a switching element 2a is driven through buffers 14 and 14a. A discharged current from a gate is passed through gate resistors 15 and 15a. The gate resistors 15 and 15a are connected in parallel and the apparent resistance is reduced so that an input capacity of the switching element 2a has a shorter discharging time. Then, the switching time is reduce. In addition, a comparator 16b, 16c and so on that become lower than reference voltages (Vb, Vc, and so on) are sequentially operated. In this way, the switching time of the switching element 2a is reduced, and the loss in switching is much reduced. As for a surge voltage, a switching time is reduced, but the output current signal from the inverter is made smaller, so the surge voltage is held almost at the same level as before.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a gate drive circuit with inverter output current signal information so that the output impedance of the gate drive circuit is determined based on the inverter output current signal. The present invention relates to an inverter device that controls the switching time of a semiconductor switch element.

[0002]

2. Description of the Related Art FIG. 1 is a system diagram of a motor drive by a conventional inverter device. DC power supply 1 is M
It is connected to OS input type semiconductor switch elements (hereinafter simply referred to as switch elements) 2a to 2c and 3a to 3c.
The current paths from the DC power supply 1 to the three-phase motor 4 are switched by switching the energization states of the switch elements 2a to 2c and 3a to 3c, respectively. Further, diodes 5a to 5c and 6a to 6c are reversely connected in parallel to the current input terminals and output terminals of the switch elements 2a to 2c and 3a to 3c, respectively.

The current sensors 7a and 7b are U phase,
The W-phase inverter output current is detected and transmitted to the current signal amplifier circuit 8. Then, the current signal amplification circuit 8 transmits the current signal to the controller 9. Based on the inverter output current signals of the current sensors 7a and 7b and the accelerator signal of the accelerator sensor 10, the controller 9 sets the
The gate drive circuits 11a to 11f are driven so that the phase motor 4 outputs a predetermined torque. The gate drive circuits 11a to 11f use the drive signal from the controller 9 as a trigger to switch the switch elements 2a to 2c.
And 3a to 3c.

FIG. 2 shows the gate drive circuits 11a to 11f.
It shows the details of. The buffer 12 drives the photocoupler 13 with the drive signal from the controller 9, and the photocoupler 13 drives the buffer 14. Then, the buffer 14 charges and discharges the gate capacitance of each of the switch elements 2a to 2c and 3a to 3c through the gate resistor 15.

In the conventional inverter device having the above structure, when the switch element is driven, the resistance value of the gate resistance of the gate drive circuit is increased to lengthen the switching time, whereby the switching surge voltage (hereinafter referred to as surge voltage) is increased. It was suppressed. This is because if the surge voltage is too large and exceeds the allowable range, the switch element is destroyed by overvoltage. The switching time is a turn-on time and a turn-off time of the switch element shown in FIG. 3A, and particularly this turn-off time is involved in the surge voltage (see FIG. 3).
(See (b)). The surge voltage ΔV is calculated by the formula ΔV = -L · dI
As shown by / dt (L ... Wiring inductance, I ... Current of switch element), it is understood that the surge voltage increases in principle when the switching time (turn-off time) is short. On the other hand, the switching time of the switch element is determined by the charging / discharging time of the input capacitance,
As described above, the resistance value of the gate resistance of the gate drive circuit is increased and the switching time is lengthened to prevent overvoltage breakdown.

However, if the switching time is lengthened as described above, switching loss increases. The switching loss is a loss in a transient region in which a switch element makes a transition from on to off or from off to on, and accounts for most of the loss of the inverter. The switching loss P is calculated by the following formula.

[0007]

[Equation 1] Here, the integration section T1 to T2 is the switching time (turn-off time) shown in FIG.

[0008]

However, in the above-mentioned conventional inverter device, since the output impedance of the circuit for charging the input capacitance of the switch element is fixed, the current flowing through the switch element may reach the maximum value. The switching time must be set in consideration.
For this reason, there is a problem that the switching time cannot be shortened when a current equal to or less than the maximum value flows to reduce the switching loss. The present invention has been made by paying attention to the fact that the surge voltage is proportional to the inverter output current, and the switching impedance is controlled by controlling the output impedance of the circuit that charges the input capacitance according to the current flowing through the switch element. An object of the present invention is to provide an inverter device that can minimize the time and reduce the switching loss.

[0009]

In order to achieve the above object, an inverter device of the present invention according to claim 1 is a power converter composed of a DC power source and a switch element connected in series to the DC power source. And an inverter device in which the series connection points of the switch elements are output terminals, respectively, the switching time of the switch elements can be directly controlled according to the inverter output current or the current flowing through the switch elements. .

According to a second aspect of the present invention for attaining the above object, in the first aspect, the switching time of the switch element can be continuously controlled.

According to a third aspect of the present invention to achieve the above object, an inverter device of the present invention includes a DC power source, a power converter including a switching element connected in series to the DC power source, and the switch. In an inverter device in which elements connected in series are output terminals, the switching time of the MOS input type semiconductor switch element is controlled according to the inverter output current or the current flowing in the MOS input type semiconductor switch element. It is characterized in that the charging and discharging paths of the gate capacitance are switched by the gate driving circuits connected in parallel.

Further, in order to achieve the above-mentioned object, an inverter device of the present invention according to claim 4 is a DC power source, a power converter comprising a switching element connected in series to the DC power source, and the switch. In an inverter device in which the series connection points of the elements are output terminals, the inverter output current or amplitude information of the current flowing through the switch element is transmitted to a gate drive circuit, and the output impedance of the gate drive circuit is transmitted to the gate drive circuit. It is configured such that it is determined based on the current signal information thus obtained, and the switching time of the switch element can be controlled.

[0013]

The inverter device of the present invention having the above-described structure can directly control the switching time of the switching element according to the inverter output current or the current flowing through the switching element. Further, the invention of claim 3 or claim 4 controls the output impedance of the gate drive circuit based on the inverter output current or the current flowing through the switch element. Therefore, the switching time of the switch element can be shortened and the switching loss can be reduced within a range in which the switch element is not damaged by the surge voltage due to the surge voltage. In particular, in the inverter device for electric vehicles, the reduction of switching loss has an excellent effect such that the traveling distance can be extended, the load of the inverter cooling device can be reduced to reduce the cost, and the reliability can be improved. Can bring

[0014]

【Example】

(First Embodiment) A first embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 4 is a system diagram of a motor drive by the inverter device of the present invention. It differs from the conventional one shown in FIG. 1 in that a current signal is directly transmitted from the current signal amplifier circuit 8 to not only the controller 9 but also the gate drive circuits 21a to 21f. Since the gate drive circuits 21a to 21f of the inverter device of the present invention have the same configuration, the details of the gate drive circuit 21a for driving the switch element 2a are shown in FIG.

The gate drive circuit 21a is similar to the conventional one, that is, the current signal amplifier circuit 8 → the controller 9 → the buffer 1
2 → photo coupler 13 → buffer 14 → gate resistor 15
→ The comparators 16a to 16n → the buffers 12a to 12n are connected between the charge / discharge path 22 for charging / discharging the gate capacitance and the current signal amplifier circuit 8 and the switch element 2a, respectively, by transmitting the drive signal in the order of the switch element 2a. → Photo couplers 13a to 13n → AND circuits 17a to 17n → Buffers 14a to 14n → Gate resistors 15a to 15n are connected in this order, and each path is connected in parallel, and a drive signal is transmitted in the order of the connection. The charging / discharging paths 22a to 22n charge and discharge the gate capacitance. The charge / discharge path 2 is connected to each of the comparators 16a to 16n.
Comparison reference voltage v _a to v _n with low voltage in the order of subscript 2A～22n a to n are set. In addition, the charge / discharge path 2
The output of the second photocoupler 13 is the charge / discharge paths 22a to 22a.
22n AND circuits 17a to 17n.

The operation of the gate drive circuit 21a having the above structure will be described below. The inverter output current signal from the current signal amplifier circuit 8 is directly input to the comparators 16a to 16n of the charge / discharge paths 22a to 22n. Each comparator 16a-16n, is compared with the comparison reference voltage v _a to v _n respectively set. Voltage of the inverter output current signal is larger than the comparison reference voltage v _a to v _n, each photocoupler 13a~13n is not driven. Therefore, when the drive signal is input from the controller 9, only the charge / discharge path 22 is established and the buffer 14 drives the switch element 2a. At this time, the charge / discharge current of the gate passes through the gate resistor 15.

However, when the inverter output current signal decreases and the voltage decreases and becomes lower than the comparison reference voltage v _a , the comparator 16a operates to establish the charging / discharging path 22a, and the buffer elements 14a drive the switch element 2a. To do. At this time, the charge / discharge current of the gate passes through the gate resistors 15 and 15a. In this case, the gate resistors 15 and 15a are connected in parallel, and the gate resistance is apparently reduced. When the gate resistance is reduced, the charging / discharging time of the input capacitance of the switch element 2a is shortened and the switching time is shortened. If the switching time becomes short,
Switching loss can be reduced. In this case, the switching time for the surge voltage is shortened, but the inverter output current signal during switching is also reduced.
The surge voltage is kept at about the same level.

Furthermore, when the voltage inverter output current signal is reduced is lowered, the charge and discharge path 22b · comparator 16b · · · 16n becomes lower than the comparison reference voltage v _b ... v _n is operated in order ..22n is established and the apparent gate resistance is reduced, so that the switching time of the switch element 2a is shortened and the switching loss can be further reduced. Also in this case, the surge voltage is maintained at substantially the same level by reducing the inverter output current signal during switching. The gate drive circuits 21b to 21f
The operation of is also the same as above.

FIG. 6 is a timing chart of a gate drive circuit composed of a charge / discharge path 22 for drive signals and charge / discharge paths 22a to 22c. FIG. 6A (hereinafter, omitted from FIG. 6) shows a drive signal output from the controller 9 by generating a PWM waveform by comparing the inverter output current signal with a triangular wave. (B) shows a comparison of the comparison reference voltage v _a to v _c and the inverter output current signal.
(C) shows the operation of the comparators 16a to 16c. Further, (D) shows the operating states of the charge / discharge path 22 and the charge / discharge paths 22a to 22c.

FIG. 7 shows switching elements 2a to 2c and 3a.
3C is a comparison of the surge voltage levels in the present example and the conventional example in the on / off states of 3c. In the case of the conventional example, the surge voltage level is substantially proportional to the absolute value of the inverter output current signal shown in FIG. Therefore, there is a margin with the allowable level, and there is room for shortening the switching time. On the other hand, in the case of this embodiment, as described above, the switching time is shortened according to the magnitude of the inverter output current signal, and the surge voltage level is controlled to be substantially constant. The switching loss can be reduced by optimizing.

(Second Embodiment) FIG. 8 shows a gate drive circuit according to the second embodiment. The gate drive circuit 31 is provided in each of the switch elements 2a to 2c and 3a to 3c, and the current signal amplifier circuit 8 → controller 9 → buffer 12 → photo coupler 13 → buffer 14 → current source 32 → switch elements 2a to 2c, respectively. Connect in the order of 3a to 3c. And
The controller 9 gives an on / off signal (on / off signal of the switch element) to the current source 32. The output current value of the current source 32 is determined by the inverter output current signal output from the current signal amplifier circuit 8. That is, the current source 3
The output impedance of 2 is determined by the inverter output current signal. When the inverter output current is maximum, the gate capacitance of the switch element is slowly charged, and as the inverter output current becomes smaller, the gate capacitance is quickly changed. Be sure to charge it so that the surge voltage does not exceed the allowable level. Therefore, the switching time can be shortened and the switching loss can be reduced.

FIG. 9 shows the relationship between the inverter output current signal and the output impedance in the case of the second embodiment, and also shows the output impedance in the case of the gate drive circuit of the first embodiment shown in FIG. It is a thing. Also, FIG.
Similarly, 0 indicates the relationship between the inverter output current signal and the surge voltage level. The frequency of the inverter output current signal is several hundred Hz, and the carrier frequency (the frequency of the triangular wave that generates the PWM waveform) is several tens kHz. Since the frequency is considerably high, even in the case of the first embodiment, the surge voltage level remains below the allowable level for a long period as shown in the figure.
There is room for further shortening of switching time.

The gate drive circuit 31 of the present embodiment transmits an analog current signal to the current source 32 to continuously control the switching time, and it is not necessary to form a plurality of charge / discharge paths, so the cost is low. Can be

[Brief description of drawings]

FIG. 1 is a system diagram of a motor drive by a conventional inverter device.

FIG. 2 is a gate drive circuit diagram of a conventional inverter device.

FIG. 3 is an explanatory diagram of switching time and surge voltage.

FIG. 4 is a system diagram of a motor drive by the inverter device of the first embodiment.

FIG. 5 is a gate drive circuit diagram of the inverter device of the first embodiment.

FIG. 6 is a timing chart of a gate drive circuit.

FIG. 7 is a timing chart comparing the surge voltage of the conventional example with that of the present invention.

FIG. 8 is a circuit diagram of a gate drive circuit according to a second embodiment.

FIG. 9 is a timing chart showing the relationship between the inverter output current signal and the output impedance in the second embodiment.

FIG. 10 is a timing chart showing the relationship between the inverter output current signal and the surge voltage level in the second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 DC power supply 2a-2c, 3a-3c MOS input type semiconductor switch element 4 3-phase motor 8 Current signal amplification circuit 9 Controller 12a-12n, 14a-14n Buffer 13a-13n Photocoupler 15, 15a-15n Gate resistance 16a-16n Comparator 17a-17n AND circuit 22, 22a-22n Charge / discharge path 21a-21f Gate drive circuit 32 Current source

Claims (4)

[Claims] 1. A power converter composed of a DC power supply, a MOS input type semiconductor switching device connected in series to the DC power supply, and an inverter having output terminals at series connection points of the MOS input type semiconductor switching device. In the apparatus, the switching time of the MOS input type semiconductor switching element can be directly controlled according to an inverter output current or a current flowing in the MOS input type semiconductor switching element. 2. The inverter device according to claim 1, wherein the switching time of the MOS input type semiconductor switch element can be continuously controlled. 3. A power converter composed of a DC power supply, a MOS input type semiconductor switching device connected in series with the DC power supply, and an inverter having output terminals at the series connection points of the MOS input type semiconductor switching device. In the device, control of the switching time of the MOS input type semiconductor switching element, which is performed according to the inverter output current or the current flowing in the MOS input type semiconductor switching element, is performed by a gate drive circuit in which a gate resistor is connected in parallel to fill the gate capacitance. An inverter device characterized by performing a discharge path switching. 4. A power converter composed of a DC power source, a MOS input type semiconductor switching device connected in series to the DC power source, and an inverter having output terminals at series connection points of the MOS input type semiconductor switching device. In the device, an inverter output current or amplitude information of a current flowing through the MOS input type semiconductor switch element is transmitted to a gate drive circuit, and the output impedance of the gate drive circuit is based on the current signal information transmitted to the gate drive circuit. An inverter device characterized in that the switching time of the MOS input type semiconductor switch element is controllable by being configured to be determined.