JPH07183926A - Qpsk preamble signal generator - Google Patents

Abstract

PURPOSE:To enable clock extraction even when a frequency error is 9 large by repeatedly generating a signal obtained by inverting both an in-phase signal of symbol values of QPSK and an orthogonal signal, and a signal obtained by inverting one of them, each a specific number of times. CONSTITUTION:Pattern generating means 11 and 12 input the in-phase signal I and orthogonal signal Q outputted from a register 13, and the means 11 inverts the signs of both the signals I and Q and outputs them. The means 12, on the other hand, generates the signal, obtained by inverting the signal I while the signal Q is not inverted, and the signal obtained by inverting the signal Q while the signal I is not inverted, alternately at intervals of (r) times. One of the signals I and Q generated by the means 11 and 12 respectively is selected by a selector 14 and the signals I or Q is outputted through the output register 13. This constitution provides variation passing through an origin on an IQ plane and facilitates the extraction of a clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is particularly suitable for a burst-generated QPSK signal, and a preamble signal which is added to the beginning of the QPSK signal or inserted in a blank part and used for extraction of a symbol clock timing on the receiving side. It relates to a signal generator to be generated.

[0002]

2. Description of the Related Art Conventionally, a multiplexed signal of 1, -1,1, -1, ... Is used for this type of preamble signal.

[0003]

In the conventional preamble signal, on the IQ plane (I is an in-phase signal having a symbol value of QPSK, Q is a quadrature signal), a signal point P _{1 in} the first quadrant and a quadrant in the third quadrant are used. a signal for reciprocating the signals back and forth between signal point P _3, or the second quadrant of the signal point P ₂ and the fourth quadrant of the signal point P _4, 0 point for each change in each symbol (I, Q-plane Since it passes through the origin, it is possible to easily detect the clock timing of the symbol by detecting the zero crossing.

However, when the frequency error becomes large, the IQ
The direction of reciprocation on a plane tends to be parallel to the I axis or the Q axis, making it difficult to detect the passage of the 0 point and making it difficult to detect the clock timing. Further, it becomes difficult to detect the frequency error.

[0005]

According to a first aspect of the present invention, there is provided a first pattern generating means for generating a signal obtained by inverting both an in-phase signal and a quadrature signal having a QPSK symbol value,
Generating a signal that is one of the in-phase signal and the quadrature signal inverted, and alternating the inverted signal every r times; and generating a signal m times from the first pattern generating means, And means for repeating the generation of the signal n times by the second pattern generating means.

According to a second aspect of the invention, the second pattern generating means of the first aspect of the invention generates not only the inversion signal of the in-phase signal and the quadrature signal but also the inversion signal of both signals. The three signals are alternated every r times. According to the invention of claim 4, in the invention of claim 2, the generation of the three signals by the second pattern generating means is randomly replaced.

According to the invention of claim 5, the generation by the first pattern generating means and the generation by the second pattern generating means in the invention of claim 1 are repeated at random.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 functionally shows an embodiment of the present invention. A first pattern generating means 11 and a second pattern generating means 12 are provided, and these first and second pattern generating means 11,
The in-phase signal I and the quadrature signal Q output from the output register 13 are respectively input to the output terminal 12, and the first pattern generating means 11 outputs both signals I and Q with their signs inverted.
The second pattern generating means 12 inverts the input in-phase signal I and does not invert the quadrature signal Q, a signal that does not invert the in-phase signal and inverts the quadrature signal Q, the in-phase signal I and the quadrature signal. Either the signal that does not invert the signal Q is generated.

One of the signals I and Q generated by the first and second pattern generating means 11 and 12 is selected by the selector 14 and stored in the output register 13, and the signals I and Q are output from the output register 13. To be done. Control unit 15
Thus, the designation of the generated signal in the second pattern generating means 12 and the designation of the output signal of the first and second pattern generating means 11, 12 in the selector 14 are designated. Further, the whole operates in synchronization with the clock from the clock generator 16.

In FIG. 2, the output of the first pattern generating means 11 and the output of the second pattern generating means 12 are alternately selected (m = n = 1), and in the second pattern generating means 12, the same phase is selected. A processing procedure when the signal I and the quadrature signal Q are alternately inverted (r = 1) will be described. First, the in-phase signal I,
The quadrature signal Q is set to 1 and the parameters A and B are set to 1 respectively.
(S ₁ ), waits for the clock to be input (S ₂ ), and when input, determines whether the parameter A is positive (S ₃ ). signal I, and generates a signal obtained by inverting each multiplied by -1 to Q-phase signal I, as an orthogonal signal Q (S _4). After that, when the parameter A is positive and the signals I and Q from the first pattern generating means 11 are output to the register 13 (S ₅ ), the parameter A
By multiplying by -1 to return to step S ₂ as a parameter A (S _6).

On the other hand, step S₃If A is not positive in
Check if parameter B is positive (S ₇), If positive then
The two-pattern generating means 12 multiplies the signal I by -1 (S
₈). After that, the parameter B is multiplied by -1, and the parameter is
Step S as B_FiveMove to (S₉). Step S_Fiveso
Since the parameter A is negative, the second pattern generating means 12
To output the signals I and Q to the register 13. Step S
₇And B is not positive, the second pattern generating means 12 outputs a signal.
Multiply Q by -1 and step S₉Move to (S_Ten).

Each time the clock is input, the register 13
The signals I and Q output from are as shown in FIG. 3A,
This preamble signal sequentially moves through every clock as shown in FIG. 4A on the IQ plane. In this way, each symbol (clock) passes through the origin of the IQ plane,
The movement facilitates detection of clock timing, and the movement of each symbol in parallel with the I axis or Q axis facilitates detection of frequency error. This means that each signal point P
_It is understood that _{1 to} P ₄ are at the same point unless there is a frequency error, and in the case of the same data, the signal points P _{1 to} P ₄ are displaced due to the frequency error, so that it is easy to detect the frequency error.

Further, the instantaneous power (√ {I (t) ² + Q (t) ² }) of this preamble signal becomes as shown in FIG. 5A, and the point at which the variance value at each time point becomes the minimum is obtained. When the clock timing is calculated, it is sufficient that there are at least two consecutive symbol data, that is, if there are at least one pattern from the first pattern generating means 11 and at least one pattern from the second pattern generating means 12. The clock timing can be detected very well very well. Regarding the instantaneous power,
If the difference between the symbol-delayed one and the symbol-delayed one is taken, the center of the symbol becomes the zero-cross point as shown in FIG. 5B, and therefore the clock can be extracted from this operation. This means that the midpoint between the maximum and the minimum in the instantaneous power is the same value, and the timing when the values before and after one symbol are the same is the center of the symbol (clock timing).

FIG. 6 shows another embodiment of the present invention.
The same symbols are attached to the portions corresponding to. In this example
The processing of the 2 pattern generation means 12 is different from that of FIG.
S ₈, S_TenFrom step S₉Without moving to
Parameter B is incremented by 1 to obtain parameter B (S₁₁), The para
Check if meter B is 3 or more (S₁₂), 3
In the above case, the parameter B is set to -1 in step S_FiveTo
Move, step S₁₂And parameter B is 3 or more,
Step S_FiveMove on to.

The signals I and Q output in this case are shown in FIG. 3B.
And the movement on the IQ plane is as shown in FIG. 4B. In the case of FIG. 2, the signals I and Q are alternately inverted by the second pattern generating means 12, but in FIG. 6, the signal I is inverted twice and then Q is inverted twice.
By doing so, the direction of movement following the signal point on the IQ plane is counterclockwise in FIG. 2 (FIG. 4A), but twice in FIG. 6 (FIG. 4B). Occur one by one. When the rotation direction changes before and after such an oblique change, it passes relatively straight around zero, and it becomes easier to detect correctly than the clock timing.

When the signal is generated m times from the first pattern generating means 11 to be output and the signal is generated n times from the second pattern generating means 12 to be output, for example, in FIG. 2, immediately after step S ₄ . m is decremented by 1 to be m, and the process proceeds to step S _5. Also, after step S ₉ , n is decremented by 1 and n.
Then, the process proceeds to step S ₅ , and in step S ₆ , m = 0, n
Only when = 0, it is sufficient to multiply A by -1 and set m and n respectively.

The output of the first pattern generating means 11 and the second
The output of the pattern generating means 12 is randomly selected, and
The signals to be inverted by the second pattern generating means 12 are I and Q.
It is also possible to randomly select from. That
FIG. 7 shows an example of the processing procedure in this case. That is, first the signal I
1, signal Q is initialized to 1 (S₁),clock
Wait for input (S₂), When the clock is input, a random number
Is generated (S₃), Determine if the generated random number is even
Set (S_Four), If it is even, the first pattern generating means 11
Signal from (S_Five), The signal to register 13
Output to (S ₆).

If the random number is not an even number in step S ₄ , a random number is generated again (S ₇ ), and it is checked whether the random number is an even number (S ₈ ).
In by multiplying -1 to the signal I (S _9), and stores the signal of the second pattern generation unit 12 to the register 13 (S _6),
Steps random number S ₈ is then multiplied by -1 signal Q by a second pattern generation unit 12 to be an even number (S _10), and stores the signal of the second pattern generation unit 12 to the register 13 (S _6).

For example, as shown in FIG. 4C, signal points P ₃ ,
It is also possible to make it easier to detect the frequency error by outputting the same signals I and Q at P ₄ without moving even if a clock is input respectively. In order to detect the clock timing from the above-described preamble signal according to the present invention, generally, the I signal and the Q signal are obtained, and (| I | ^x
+ | Q | ^y ) ^z = P (x, y, and z are real numbers that are not zero) may be used to extract the clock timing from the change state of P. Further, it is detected that the I signal and the Q signal both sign-invert during the symbol interval, and P = (| I |
^{By obtaining} the minimum point of ^x + | Q | ^y ) ^z , even when the carrier frequency deviation is large, it is possible to obtain more accurately than simply obtaining the zero-cross point. Alternatively, the clock timing may be determined from the average value, the maximum value, the minimum value, the variance, etc. by statistically processing the value of P at each point by dividing the intervals between the symbols.

[0020]

As described above, according to the present invention, due to the existence of the pattern in which the in-phase signal I and the quadrature signal Q are simultaneously inverted, there is a change passing through the origin on the IQ plane, and the clock extraction is easy. . In addition, there is also a pattern in which only one of the in-phase signal I and the quadrature signal Q is inverted, and it moves parallel to the I-axis or the Q-axis on the IQ plane, and it is easy to detect the frequency error and even if the frequency error is relatively large The clock can be easily detected.

[Brief description of drawings]

FIG. 1 is a functional configuration block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a generation processing procedure of an example of a preamble signal according to the present invention.

FIG. 3 is a diagram showing an example of a preamble signal generated according to the present invention.

FIG. 4 is a diagram showing a moving state of a preamble signal generated according to the present invention on an IQ plane.

5 is an instantaneous power of the preamble signal generated in FIG.
The figure which shows the difference of the thing which shifted 1 symbol, and the thing which does not shift, respectively.

FIG. 6 is a flowchart showing a generation processing procedure of another example of the preamble signal according to the present invention.

FIG. 7 is a flowchart showing a preamble signal generation processing procedure of still another example.

Claims (5)

[Claims] 1. A first pattern generating means for generating a signal obtained by inverting both an in-phase signal and a quadrature signal of a QPSK symbol value; and a signal for inverting one of the in-phase signal and the quadrature signal, and Second pattern generating means for alternating the inverted signal every r times; generating the signal m times by the first pattern generating means; and generating the signal n times by the second pattern generating means. A QPSK preamble signal generator comprising: repeating means; 2. The second pattern generating means generates a signal which is the signal obtained by inverting one of the in-phase signal and the quadrature signal, and a signal which is not inverted by both signals, and these three signals are generated every r times. The QPSK preamble signal generator according to claim 1, characterized in that 3. The QPSK preamble signal generator according to claim 1 or 2, wherein each of said m and n is 1. 4. The second pattern generating means includes an inversion signal of the in-phase signal and an inversion signal of the quadrature signal,
3. The QPSK preamble signal generator according to claim 2, wherein the QPSK preamble signal generator is means for randomly altering and generating a signal that does not invert both of the signals. 5. A first pattern generating means for generating a signal obtained by inverting both an in-phase signal and a quadrature signal of a QPSK symbol value; and a signal for inverting one of the in-phase signal and the quadrature signal, and A second pattern generating means for alternating the inversion every r times; and means for randomly switching between the generation by the first pattern generating means and the generation by the second pattern generating means. QPSK preamble signal generator.