JPH07183369A - Method for forming trench isolation region - Google Patents
Method for forming trench isolation regionInfo
- Publication number
- JPH07183369A JPH07183369A JP34657293A JP34657293A JPH07183369A JP H07183369 A JPH07183369 A JP H07183369A JP 34657293 A JP34657293 A JP 34657293A JP 34657293 A JP34657293 A JP 34657293A JP H07183369 A JPH07183369 A JP H07183369A
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- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor substrate
- polishing
- mechanical polishing
- isolation region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に用いられ
る素子分離の形成方法であって、特にはトレンチ素子分
離領域の形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming element isolation used in a semiconductor device, and more particularly to a method for forming a trench element isolation region.
【０００２】[0002]
【従来の技術】半導体装置の素子分離領域をトレンチ素
子分離で形成する方法は、まず、半導体基体に溝を形成
した後、その溝の内部とともに当該半導体基体の表面上
に絶縁膜を成膜する。その後、絶縁膜の表面側を除去し
て溝の内部に絶縁膜を残してトレンチ素子分離領域を形
成する。上記絶縁膜の除去方法は、機械的研磨および化
学的機械研磨のいづれか一方によって行われている。2. Description of the Related Art In a method of forming an element isolation region of a semiconductor device by trench element isolation, a groove is first formed in a semiconductor substrate, and then an insulating film is formed inside the groove and on the surface of the semiconductor substrate. . Then, the surface side of the insulating film is removed and the insulating film is left inside the trench to form a trench element isolation region. The method of removing the insulating film is performed by either mechanical polishing or chemical mechanical polishing.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、機械的
研磨で半導体基体が露出するまで絶縁膜を除去した場合
には、図４に示すように、半導体基体４１および当該半
導体基体４１に形成した複数の溝４２に埋め込まれた絶
縁膜４３の各研磨面の表層に加工変質層４４が形成され
る。さらに半導体基体４１の表層にも加工変質層４５が
形成される。このため、絶縁膜４３をトレンチ素子分離
領域とした場合には、その耐圧は低くなる。また半導体
基体４１を素子形成領域とした場合には、例えばリーク
電流が多くなる。However, when the insulating film is removed by mechanical polishing until the semiconductor substrate is exposed, as shown in FIG. 4, the semiconductor substrate 41 and a plurality of semiconductor substrates formed on the semiconductor substrate 41 are removed. A work-affected layer 44 is formed on the surface layer of each polished surface of the insulating film 43 embedded in the groove 42. Further, the work-affected layer 45 is also formed on the surface layer of the semiconductor substrate 41. Therefore, when the insulating film 43 is used as the trench element isolation region, the breakdown voltage becomes low. Further, when the semiconductor substrate 41 is used as the element formation region, for example, the leak current increases.
【０００４】また化学的機械研磨を行った場合には、研
磨剤（図示せず）と絶縁膜の被研磨面との化学反応によ
って、当該絶縁膜は等方的にエッチングされる。このた
め、図５に示すように、溝幅ｗ１のような狭い溝５２ａ
（例えばｗ１＝１μｍ程度）に絶縁膜５３が半導体基体
５１とほぼ同等の高さに埋め込まれるように研磨した場
合には、溝幅ｗ２のような広い溝５２ｂ（例えばｗ２＝
１０μｍ程度）に埋め込まれる絶縁膜５３の膜厚ｄは薄
くなり過ぎる。また半導体基体５１の素子形成領域５４
上に絶縁膜５３が残らないように研磨すると、溝５２
ａ，５２ｂの各内部の絶縁膜５３の膜厚はさらに薄くな
る。このように、半導体基体５１よりも高さが低い絶縁
膜５３をトレンチ素子分離領域として用いた場合には、
素子分離機能が十分に働かなくなる。このため、そのよ
うな絶縁膜５３をトレンチ素子分離領域とすることはで
きない。When chemical mechanical polishing is performed, the insulating film is isotropically etched by a chemical reaction between a polishing agent (not shown) and the surface to be polished of the insulating film. Therefore, as shown in FIG. 5, a narrow groove 52a having a groove width w1 is formed.
When the insulating film 53 is polished so as to be embedded in the semiconductor substrate 51 at a height substantially equal to that of the semiconductor substrate 51 (for example, w1 = 1 μm), a wide groove 52b such as a groove width w2 (for example, w2 =
The film thickness d of the insulating film 53 embedded to about 10 μm) becomes too thin. Further, the element formation region 54 of the semiconductor substrate 51
When the polishing is performed so that the insulating film 53 does not remain on the upper surface of the groove 52,
The film thickness of the insulating film 53 inside each of a and 52b is further reduced. As described above, when the insulating film 53 having a height lower than that of the semiconductor substrate 51 is used as the trench element isolation region,
The element isolation function does not work sufficiently. Therefore, such an insulating film 53 cannot be used as a trench element isolation region.
【０００５】本発明は、加工変質層を残さずにトレンチ
素子分離領域を形成するのに優れたトレンチ素子分離領
域の形成方法を提供することを目的とする。An object of the present invention is to provide a method for forming a trench element isolation region which is excellent in forming the trench element isolation region without leaving a work-affected layer.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するためになされたトレンチ素子分離領域の形成方法
である。すなわち、第１工程では、素子分離領域を形成
しようとする半導体基体の領域に溝を形成した後、その
溝の内部を含む半導体基体の表面に絶縁膜を成膜する。
次いで第２工程で、機械的研磨によって、半導体基体の
表面が露出しない状態で絶縁膜の表面が平坦面になるま
でその絶縁膜を研磨する。続いて第３工程で、ウェット
エッチングによって、絶縁膜の表面側を半導体基体の表
面が露出するまでエッチングする。その後第４工程で、
化学的機械研磨によって、半導体基体の表面側を研磨す
る。SUMMARY OF THE INVENTION The present invention is a method for forming a trench element isolation region, which has been made to achieve the above object. That is, in the first step, after forming a groove in the region of the semiconductor substrate where the element isolation region is to be formed, an insulating film is formed on the surface of the semiconductor substrate including the inside of the groove.
Then, in a second step, the insulating film is polished by mechanical polishing until the surface of the insulating film becomes a flat surface without exposing the surface of the semiconductor substrate. Then, in a third step, the surface side of the insulating film is etched by wet etching until the surface of the semiconductor substrate is exposed. Then in the fourth step,
The surface side of the semiconductor substrate is polished by chemical mechanical polishing.
【０００７】あるいは、上記第３工程では、半導体基体
と絶縁膜との研磨速度がほぼ同一になるアルカリ性の研
磨剤を用いた化学的機械研磨によって、絶縁膜の表面側
と半導体基体の表面側とを研磨してもよい。または、絶
縁膜に対してエッチング性を有する研磨剤を用いた化学
的機械研磨によって、絶縁膜の表面側を半導体基体の表
面が露出するまで研磨してもよい。Alternatively, in the third step, the surface side of the insulating film and the surface side of the semiconductor substrate are subjected to chemical mechanical polishing using an alkaline polishing agent which makes the polishing rates of the semiconductor substrate and the insulating film substantially the same. May be polished. Alternatively, the surface side of the insulating film may be polished until the surface of the semiconductor substrate is exposed by chemical mechanical polishing using a polishing agent having an etching property with respect to the insulating film.
【０００８】[0008]
【作用】上記トレンチ素子分離領域の形成方法では、機
械的研磨によって、半導体基体の表面が露出しない状態
で絶縁膜の表面が平坦面になるまでその絶縁膜を研磨す
ることから、絶縁膜の表面は平坦に形成される。したが
って、溝内に埋め込まれる絶縁膜の膜厚は、溝幅によら
ず均一になる。そしてウェットエッチングによって、絶
縁膜の表面側を半導体基体の表面が露出するまでエッチ
ングすることから、新たな加工変質層を形成することな
く絶縁膜の表層に形成されている加工変質層は除去され
る。その際、半導体基体の表面には加工変質層が形成さ
れない。さらに化学的機械研磨によって、半導体基体の
表面側を研磨することから、半導体基体の表面は絶縁膜
の表面の高さよりも低くなる。その際に、半導体基体お
よび絶縁膜の各研磨面側の表層には加工変質層が形成さ
れない。In the method for forming the trench element isolation region, the insulating film is polished by mechanical polishing until the surface of the semiconductor film becomes a flat surface without exposing the surface of the semiconductor substrate. Are formed flat. Therefore, the film thickness of the insulating film embedded in the groove is uniform regardless of the groove width. Then, since the surface side of the insulating film is etched by wet etching until the surface of the semiconductor substrate is exposed, the work-affected layer formed on the surface layer of the insulation film is removed without forming a new work-affected layer. . At this time, no work-affected layer is formed on the surface of the semiconductor substrate. Further, since the surface side of the semiconductor substrate is polished by chemical mechanical polishing, the surface of the semiconductor substrate becomes lower than the height of the surface of the insulating film. At that time, the work-affected layer is not formed on the surface layer of each of the semiconductor substrate and the insulating film on the polished surface side.
【０００９】あるいは、上記ウェットエッチングの代わ
りにアルカリ性の研磨剤を用いた化学的機械研磨によっ
て、絶縁膜の表面側と半導体基体の表面側とを研磨する
ことから、上記同様に、新たな加工変質層を形成するこ
となく絶縁膜の表層に形成されている加工変質層は除去
される。その際、半導体基体の表面には加工変質層が形
成されない。または、上記ウェットエッチングの代わり
に絶縁膜に対してエッチング性を有する研磨剤を用いた
化学的機械研磨によって、絶縁膜の表面側を半導体基体
の表面が露出するまで研磨しても、上記同様の作用が得
られる。Alternatively, instead of the above wet etching, the surface side of the insulating film and the surface side of the semiconductor substrate are polished by chemical mechanical polishing using an alkaline polishing agent, so that a new process alteration is performed in the same manner as above. The work-affected layer formed on the surface layer of the insulating film is removed without forming a layer. At this time, no work-affected layer is formed on the surface of the semiconductor substrate. Alternatively, instead of the above wet etching, the surface side of the insulating film may be polished until the surface of the semiconductor substrate is exposed by chemical mechanical polishing using a polishing agent having an etching property with respect to the insulating film. The action is obtained.
【００１０】[0010]
【実施例】第１発明の実施例を図１の形成工程図により
説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to the process chart of FIG.
【００１１】図１の（１）に示すように、第１の工程で
は、リソグラフィー技術とエッチングとによって、半導
体基体１１の素子分離領域を形成しようとする領域に溝
１２を形成する。その後、成膜技術〔例えば、熱ＣＶＤ
法，ＥＣＲ（Electron Cycrotron Resonance）プラズ
マＣＶＤ法等〕によって、上記溝１２の内部を含む上記
半導体基体１１の表面に絶縁膜１３を成膜する。上記半
導体基体１１は、例えばシリコンからなる。上記絶縁膜
１３は、絶縁性に優れた材料として、例えば酸化シリコ
ン（ＳｉＯ2 ）で形成されている。As shown in FIG. 1A, in the first step, a groove 12 is formed in a region of the semiconductor substrate 11 where an element isolation region is to be formed by a lithography technique and etching. After that, a film forming technique (for example, thermal CVD
Method, ECR (Electron Cycrotron Resonance) plasma CVD method, etc.], an insulating film 13 is formed on the surface of the semiconductor substrate 11 including the inside of the groove 12. The semiconductor substrate 11 is made of silicon, for example. The insulating film 13 is formed of, for example, silicon oxide (SiO 2 ) as a material having excellent insulating properties.
【００１２】次いで図１の（２）の示す第２工程を行
う。この工程では、機械的研磨によって、上記半導体基
体１１の表面が露出しない状態で上記絶縁膜１３の表面
が平坦面になるまで研磨する。このとき、当該絶縁膜１
３の表層には加工変質層２１が形成される。Next, the second step shown in FIG. 1B is performed. In this step, mechanical polishing is performed until the surface of the insulating film 13 becomes a flat surface without exposing the surface of the semiconductor substrate 11. At this time, the insulating film 1
A work-affected layer 21 is formed on the surface layer of No. 3.
【００１３】上記機械的研磨では、例えば、研磨砥粒に
は粒径が３００ｎｍ〜６００ｎｍ程度の酸化セリウム
（ＣｅＯ2 ）を用い、研磨液には純水（ｐＨ＝７．０）
を用いる。またポリシングクロスには、硬度としてＡｓ
ｋｅｒ−Ｃが８０以上の比較的硬質なものを用いる。上
記研磨砥粒には、１次粒径が２０ｎｍ〜６０ｎｍ程度で
２次粒径が２００ｎｍ〜３００ｎｍ程度のフュームドシ
リカを用いてもよい。この場合の研磨液は、純水または
アルカリ性溶液（例えばｐＨ＝７〜１０程度）を用い
る。または、１次粒径が８０ｎｍ〜９０ｎｍ程度で２次
粒径が２００ｎｍ〜３００ｎｍ程度のコロイダルシリカ
を用いてもよい。この場合の研磨液は、純水またはアル
カリ性溶液（例えばｐＨ＝７〜１０程度）を用いる。In the mechanical polishing, for example, cerium oxide (CeO 2 ) having a particle size of about 300 nm to 600 nm is used as the polishing abrasive grains, and pure water (pH = 7.0) is used as the polishing liquid.
To use. The polishing cloth has a hardness of As.
A relatively hard material having a ker-C of 80 or more is used. Fumed silica having a primary particle size of about 20 nm to 60 nm and a secondary particle size of about 200 nm to 300 nm may be used as the polishing abrasive particles. As the polishing liquid in this case, pure water or an alkaline solution (for example, pH = about 7 to 10) is used. Alternatively, colloidal silica having a primary particle size of about 80 nm to 90 nm and a secondary particle size of about 200 nm to 300 nm may be used. As the polishing liquid in this case, pure water or an alkaline solution (for example, pH = about 7 to 10) is used.
【００１４】続いて図１の（３）に示す第３工程を行
う。この工程では、ウェットエッチングによって、２点
鎖線で示す部分の上記絶縁膜１３の表面側を上記加工変
質層２１（１点鎖線で示す部分）とともに上記半導体基
体１１の表面が露出するまでエッチングする。Subsequently, the third step shown in FIG. 1C is performed. In this step, wet etching is performed to etch the surface side of the insulating film 13 in the portion indicated by the two-dot chain line together with the work-affected layer 21 (the portion indicated by the one-dot chain line) until the surface of the semiconductor substrate 11 is exposed.
【００１５】上記エッチング液には、例えば０．数％〜
１０％程度の濃度範囲のフッ酸溶液を用いる。また上記
絶縁膜１３が酸化シリコン以外の材料で形成されている
場合には、半導体基体１１とのエッチング選択性が高い
エッチング液によって、上記ウェットエッチングを行
う。The above etching solution contains, for example, 0. number%~
A hydrofluoric acid solution having a concentration range of about 10% is used. When the insulating film 13 is made of a material other than silicon oxide, the wet etching is performed with an etching solution having a high etching selectivity with respect to the semiconductor substrate 11.
【００１６】その後図１の（４）に示す第４工程を行
う。この工程では、化学的機械研磨によって、２点鎖線
で示す部分の上記半導体基体１１の表面側を研磨する。
このとき、１点鎖線で示す部分の絶縁膜１３も研磨され
る。そして溝１２の内部に埋め込まれた絶縁膜（１３）
でトレンチ素子分離領域１４を形成する。Thereafter, the fourth step shown in FIG. 1 (4) is performed. In this step, the surface side of the semiconductor substrate 11 at the portion indicated by the chain double-dashed line is polished by chemical mechanical polishing.
At this time, the portion of the insulating film 13 indicated by the alternate long and short dash line is also polished. The insulating film (13) embedded in the groove 12
Then, the trench element isolation region 14 is formed.
【００１７】上記化学的機械研磨では、例えば、研磨砥
粒には粒径が１０ｎｍ〜２０ｎｍ程度のコロイダルシリ
カを用い、研磨液には半導体基体１１に対してエッチン
グ性を有するアルカリ性溶液（例えばｐＨ＝１０〜１１
程度）を用いる。このアルカリ性溶液としては、例えば
アンモニア水を用いる。In the chemical mechanical polishing, for example, colloidal silica having a particle size of about 10 nm to 20 nm is used as the polishing abrasive grains, and an alkaline solution having an etching property with respect to the semiconductor substrate 11 (for example, pH =) is used as the polishing liquid. 10-11
Degree) is used. Ammonia water, for example, is used as the alkaline solution.
【００１８】上記図１で説明した実施例では、機械的研
磨によって、半導体基体１１の表面が露出しない状態で
絶縁膜１３の表面が平坦面になるまでその絶縁膜１３を
研磨することにから、絶縁膜１３の表面は平坦に形成さ
れる。したがって、溝１２内に埋め込まれる絶縁膜１３
の膜厚は、溝１２の幅によらず均一になる。In the embodiment described with reference to FIG. 1, the insulating film 13 is polished by mechanical polishing until the surface of the insulating film 13 becomes flat without exposing the surface of the semiconductor substrate 11. The surface of the insulating film 13 is formed flat. Therefore, the insulating film 13 embedded in the groove 12
Has a uniform film thickness regardless of the width of the groove 12.
【００１９】そしてウェットエッチングによって、絶縁
膜１３の表面側を半導体基体１１の表面が露出するまで
エッチングすることから、新たな加工変質層を形成する
ことなく絶縁膜１３の表層に形成されている加工変質層
２１は除去される。その際、半導体基体１１の表面には
加工変質層が形成されない。また、溝１２の内部に埋め
込まれている絶縁膜１３の膜厚はほぼ均一な状態が保た
れる。Since the surface side of the insulating film 13 is etched by wet etching until the surface of the semiconductor substrate 11 is exposed, the process formed on the surface layer of the insulating film 13 without forming a new process-affected layer. The altered layer 21 is removed. At that time, no work-affected layer is formed on the surface of the semiconductor substrate 11. Further, the film thickness of the insulating film 13 embedded in the groove 12 is kept substantially uniform.
【００２０】さらに化学的機械研磨によって、半導体基
体１１の表面側を研磨することから、半導体基体１１の
表面は絶縁膜１３の表面の高さよりも低くなる。その際
に、半導体基体１１および絶縁膜１３の各研磨面側の表
層には加工変質層が形成されない。Further, since the surface side of the semiconductor substrate 11 is polished by chemical mechanical polishing, the surface of the semiconductor substrate 11 becomes lower than the height of the surface of the insulating film 13. At this time, no work-affected layer is formed on the surface layers of the semiconductor substrate 11 and the insulating film 13 on the polished surface side.
【００２１】次に第２発明の実施例を図２の形成工程図
により説明する。なお、第１，第２工程は、上記図１に
よって説明したのと同様なのでここでの説明は省略す
る。また上記図１で説明したのと同様の構成部品には同
一符号を付す。Next, an embodiment of the second invention will be explained with reference to the process chart of FIG. Since the first and second steps are the same as those described with reference to FIG. 1, the description thereof is omitted here. The same components as those described with reference to FIG. 1 are designated by the same reference numerals.
【００２２】上記図１の（１），（２）で説明したのと
同様にして、第１，第２工程を行った後、図２の（１）
に示すように、第３工程を行う。この工程では、半導体
基体１１と絶縁膜１３との研磨速度がほぼ同一になるア
ルカリ性の研磨剤を用いた化学的機械研磨によって、２
点鎖線で示す部分の絶縁膜１３の表面側をその表層に形
成されている加工変質層２１（１点鎖線で示す部分）と
ともに研磨する。さらに、絶縁膜１３の表層と破線で示
す部分の半導体基体１１の表層とを研磨して平坦化を行
う。After carrying out the first and second steps in the same manner as described above with reference to (1) and (2) of FIG. 1, (1) of FIG.
As shown in, the third step is performed. In this step, the chemical mechanical polishing using an alkaline polishing agent, which makes the polishing rates of the semiconductor substrate 11 and the insulating film 13 approximately the same, is performed.
The surface side of the insulating film 13 indicated by the dotted chain line is polished together with the work-affected layer 21 (the portion indicated by the dashed line) formed on the surface layer thereof. Further, the surface layer of the insulating film 13 and the surface layer of the semiconductor substrate 11 in the portion shown by the broken line are polished to be planarized.
【００２３】上記研磨剤には、例えば１次砥粒の粒径が
３０ｎｍ〜４０ｎｍ程度のコロイダルシリカを研磨液と
なるアンモニア水溶液（例えばｐＨ＝１０〜１１）に分
散させたものを用いる。上記研磨液には、半導体基体１
１と絶縁膜１３とをエッチングする溶液であればよく、
例えば水酸化カリウム水溶液，水酸化バリウム水溶液等
を用いてもよい。As the abrasive, for example, colloidal silica having a primary abrasive grain size of about 30 nm to 40 nm dispersed in an aqueous ammonia solution (for example, pH = 10 to 11) serving as a polishing liquid is used. The polishing liquid contains the semiconductor substrate 1
1 as long as it is a solution for etching 1 and the insulating film 13,
For example, a potassium hydroxide aqueous solution, a barium hydroxide aqueous solution or the like may be used.
【００２４】その後図２の（２）に示す第４工程を行
う。この工程では、上記図１の（４）で説明したのと同
様の化学的機械研磨によって、２点鎖線で示す部分の上
記半導体基体１１の表面側を研磨する。このとき、１点
鎖線で示す部分の絶縁膜１３も研磨される。そして溝１
２の内部に埋め込まれた絶縁膜（１３）でトレンチ素子
分離領域１４を形成する。Thereafter, a fourth step shown in FIG. 2B is performed. In this step, the surface side of the semiconductor substrate 11 in the portion indicated by the chain double-dashed line is polished by the same chemical mechanical polishing as described in (4) of FIG. At this time, the portion of the insulating film 13 indicated by the chain line is also polished. And groove 1
The trench element isolation region 14 is formed by the insulating film (13) embedded in the inside of 2.
【００２５】上記図２で説明した実施例では、半導体基
体１１と絶縁膜１３との研磨速度がほぼ同一になるアル
カリ性の研磨剤を用いた化学的機械研磨によって、絶縁
膜１３の表面側と半導体基体１１の表面側とを研磨する
ことから、新たな加工変質層を形成することなく絶縁膜
１３の表層に形成されている加工変質層２１は除去され
る。そして上記アルカリ性の研磨剤を用いた化学的機械
研磨が進行しても、半導体基体１１の表面や絶縁膜１３
の表面には加工変質層が形成されない。また、溝１２の
内部に埋め込まれている絶縁膜１３の膜厚はほぼ均一な
状態が保たれる。In the embodiment described with reference to FIG. 2, the semiconductor substrate 11 and the insulating film 13 are chemically and mechanically polished using an alkaline polishing agent so that the polishing rates of the semiconductor substrate 11 and the insulating film 13 are almost the same. Since the surface side of the substrate 11 is polished, the work-affected layer 21 formed on the surface layer of the insulating film 13 is removed without forming a new work-affected layer. Even if the chemical mechanical polishing using the alkaline abrasive progresses, the surface of the semiconductor substrate 11 and the insulating film 13
No work-affected layer is formed on the surface of. Further, the film thickness of the insulating film 13 embedded in the groove 12 is kept substantially uniform.
【００２６】次に第３発明の実施例を図３の形成工程図
により説明する。なお、第１，第２工程は、上記図１に
よって説明したのと同様なのでここでの説明は省略す
る。また上記図１で説明したのと同様の構成部品には同
一符号を付す。Next, an embodiment of the third invention will be described with reference to the process chart of FIG. Since the first and second steps are the same as those described with reference to FIG. 1, the description thereof is omitted here. The same components as those described with reference to FIG. 1 are designated by the same reference numerals.
【００２７】上記図１の（１），（２）で説明したのと
同様にして、第１，第２工程を行った後、図３の（１）
に示すように、第３工程を行う。この工程では、絶縁膜
１３に対してエッチング性を有する研磨剤を用いた化学
的機械研磨によって、２点鎖線で示す部分の絶縁膜１３
の表面側をその表層に形成されている加工変質層２１
（１点鎖線で示す部分）とともに半導体基体１１の表層
が露出するまで研磨を行う。上記研磨剤には、上記図２
の（１）で説明したのと同様のものを用いる。After carrying out the first and second steps in the same manner as described in (1) and (2) of FIG. 1 above, (1) of FIG.
As shown in, the third step is performed. In this step, chemical mechanical polishing is performed on the insulating film 13 using a polishing agent having an etching property, so that the insulating film 13 in the portion indicated by a two-dot chain line
Of the work-affected layer 21 with the surface side of the
The polishing is performed until the surface layer of the semiconductor substrate 11 is exposed together with (the portion indicated by the one-dot chain line). The above-mentioned abrasive has the above-mentioned FIG.
The same one as described in (1) of is used.
【００２８】その後図３の（２）に示す第４工程を行
う。この工程では、上記図１の（４）で説明したのと同
様の化学的機械研磨によって、２点鎖線で示す部分の上
記半導体基体１１の表面側を研磨する。このとき、１点
鎖線で示す部分の絶縁膜１３も研磨される。そして溝１
２の内部に埋め込まれた絶縁膜（１３）でトレンチ素子
分離領域１４を形成する。Thereafter, the fourth step shown in FIG. 3B is performed. In this step, the surface side of the semiconductor substrate 11 in the portion indicated by the chain double-dashed line is polished by the same chemical mechanical polishing as described in (4) of FIG. At this time, the portion of the insulating film 13 indicated by the chain line is also polished. And groove 1
The trench element isolation region 14 is formed by the insulating film (13) embedded in the inside of 2.
【００２９】上記図３で説明した実施例では、絶縁膜１
３に対してエッチング性を有する研磨剤を用いた化学的
機械研磨によって、絶縁膜１３の表面側と半導体基体１
１の表面側とを研磨することから、新たな加工変質層を
形成することなく絶縁膜１３の表層に形成されている加
工変質層２１は除去される。しかも、上記半導体基体１
１の表面や上記絶縁膜１３の表面には新たな加工変質層
は形成されない。また、溝１２の内部に埋め込まれてい
る絶縁膜１３の膜厚はほぼ均一な状態が保たれる。In the embodiment described with reference to FIG. 3, the insulating film 1 is used.
By chemical mechanical polishing using a polishing agent having an etching property with respect to 3, the surface side of the insulating film 13 and the semiconductor substrate 1
Since the surface of No. 1 is polished, the work-affected layer 21 formed on the surface layer of the insulating film 13 is removed without forming a new work-affected layer. Moreover, the semiconductor substrate 1
No new work-affected layer is formed on the surface of No. 1 or the surface of the insulating film 13. Further, the film thickness of the insulating film 13 embedded in the groove 12 is kept substantially uniform.
【００３０】[0030]
【発明の効果】以上、説明したように本発明によれば、
第２工程の機械的研磨によって絶縁膜を研磨するので、
絶縁膜の表面を平坦に形成することができる。このた
め、次の第３工程のウェットエッチングによって半導体
基体表面が露出するまで絶縁膜をエッチングしても、溝
内の絶縁膜の膜厚はほぼ均一になる。しかも新たな加工
変質層を形成することなく加工変質層を除去することが
できる。また、上記第３工程をアルカリ性の研磨剤を用
いた化学的機械研磨、さらには絶縁膜に対してエッチン
グ性を有する研磨剤を用いた化学的機械研磨で行って
も、上記同様の効果が得られる。さらに第４工程の化学
的機械研磨によって、半導体基体の表面側を研磨するの
で、研磨面側に加工変質層を形成することなく半導体基
体を絶縁膜よりも低い状態に研磨することができる。し
たがって、絶縁膜で形成されるトレンチ素子分離領域
は、加工変質層が無く、十分な膜厚が確保されるので、
その絶縁耐圧の向上を図ることができる。As described above, according to the present invention,
Since the insulating film is polished by the mechanical polishing in the second step,
The surface of the insulating film can be formed flat. Therefore, even if the insulating film is etched until the surface of the semiconductor substrate is exposed by wet etching in the next third step, the film thickness of the insulating film in the groove becomes substantially uniform. Moreover, the work-affected layer can be removed without forming a new work-affected layer. Even when the third step is performed by chemical mechanical polishing using an alkaline abrasive, and further chemical mechanical polishing using an abrasive having an etching property with respect to the insulating film, the same effect as described above can be obtained. To be Further, since the surface side of the semiconductor substrate is polished by the chemical mechanical polishing in the fourth step, the semiconductor substrate can be polished to a state lower than the insulating film without forming a work-affected layer on the polished surface side. Therefore, since the trench element isolation region formed of the insulating film has no process-affected layer and a sufficient film thickness is secured,
The breakdown voltage can be improved.
【図１】第１発明の実施例の形成工程図である。FIG. 1 is a process drawing of an embodiment of the first invention.
【図２】第２発明の実施例の形成工程図である。FIG. 2 is a process drawing of an embodiment of the second invention.
【図３】第３発明の実施例の形成工程図である。FIG. 3 is a process drawing of an embodiment of the third invention.
【図４】第１の課題の説明図である。FIG. 4 is an explanatory diagram of a first problem.
【図５】第２の課題の説明図である。FIG. 5 is an explanatory diagram of a second problem.
１１ 半導体基体 １２ 溝 １３ 絶縁膜 １４ トレンチ素子分離領域 11 semiconductor substrate 12 groove 13 insulating film 14 trench element isolation region
Claims (3)
基体の領域に溝を形成した後、前記溝の内部を含む前記
半導体基体の表面に絶縁膜を成膜する第１工程と、 機械的研磨によって、前記半導体基体の表面が露出しな
い状態で当該絶縁膜の表面が平坦面になるまで当該絶縁
膜を研磨する第２工程と、 ウェットエッチングによって、前記絶縁膜の表面側を前
記半導体基体の表面が露出するまでエッチングする第３
工程と、 化学的機械研磨によって、前記半導体基体の表面側を研
磨する第４工程とからなるトレンチ素子分離領域の形成
方法。1. A first step of forming an insulating film on a surface of the semiconductor substrate including the inside of the groove after forming a groove in a region of the semiconductor substrate where an element isolation region is to be formed, and mechanical polishing. A second step of polishing the insulating film until the surface of the insulating film becomes a flat surface without exposing the surface of the semiconductor substrate, and the surface side of the insulating film is wet-etched to the surface of the semiconductor substrate. Third to etch until exposed
A method of forming a trench element isolation region, which comprises a step and a fourth step of polishing the surface side of the semiconductor substrate by chemical mechanical polishing.
基体の領域に溝を形成した後、前記溝の内部を含む前記
半導体基体の表面に絶縁膜を成膜する第１工程と、 機械的研磨によって、前記半導体基体の表面が露出しな
い状態で当該絶縁膜の表面が平坦面になるまで当該絶縁
膜を研磨する第２工程と、 前記半導体基体と前記絶縁膜との研磨速度がほぼ同一の
アルカリ性の研磨剤を用いた化学的機械研磨によって、
前記絶縁膜の表面側と前記半導体基体の表面側とを研磨
する第３工程と、 化学的機械研磨によって、前記半導体基体の表面側を研
磨する第４工程とからなるトレンチ素子分離領域の形成
方法。2. A first step of forming an insulating film on a surface of the semiconductor substrate including the inside of the groove after forming a groove in a region of the semiconductor substrate where an element isolation region is to be formed, and mechanical polishing. The second step of polishing the insulating film until the surface of the insulating film becomes a flat surface without exposing the surface of the semiconductor substrate, and the alkaline rate of polishing the semiconductor substrate and the insulating film is substantially the same. By chemical mechanical polishing with the abrasive of
Method for forming trench element isolation region, which comprises a third step of polishing the surface side of the insulating film and the surface side of the semiconductor substrate, and a fourth step of polishing the surface side of the semiconductor substrate by chemical mechanical polishing .
基体の領域に溝を形成した後、前記溝の内部を含む前記
半導体基体の表面に絶縁膜を成膜する第１工程と、 機械的研磨によって、前記半導体基体の表面が露出しな
い状態で当該絶縁膜の表面が平坦面になるまで当該絶縁
膜を研磨する第２工程と、 前記絶縁膜に対してエッチング性を有する研磨剤を用い
た化学的機械研磨によって、前記絶縁膜の表面側を前記
半導体基体の表面が露出するまで研磨する第３工程と、 化学的機械研磨によって、前記半導体基体の表面側を研
磨する第４工程とからなるトレンチ素子分離領域の形成
方法。3. A first step of forming an insulating film on the surface of the semiconductor substrate including the inside of the groove after forming the groove in the region of the semiconductor substrate where the element isolation region is to be formed, and mechanical polishing. A second step of polishing the insulating film until the surface of the insulating film becomes a flat surface without exposing the surface of the semiconductor substrate, and a chemical using an abrasive having an etching property with respect to the insulating film. Trench including a third step of polishing the surface side of the insulating film by mechanical mechanical polishing until the surface of the semiconductor substrate is exposed, and a fourth step of polishing the surface side of the semiconductor substrate by chemical mechanical polishing Method for forming element isolation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34657293A JP3271111B2 (en) | 1993-12-22 | 1993-12-22 | Method of forming trench element isolation region |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34657293A JP3271111B2 (en) | 1993-12-22 | 1993-12-22 | Method of forming trench element isolation region |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07183369A true JPH07183369A (en) | 1995-07-21 |
| JP3271111B2 JP3271111B2 (en) | 2002-04-02 |
Family
ID=18384337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34657293A Expired - Fee Related JP3271111B2 (en) | 1993-12-22 | 1993-12-22 | Method of forming trench element isolation region |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3271111B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789792A (en) * | 1996-08-28 | 1998-08-04 | Mitsubishi Denki Kabushiki Kaisha | Isolation trench structures protruding above a substrate surface |
| KR100355872B1 (en) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | planarization method of semiconductor devices |
-
1993
- 1993-12-22 JP JP34657293A patent/JP3271111B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789792A (en) * | 1996-08-28 | 1998-08-04 | Mitsubishi Denki Kabushiki Kaisha | Isolation trench structures protruding above a substrate surface |
| KR100355872B1 (en) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | planarization method of semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3271111B2 (en) | 2002-04-02 |
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