JPH07183299A - Method for forming copper wirings - Google Patents

Method for forming copper wirings

Info

Publication number
JPH07183299A
JPH07183299A JP32498793A JP32498793A JPH07183299A JP H07183299 A JPH07183299 A JP H07183299A JP 32498793 A JP32498793 A JP 32498793A JP 32498793 A JP32498793 A JP 32498793A JP H07183299 A JPH07183299 A JP H07183299A
Authority
JP
Japan
Prior art keywords
film
copper
groove
etching
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32498793A
Other languages
Japanese (ja)
Inventor
Toshimi Hashimoto
敏己 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP32498793A priority Critical patent/JPH07183299A/en
Publication of JPH07183299A publication Critical patent/JPH07183299A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form fine copper wirings by embedding a copper film in a groove formed in an interlayer insulating film and etching back it. CONSTITUTION:A groove is formed on an SiO2 film 2 formed on a silicon substrate 1, and a copper film 4 is so deposited as to embed the groove. Then, chlorine plasma is formed in an etching chamber of a dry etching unit, the film 4 previously deposited in the plasma is exposed to react the film 4 with a copper chloride film 5 to a surface of the film 2. Then, the substrate 1 is transferred in a vacuum to an ashing chamber without exposing the reacted film 5 with the atmosphere, and heat treated. Then, the substrate 1 is again transferred to the etching chamber to etch back the film 5 by using a plasma by O2 gas or rare gas in the etching chamber, thereby forming copper wirings 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体集積回路の製造方
法に関し、特に銅配線の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for forming copper wiring.

【0002】[0002]

【従来の技術】半導体集積回路の微細化にともないアル
ミ配線のエレクトロマイグレーション、ストレスマイグ
レーション耐性の劣化が顕在化してきた。このため、従
来より、アルミにシリコンや銅などを添加したり、チタ
ンや窒化チタンの積層構造をとることでエレクトロマイ
グレーション、ストレスマイグレーション耐性を向上さ
せる方法が用いられてきた(吉川他 IEEE トラン
ザクション オン エレクトロン デバイス(TRAN
SACTIONS ON ELECTRON DEVI
CES)1993 40冊 2号 296ページ)。
2. Description of the Related Art With the miniaturization of semiconductor integrated circuits, electromigration of aluminum wiring and deterioration of stress migration resistance have become apparent. For this reason, conventionally, a method of improving resistance to electromigration and stress migration by adding silicon or copper to aluminum or taking a laminated structure of titanium or titanium nitride has been used (Yoshikawa et al. IEEE Transaction on Electron). Device (TRAN
SACTIONS ON ELECTRON DEVI
(CES) 1993 40, No. 2, 296).

【0003】一方、銅系材料は、高いマイグレーション
耐性と低い抵抗値を持つことから、次世代の半導体デバ
イスの配線材料として有望視されている。銅膜のドライ
エッチングには、塩素ガスを用いて銅の塩化物である塩
化銅を形成させる方法が用いられてきた(大野他 ジャ
パニーズ オブ ジャーナル アプライド フィジカル
ス(Jpn.J.Appl.Phys.)1989 2
8巻 L1070ページ)。しかしながら塩化銅は、蒸
気圧が低いため基板加熱を行いながらエッチングを行っ
てきた。
On the other hand, copper-based materials have high migration resistance and low resistance, and are therefore regarded as promising wiring materials for next-generation semiconductor devices. A method of forming copper chloride, which is a chloride of copper, using chlorine gas has been used for dry etching of a copper film (Ohno et al., Japanese of Journal Applied Physicals (Jpn. J. Appl. Phys.) 1989). Two
Volume 8, page L1070). However, since copper chloride has a low vapor pressure, it has been etched while heating the substrate.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上述し
た従来の技術では、銅膜のドライエッチングを行うため
に高温エッチング装置が必要になる。そして、高温によ
るドライエッチングを行うためフォトレジストの耐熱性
が問題となり、従来のフォトレジストに代わるエッチン
グマスクが必要となってきた。フォトレジストに代わる
エッチングマスクとしては、耐熱性の高いハードマスク
(SiO2 等)を用いた銅膜のエッチングが報告されて
いる。(ジー・シー・シュワルツ他 ジャーナル オブ
エレクトロケミカル ソサイエティー(J.Elec
trochem.Soc.)1983 130巻 17
77ページ)。しかしながら、工程数の増加やハードマ
スクと銅膜の密着性などの問題があった。
However, in the above-mentioned conventional technique, a high temperature etching apparatus is required to perform the dry etching of the copper film. Since the dry etching is performed at a high temperature, the heat resistance of the photoresist becomes a problem, and an etching mask that replaces the conventional photoresist has been required. As an etching mask that replaces the photoresist, etching of a copper film using a hard mask (SiO 2 or the like) having high heat resistance has been reported. (GC Schwartz et al. Journal of Electrochemical Society (J. Elec
trochem. Soc. ) 1983 130 Volume 17
(P. 77). However, there are problems such as an increase in the number of steps and adhesion between the hard mask and the copper film.

【0005】本発明の目的は、銅膜の微細加工を行わず
絶縁膜に溝を形成し銅膜を堆積させ溝以外の銅膜を塩素
プラズマを用いて塩化銅膜に反応させこの塩化銅膜をエ
ッチバックして銅配線を形成することにより、従来技術
を利用した半導体集積回路の製造方法を提供することに
ある。
An object of the present invention is to form a groove in an insulating film without finely processing the copper film, deposit the copper film, and react the copper film other than the groove with the copper chloride film by using chlorine plasma. It is intended to provide a method for manufacturing a semiconductor integrated circuit using a conventional technique by etching back to form a copper wiring.

【0006】[0006]

【課題を解決するための手段】本発明の方法では、まず
基板上に形成した絶縁膜に溝を形成し、溝を埋めつくす
様に銅膜を堆積する。次いで、ドライエッチング装置を
用いてエッチングチャンバー内に塩素プラズマを形成
し、この塩素プラズマ中に先に堆積させた銅膜を曝して
絶縁膜表面まで銅膜を塩化銅膜に反応させる。次いで、
反応させた塩化銅膜を大気に曝すこと無く基板を真空中
でアッシングチャンバーに搬送し、そこで基板を加熱処
理する。アッシングチャンバー内で加熱処理を行った
後、再びエッチングチャンバー内に基板を搬送し、エッ
チングチャンバー内でO2 ガスまたは希ガスによるプラ
ズマを用いて塩化銅膜のエッチバックを行い、銅配線を
形成する工程とを備えたものである。
According to the method of the present invention, first, a groove is formed in an insulating film formed on a substrate, and a copper film is deposited so as to fill the groove. Then, chlorine plasma is formed in the etching chamber using a dry etching apparatus, and the previously deposited copper film is exposed to this chlorine plasma so that the copper film reacts with the copper chloride film up to the surface of the insulating film. Then
The substrate is transferred to an ashing chamber in vacuum without exposing the reacted copper chloride film to the atmosphere, and the substrate is heat-treated there. After heat treatment is performed in the ashing chamber, the substrate is transported again into the etching chamber, and the copper chloride film is etched back using plasma of O 2 gas or rare gas in the etching chamber to form a copper wiring. And a process.

【0007】[0007]

【作用】本発明においては、層間絶縁膜上の配線となる
溝が埋め込まれるように銅膜を形成し、そして、塩素ガ
スプラズマに曝す工程により層間絶縁膜表面まで銅膜を
塩化銅膜に反応させ、基板加熱により塩化銅膜の温度を
上げた後、塩化銅膜をエッチバックすることにより、溝
に埋め込まれた銅膜が配線となる。
In the present invention, a copper film is formed so as to fill a groove to be a wiring on the interlayer insulating film, and the copper film reacts with the copper chloride film up to the surface of the interlayer insulating film by the step of exposing to chlorine gas plasma. Then, the temperature of the copper chloride film is raised by heating the substrate, and then the copper chloride film is etched back, whereby the copper film embedded in the groove becomes a wiring.

【0008】[0008]

【実施例】【Example】

実施例1 次に本発明について図面を用いて説明する。図1(a)
〜(d)は、本発明の一実施例を説明するための工程順
に示した半導体チップの断面図である。
Embodiment 1 Next, the present invention will be described with reference to the drawings. Figure 1 (a)
8D are cross-sectional views of the semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

【0009】まず図1(a)に示すように、シリコン基
板1を熱酸化して厚さ約500nmのSiO2 膜を形成
したのちリアクティブイオンエッチング(RIE法)に
より、所望の位置に配線となる溝を形成する。
First, as shown in FIG. 1A, a silicon substrate 1 is thermally oxidized to form a SiO 2 film having a thickness of about 500 nm, and then a wiring is formed at a desired position by reactive ion etching (RIE method). Forming a groove.

【0010】次に図1(b)に示すように、フォトレジ
スト膜3を剥離したあとスパッタ法または蒸着法または
CVD法の何れかを用いて全面に銅膜4を堆積して溝を
埋め込む。
Next, as shown in FIG. 1B, the photoresist film 3 is peeled off, and then a copper film 4 is deposited on the entire surface by any one of the sputtering method, the vapor deposition method and the CVD method to fill the groove.

【0011】次に図1(c)に示すように、銅膜4を室
温で塩素プラズマに曝して銅膜4と反応させる。反応さ
せる膜厚は、反応生成物である塩化銅膜5がSiO2
2の表面まで反応するように塩素プラズマへの暴露時間
を調節する。
Next, as shown in FIG. 1C, the copper film 4 is exposed to chlorine plasma at room temperature to react with the copper film 4. The film thickness to be reacted is adjusted by the exposure time to chlorine plasma so that the copper chloride film 5 as a reaction product reacts to the surface of the SiO 2 film 2.

【0012】次に図1(d)に示すように、反応させた
塩化銅膜5を大気に曝すことなくシリコン基板1をアッ
シングチャンバーに搬送し加熱を行なう。シリコン基板
1の加熱後、再びエッチングチャンバーにシリコン基板
を搬送し酸素ガスまたはアルゴンなどの希ガスプラズマ
を用いてエッチングを行い塩化銅膜5のエッチバックを
行ない、銅配線6を形成する。
Next, as shown in FIG. 1D, the silicon substrate 1 is transferred to an ashing chamber and heated without exposing the reacted copper chloride film 5 to the atmosphere. After heating the silicon substrate 1, the silicon substrate is again transported to the etching chamber and etched using oxygen gas or a rare gas plasma such as argon to etch back the copper chloride film 5 to form the copper wiring 6.

【0013】このように本実施例によれば、SiO2
2に形成した溝に銅膜を埋め込み反応させた塩化銅膜5
をエッチバックにより銅配線6を形成するため、従来の
ように銅膜3の微細加工を必要としない。
As described above, according to the present embodiment, the copper chloride film 5 in which the copper film is embedded in the groove formed in the SiO 2 film 2 and reacted
Since the copper wiring 6 is formed by etching back, the fine processing of the copper film 3 is not required unlike the conventional case.

【0014】実施例2 次に本発明について図面を用いて説明する。図2(a)
〜(d)は、本発明の一実施例を説明するための工程順
に示した半導体チップの断面図である。
Embodiment 2 Next, the present invention will be described with reference to the drawings. Figure 2 (a)
8D are cross-sectional views of the semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

【0015】まず図2(a)に示すように、シリコン基
板1を熱酸化して厚さ約500nmのSiO2 膜2を形
成したのちリアクティブイオンエッチング(RIE)法
により、所望の位置に配線となる溝を形成する。
First, as shown in FIG. 2A, a silicon substrate 1 is thermally oxidized to form a SiO 2 film 2 having a thickness of about 500 nm, and then a wiring is formed at a desired position by a reactive ion etching (RIE) method. Forming a groove.

【0016】次に図2(b)に示すように、フォトレジ
スト膜3を剥離したあとスパッタ法により全面に窒化チ
タン膜7を成膜したのちスパッタ法または蒸着法または
CVD法の何れかを用いて全面に銅膜4を堆積して溝を
埋め込む。
Next, as shown in FIG. 2B, after peeling off the photoresist film 3, a titanium nitride film 7 is formed on the entire surface by a sputtering method, and then any of the sputtering method, the vapor deposition method or the CVD method is used. Copper film 4 is deposited on the entire surface to fill the groove.

【0017】次に図2(c)に示すように、銅膜4を室
温で塩素プラズマに曝して銅膜4と反応させる。反応さ
せる膜厚は、反応生成物である塩化銅膜5が窒化チタン
膜7の表面まで反応するように塩素プラズマへの暴露時
間を調節する。
Next, as shown in FIG. 2C, the copper film 4 is exposed to chlorine plasma at room temperature to react with the copper film 4. The film thickness to be reacted is adjusted by the exposure time to chlorine plasma so that the copper chloride film 5, which is a reaction product, reacts up to the surface of the titanium nitride film 7.

【0018】次に図2(d)に示すように、反応させた
塩化銅膜5を大気に曝すことなくシリコン基板1をアッ
シングチャンバーに搬送し加熱を行なう。シリコン基板
1の加熱後、再びエッチングチャンバーにシリコン基板
を搬送し酸素ガスまたは希ガスプラズマを用いてエッチ
ングを行い塩化銅膜5のエッチバックを行なう。次いで
表面に露呈した窒化チタン膜7をフッ素プラズマを用い
てエッチバックを行い銅配線6を形成する。
Next, as shown in FIG. 2D, the silicon substrate 1 is transferred to the ashing chamber and heated without exposing the reacted copper chloride film 5 to the atmosphere. After heating the silicon substrate 1, the silicon substrate is again transported to the etching chamber and is etched using oxygen gas or rare gas plasma to etch back the copper chloride film 5. Next, the titanium nitride film 7 exposed on the surface is etched back using fluorine plasma to form the copper wiring 6.

【0019】このように本実施例によれば、SiO2
に形成した溝に銅膜を埋め込み反応させた塩化銅膜5を
エッチバックにより銅配線6を形成するため、従来のよ
うに銅膜3の微細加工を必要としない。
As described above, according to this embodiment, the copper wiring 6 is formed by etching back the copper chloride film 5 in which the copper film is embedded and reacted in the groove formed in the SiO 2 film. No fine processing of 3 is required.

【0020】[0020]

【発明の効果】以上、説明したように本発明によれば、
所望の位置に加工された溝に銅膜を埋め込み、溝以外の
銅膜を塩化銅膜に反応させエッチバックすることで、銅
膜の微細加工を行なうことなく銅配線を形成することが
できる。このため半導体集積回路の製造プロゼスに用い
ることにより、製造プロセスの簡略化が可能になるばか
りでなく、製造プロセスの確実性・信頼性を向上させる
ことができるとともに、デバイス特性の向上に大きく寄
与できる効果を有するものである。
As described above, according to the present invention,
By embedding a copper film in a groove processed at a desired position and reacting a copper film other than the groove with a copper chloride film to etch back, a copper wiring can be formed without performing fine processing of the copper film. Therefore, when used in the manufacturing process of a semiconductor integrated circuit, not only the manufacturing process can be simplified, but also the reliability and reliability of the manufacturing process can be improved and the device characteristics can be greatly improved. It has an effect.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明するための工程順に示
した半導体チップの断面図。
FIG. 1 is a cross-sectional view of a semiconductor chip showing the process sequence for explaining an embodiment of the present invention.

【図2】本発明の一実施例を説明するための工程順に示
した半導体チップの断面図。
2A to 2D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 SiO2 膜 3 フォトレジスト膜 4 銅膜 5 塩化銅膜 6 銅配線 7 窒化チタン膜1 silicon substrate 2 SiO 2 film 3 photoresist film 4 copper film 5 copper chloride film 6 copper wiring 7 titanium nitride film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板上に層間絶縁膜を形成したのち配線
が形成される溝を形成する工程と、この溝内に銅膜を埋
め込んだ後、塩素を用いたプラズマ中に前記銅膜を曝し
て塩化銅膜を形成する工程と、外気に出すことなく塩化
銅膜を加熱する工程と、加熱後及びエッチングチャンバ
ー内で塩化銅膜のエッチングを行ない銅配線を形成する
工程とを備えたことを特徴とする銅配線の形成方法。
1. A step of forming a groove in which a wiring is formed after forming an interlayer insulating film on a substrate, and burying a copper film in the groove, and then exposing the copper film to plasma using chlorine. To form a copper chloride film, to heat the copper chloride film without exposing it to the outside air, and to form a copper wiring by etching the copper chloride film after heating and in the etching chamber. A method for forming a characteristic copper wiring.
JP32498793A 1993-12-22 1993-12-22 Method for forming copper wirings Pending JPH07183299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32498793A JPH07183299A (en) 1993-12-22 1993-12-22 Method for forming copper wirings

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32498793A JPH07183299A (en) 1993-12-22 1993-12-22 Method for forming copper wirings

Publications (1)

Publication Number Publication Date
JPH07183299A true JPH07183299A (en) 1995-07-21

Family

ID=18171871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32498793A Pending JPH07183299A (en) 1993-12-22 1993-12-22 Method for forming copper wirings

Country Status (1)

Country Link
JP (1) JPH07183299A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459947B1 (en) * 1997-12-30 2005-02-03 주식회사 하이닉스반도체 Method of forming a metal line of semiconductor device
JP2007520079A (en) * 2004-01-30 2007-07-19 ラム リサーチ コーポレーション Stress-free etching using a dynamic liquid meniscus
JP2007533116A (en) * 2003-03-14 2007-11-15 ラム リサーチ コーポレーション System, method and apparatus for improved global dual damascene planarization
SG140443A1 (en) * 2000-05-18 2008-03-28 Tokyo Electron Ltd Film forming appparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62139321A (en) * 1985-12-12 1987-06-23 Fujitsu Ltd Manufacture of semiconductor device
JPH01283936A (en) * 1988-05-11 1989-11-15 Hitachi Ltd Method and apparatus for treating surface
JPH02114639A (en) * 1988-10-25 1990-04-26 Seiko Epson Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62139321A (en) * 1985-12-12 1987-06-23 Fujitsu Ltd Manufacture of semiconductor device
JPH01283936A (en) * 1988-05-11 1989-11-15 Hitachi Ltd Method and apparatus for treating surface
JPH02114639A (en) * 1988-10-25 1990-04-26 Seiko Epson Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459947B1 (en) * 1997-12-30 2005-02-03 주식회사 하이닉스반도체 Method of forming a metal line of semiconductor device
SG140443A1 (en) * 2000-05-18 2008-03-28 Tokyo Electron Ltd Film forming appparatus
JP2007533116A (en) * 2003-03-14 2007-11-15 ラム リサーチ コーポレーション System, method and apparatus for improved global dual damascene planarization
JP4859664B2 (en) * 2003-03-14 2012-01-25 ラム リサーチ コーポレーション Improved global dual damascene planarization method
JP2007520079A (en) * 2004-01-30 2007-07-19 ラム リサーチ コーポレーション Stress-free etching using a dynamic liquid meniscus

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