JPH07182164A - Central processor - Google Patents

Abstract

PURPOSE:To improve the overall processing efficiency of a system by stopping the fetching operation based on the count value of a counter which stores the number of branching instructions carried out within a prescribed time and the count value of a counter which counts the number of instructions stored in an instruction queue. CONSTITUTION:A 1st counter 102 counts and stores the number of instruction codes which are already read into an instruction queue 502 and not read out an instruction decoding unit 519 yet by AND gates 112-114 and OR gates 115-117. The count value of the counter 102 is combined with the count value of a 2nd counter 512 which counts the number of branching instructions that are carried out by the unit 519 within a prescribed time. Thus the fetch bus cycle is suppressed. In such a way, the invalid fetch bus cycle is reduced regardless of the branching instruction and the bus occupation rate of a CPU 101 is reduced down to a necessary limit level. As a result, the overall processing efficiency of a system is improved.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a central processing unit.

[0002]

2. Description of the Related Art Generally, as a technique for speeding up a central processing unit (hereinafter abbreviated as CPU), there is a technique for prefetching an instruction code by using an instruction queue. This is the CPU
In the CPU, the next instruction code is stored in the instruction queue inside the CPU by using the free time of the bus during the internal processing, and immediately after the execution of the previous instruction, the execution of the next instruction is executed. It is a technique that allows you to get started. FIG. 5 shows an example of a CPU using an instruction queue. As shown in FIG. 5, the CPU 501 of this conventional example
Is the instruction queue 50 corresponding to the CPU external data bus.
2, transfer gates 503 and 504, a counter 512, a bus cycle control circuit 514, and NO.
R gate 515, OR gate 516, instruction decoding execution unit 519, queue read / write control circuit 52
It is configured with 0 and.

In FIG. 5, it is assumed that the instruction queue 502 has a capacity of 8 words. Instruction queue 50
In 2, the instruction code fetched from the data bus 518 by the bus cycle control circuit 514 is stored.
In the instruction execution decoding unit 519, the instruction queue 5
The instruction code stored in 02 is fetched, decoded, and executed. In the queue read / write control circuit 520,
A queue write signal 506 for writing the instruction code fetched by the bus cycle control circuit 514 into the instruction queue 502 and a queue read / write signal for reading the instruction code stored in the instruction queue 502 into the instruction decoding execution unit 519. 507 is generated. Counter 512
Is the cue write signal 506 and the cue read signal 50.
It is a 4-bit binary counter that counts up and down by a one-shot LOW pulse of 7 and is reset by a branch instruction detection signal 510 output from the instruction decoding execution unit 519. That is,
The number counted by the counter 512 is the instruction queue 502.
Represents the number of instruction codes waiting to be executed, which are stored in the instruction decoding execution unit 519.
The cue write signal 506 and cue read signal 507
When the two become LOW at the same time, the count number of the counter 512 does not change.

The fetch bus cycle activation request signal 521 output from the NOR gate 515 is output when the branch instruction detection signal 510 output from the instruction decoding execution unit 519 is active or when the count value of the counter 512 is 8, that is, the most significant bit. It is a control signal that becomes inactive, that is, LOW when C3 becomes HIGH. This means that the fetch bus cycle is activated and controlled when the instruction decoding execution unit 519 is executing a branch instruction and when the instruction code stored in the instruction queue 502 is full of 8 words. I mean. OR gate 5
A queue valid signal 517 output from 16 is an output signal of the logical sum operation of the constituent bits of the counter 512, and when the count value of the counter 512 is 0, that is, when the instruction code stored in the instruction queue 502 is 0. Is inactive, i.e., LOW only. The instruction execution bus cycle activation request signal 511 output from the instruction decoding execution unit 519 is a bus cycle activation request signal necessary for executing an instruction, and this bus cycle is distinguished from the fetch bus cycle. There is. In the following, for simplicity of explanation, it is assumed that the instruction execution bus cycle activation request signal 511 is always LOW.

Next, the operation of the conventional CPU 501 shown in FIG. 5 will be described.

First, the operation of fetching an instruction code in the CPU 501 and storing it in the instruction queue 502 will be described. Instruction execution bus cycle activation request signal 511
Is inactive, i.e., LOW, the fetch bus cycle activation request signal 521 becomes active, i.e., HIGH, thereby activating the fetch bus cycle. When the fetch bus cycle activation request signal 521 becomes HIGH, the bus cycle control circuit 514 activates the fetch bus cycle, reads a 1-word instruction code from the data bus 518, and sends the data to the internal data bus 505. At this time, at the same time, the bus cycle control circuit 514 receives the status signal 50 of the fetch bus cycle.
8 is made active, that is, HIGH. The queue read / write control circuit 520 outputs a one-shot LOW pulse as the queue write signal 506 when the status signal 508 of the fetch bus cycle becomes HIGH. When the cue write signal 506 becomes LOW, the transfer gate 503 opens, and the data of the instruction code sent to the internal data bus 505 is transferred to the instruction queue 50.
Stored in 2. At this time, the cue light signal 5
The one-shot LOW pulse of 06 causes the counter 51 to
The count number of 2 is incremented by 1.

Next, the operation of reading the instruction code from the instruction queue 502 by the instruction decoding execution unit 519 will be described. When the processing of the previous instruction is finished and the decoding execution of the next instruction is started, in the instruction decoding execution unit 519, the queue request signal 509 is activated, that is, HI.
GH output, and queue read / write control circuit 520
To enter. At this time, the cubic valid signal 517 is H
When the IGH, that is, the instruction code in the instruction queue 502 is not empty, the one-shot L as the queue read signal 507 in the queue read / write control circuit 520.
Output OW pulse. Cue white control circuit 5
When 20 becomes LOW, the transfer gate 504 is opened, and the instruction code sent from the instruction queue 512 is fetched by the instruction decoding execution unit 519. At this time, the one-shot LO of the cue dry weight signal 507
The W pulse decrements the count number of the counter 512 by one.

As described above, in the CPU 501, the instruction queue 502 is interposed to perform the parallel processing of the instruction fetch and the instruction decoding execution, whereby the processing speed is increased. However, instruction queue 5
In the case of prefetching the instruction code by 02, when an instruction such as a branch instruction that changes the program sequence is executed, all the instruction codes already stored in the instruction queue at that time are wasted. FIG. 6 is a timing chart showing this example based on the conventional CPU 501 shown in FIG. In FIG. 6, the CPU
In 501, a branch instruction is fetched at time T1. This branch instruction is read by the instruction decoding execution unit 519 at time T9 and decoded at time T10 to detect that it is a branch instruction.
At this time, the branch instruction detection signal becomes active, that is, HIGH, and the counter 512 is reset from "7" to "0". That is, this means that the instruction code stored in the instruction queue 502 until the branch instruction is executed is discarded by 7 words. The discarded seven-word instruction code is an instruction fetched by the CPU 501 from time T2 to time T7 and at time T9. That is, in the CPU 501 during this period, the bus is occupied by the invalid fetch bus cycle. Such meaningless bus occupation in the CPU causes a problem of significantly degrading the performance of the entire system.

Therefore, in the following, a conventional technical method adopted to avoid this problem will be described. FIG. 7 is a block diagram showing an example of another conventional CPU. As shown in FIG. 7, the CPU 7 of the conventional example
01 is an instruction queue 502 and transfer gates 503 and 504 corresponding to the CPU external data bus.
, Counter 512, and bus cycle control circuit 514
, OR gate 516, and instruction decoding execution unit 51
9, a queue read / write control circuit 520, a branch instruction detection predecoder 702, and a flip-flop 704.
, An OR gate 705, and a NOR gate 706.

In FIG. 7, it is assumed that the capacity of the instruction queue 502 is 8 words, as in the case of the above-mentioned conventional example. The instruction queue 502 stores the instruction code fetched from the data bus 518 by the bus cycle control circuit 514. Instruction execution decoding unit 5
At 19, the instruction code stored in the instruction queue 502 is fetched, decoded, and executed. In the queue read / write control circuit 520, the bus cycle control circuit 5
The instruction code fetched by 14 is stored in the instruction queue 5
Cue write signal 506 written in 02 and instruction queue 5
A queue read / write signal 507 for reading the instruction code stored in 02 into the instruction decoding execution unit 519 is generated. The counter 512 displays the cue light signal 50.
6 and a 4-bit binary counter that counts up and down by a one-shot LOW pulse of the queue read signal 507 and is reset by the branch instruction detection signal 510 output from the instruction decoding execution unit 519. The operation of each constituent element is the same as that of the above-mentioned conventional example. In the conventional example, the branch instruction detecting predecoder 702 is
The instruction queue 5 is provided on the output side of the transfer gate 503.
02 is connected in parallel. Also flip-flop 7
The output 703 of the branch instruction detection predecoder 702 is input to the set side input of 04, and the instruction decoding execution unit 5 is input to the reset side input of the flip-flop 704.
A branch instruction detection signal 510 output from 19 is input. The OR gate 705 has a flip-flop 70.
4 and the branch instruction detection signal 510 are input, and the output is input to the NOR gate 706. NO
The fetch bus cycle activation request signal 707 output from the R gate 706 and input to the bus cycle control circuit 514 activates the output of the OR gate 705 or the count value of the counter 512 is 8, that is, the most significant bit C3. Is a control signal that becomes inactive, i.e., LOW when becomes active, i.e., HIGH.

Next, the operation of the conventional CPU 701 of FIG. 7 will be described with reference to the timing chart of FIG. Figure 8
FIG. 8 is a timing chart showing an operation when CPU 701 of FIG. 7 executes the same instruction as that shown in FIG. 6. In FIG. 8, it is assumed that the CPU 701 is fetching a branch instruction at time T1.
The instruction code of the branch instruction fetched at this time is fetched in the instruction queue 502 and simultaneously input to the branch instruction detection predecoder 702. Branch instruction detection predecoder 702
In, decode the instruction code input at this time,
It is determined whether or not the instruction is a branch instruction. Time T1
Since the instruction taken in is a branch instruction, the output 703 of the branch instruction detecting predecoder 702 becomes active, that is, HIGH, and is input to the set side of the flip-flop 704 to set the flip-flop 704. Therefore, the output of the OR gate 705 becomes HIGH, the fetch bus cycle activation request signal 707 output from the NOR gate 706 becomes inactive LOW, and the activation of the fetch bus cycle from time T2 is suspended. The instruction code of the branch instruction fetched in the fetch bus cycle at time T1 is fetched by the instruction decoding execution unit 519 at time T9. In the instruction decoding execution unit 519, the branch instruction detection signal 510 is set to HIGH and is output, which resets the flip-flop 704. When this branch instruction detection signal 510 falls to LOW at time T10, the output value of the OR gate 705 becomes LOW, and the fetch bus cycle activation request signal 707 becomes active, that is, H.
Since it becomes IGH, the fetch bus cycle is activated again from time T11.

As described above, the conventional CPU shown in FIG.
In 701, a branch instruction detecting predecoder 702 provided in parallel with the instruction queue 502 determines whether or not the instruction code is a branch instruction. Make a decision,
As soon as it is found that the instruction is a branch instruction, the instruction fetch is suppressed. Therefore, in FIG. 6, the invalid fetch bus cycle that occurs from time T2 to time T7 and time T9 does not occur in FIG. Therefore, by reducing the bus occupancy rate of the CPU 701 to the required limit, it becomes possible for other bus masters connected to the bus of the CPU 701 to use the vacant bus, and the processing efficiency of the entire system is improved. is there.

[0013]

SUMMARY OF THE INVENTION The conventional CPU described above.
However, if the instruction to be executed is a conditional branch instruction, it has the following drawbacks.

Here, a conditional branch instruction, a branch instruction, is a branch instruction according to a value of a flag register in the CPU for storing a state of an instruction execution processing result, that is, a program status word (hereinafter abbreviated as PSW), and not performed. It is an instruction that causes a difference in operation from the case. The branch instructions described so far have been unconditional branch instructions that always branch. If time T1 in Figure 8
In, it is assumed that the fetched instruction is a conditional branch instruction. Whether or not a branch is actually executed by this branch instruction is determined by the value of PSW at time T9 at the time of execution, so that judgment cannot be made at time T1. Branch instruction detection predecoder 7
In 02, since the output signal 703 is set to HIGH only for the unconditional branch instruction, the output signal 703 remains LOW for the conditional branch instruction in this case.
Therefore, the fetch from time T2 is continued.
However, if the PSW at time T9 is a condition for branching the instruction fetched at time T1, then time T2
The result is that all subsequent fetched instructions will be invalid. That is, the conventional CPU cannot stop an invalid fetch bus cycle when the fetched instruction is a conditional branch instruction. In particular, C
When the programs executed in the PU are all configured not to use conditional branch instructions as branch instructions, the CPU is in a state of issuing many invalid fetch bus cycles. This allows the CPU
However, there is a drawback in that the processing efficiency of the entire system is remarkably reduced by unnecessarily increasing the bus occupancy rate.

Further, since the conventional CPU has the branch instruction detection predecoder, it has a drawback that the circuit scale becomes large and the cost increases.

[0016]

A CPU of the present invention is a pre-read-out type storage means (instruction queue) for temporarily storing an instruction code read from a predetermined storage device, and the storage means once stored in the storage means. The instruction decoding execution means for reading the instruction code and decoding and executing the instruction code, and the number of the instruction codes already read in the storage means and not read by the instruction decoding execution means are counted. A central processing unit including at least a first counting unit that stores the second counting unit that counts the number of branch instructions executed by the instruction decoding execution unit within a predetermined time;
And a means for suppressing a fetch bus cycle request by a combination of the count value of the first count means and the count value of the second count means. Is characterized by.

The second counting means may be provided with a switch circuit having a function of switching the predetermined time.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, the CPU 10 of this embodiment
1 is an instruction queue 5 corresponding to the CPU external data bus
02, transfer gates 503 and 504,
Counters 102 and 512, bus cycle control circuit 514, selector 103, and AND gates 112 to 1
14, OR gates 115 to 117, and NOR gate 5
15, an instruction decoding execution unit 519, and a queue read / write control circuit 520. In FIG. 1, the capacity of the instruction queue 502 will be described as 8 words, as in the case of the above-described conventional example.

In FIG. 1, in the counter 102 having the function of counting the number of branch instructions, the branch instruction detection signal 510 output from the instruction decoding execution unit 519.
And a clock are input, the number of branch instructions executed within a predetermined time is counted, and the value is determined by the terminals 123 and 12.
2, 121 and 120. The count value output by the counter 102 that counts the number of branch instructions is 4 bits in the present embodiment, and the terminals 123, 122, 121 and 120 are arranged in the order of the higher order bits.
Is output to. Here, as the clock input to the counter 102, for example, the basic clock of the CPU 101 may be used. In the instruction decoding execution unit 519, when an instruction output from the instruction queue 502 is fetched and the instruction branches, if the branch instruction is an unconditional branch instruction or a condition is satisfied by a conditional branch instruction, Outputs the branch instruction detection signal 510 to the HIGH level and outputs it. Signals 104, 105 and 106 output from AND gates 112, 113 and 114
Then, the signal 107 output from the counter 102 is input to the selector 103. Here, the counter 10
When the counter output value of 2 is 8 or more, the signal 107 is H
When it goes to IGH level and is 4 or more and 7 or less, signal 10
6 becomes HIGH level, the signal 105 becomes HIGH level when it is 2 or more and 3 or less, and the signal 104 becomes HIGH level when it is 1 or less. Also, signal 10
8 is HIGH when the count value of the 4-bit counter 512 is 8, and the signal 109 indicates the counter 51.
When the counter value of 2 becomes 4 or higher, the signal 110 becomes high when the counter value of the counter 512 is 2 or higher.
IGH level, and the signal 517 is the counter 51.
When the counter value of 2 is 1 or more, it becomes HIGH level.
In the selector 103, the signal 517 is output when the signal 107 is HIGH level, the signal 110 is output when the signal 106 is HIGH level, the signal 109 is output when the signal 105 is HIGH level, and the signal 108 is output when the signal 104 is HIGH level. NOR gate 515 respectively
Output to. The output signal of the NOR gate 515 is input to the bus cycle control circuit 514 as the fetch bus cycle activation request signal 111. Note that the other components other than this are the same as those in the conventional example shown in FIG.
The description is omitted.

Here, by the counter 102 which counts the number of branch instructions, within a predetermined time,
A second counter for counting and storing the number of branch instructions executed in the instruction decoding execution unit 519 is constituted, and AND gates 112, 113 and 114 are formed.
A count of a first counter that counts and stores the number of instruction codes that have already been read into the instruction queue 502 and have not been read out from the instruction decoding execution unit 519 by the OR gates 115, 116 and 117, and the selector 103. A combination of the value and the count value of the second counter constitutes a circuit that suppresses the fetch bus cycle.

Before explaining the operation of the present embodiment shown in FIG. 1, the operation of the counter 102 for counting the number of branch execution instructions, which is a component of FIG. 1, will be described with reference to FIG. .

FIG. 2 is a block diagram showing a first embodiment of the counter 102 for counting the number of branch execution instructions in this embodiment. The branch instruction detection signal 510 is input to the input terminal 119, and the 4-bit counter 201 is counted up. The counter 206 is counted up by the clock signal at the input terminal 118. The 4-bit latch 205 inputs the count value of the counter 201, holds the value by the carry signal 207 of the counter 206, and outputs the value to the output terminals 120, 121, 122 and 123. The NAND gate 203 and the AND gate 202 serve to prevent the counter 201 from overflowing.

Next, the operation of the counter 102 shown in FIG. 2 will be described. The counter 206 is incremented by the clock signal input to the input terminal 118. Meanwhile, a branch instruction detection signal 51 input to the input terminal 119.
The counter 201 is incremented by 0. That is, the counter 201 indicates the number of executed branch instructions. The number of counts of the counter 206 is 2 8 25
When it reaches 6, the carry signal 207 becomes HIGH level, and in the latch 205, the counter 2 at that time is
Latch the count value of 01. At this time, the latch 205
The value latched by indicates the number of branch instructions executed while the counter 206 counts 256 times. Next, the carry signal 207 resets the count value of the counter 201 via the delay circuit 204. As a result, the counter 201 counts the number of branch instructions from 1 again. Counter 20 that outputs carry signal 207
In 6 as well, similarly, all the bits become 0 again, and the count-up is performed again.

Next, the operation of the CPU 101 shown in FIG. 1 will be described. Initially, the count value in the counter 102 that counts the number of branch execution instructions is 0, that is, the output terminal 12
It is assumed that 0, 121, 122 and 123 are all 0. At this time, the signal 104 output from the AND gate 112 becomes HIGH level, so that the selector 103
, Select signal 108 as an input to NOR gate 515. This is because when the count value of the counter 512 is 8, that is, when the number of instructions stored in the instruction queue 502 becomes 8 words, the fetch bus cycle activation request signal 111 output from the NOR gate 515 becomes LOW, and the fetch bus cycle It means that the demand is suppressed.

Counter 1 for counting the number of branch execution instructions
In 02, the number of instructions branched by the instruction decoding execution unit 519 is counted in response to the input of the branch instruction detection signal 510 output from the instruction decoding execution unit 519. This count is based on the clock input terminal 11
The operation is performed every predetermined time counted by the clock input to 8, and the value counted during that time is output to the terminals 123, 122, 121 and 120. It is assumed that the number of branch instructions executed during the period is two or three after the lapse of a predetermined time. In this case, the output terminal 1 of the counter 102
21 is HIGH level, and the output terminals 123 and 122 are LOW level, so that the signal 105 is HIGH level. Therefore, in the selector 103, the signal 10
9 is selected as the input to NOR gate 515.
This is because when the count value of the counter 512 is 4 or more, that is, when the number of instructions stored in the instruction queue 502 is 4 words or more, the fetch bus cycle activation request signal 111 output from the NOR gate 515 becomes LOW level. , Fetch bus cycle requests are suppressed.

Next, a case where the number of branch instructions executed during the period after the lapse of a predetermined time is between 4 and 7 will be described. In this case, the counter 10
The output terminal 122 of 2 is HIGH level, and the output terminal 123
Goes low, the signal 114 goes high.
It becomes H level. Therefore, in the selector 103,
Signal 110 is selected as an input to NOR gate 515. This is because when the count number of the counter 512 is 2 or more, that is, when the number of instructions stored in the instruction queue 502 is 2 words or more, the fetch bus cycle activation request signal 111 output from the NOR gate 515 becomes LOW. , Means that fetch bus cycle requests are suppressed. Next, a case where the number of branch instructions executed during the period after the predetermined time has elapsed is eight or more will be described. In this case, since the output terminal 123 of the counter 102 becomes HIGH level, the signal 107
Becomes HIGH level. Therefore, the selector 103 selects the signal 517 as an input to the NOR gate 515. This is because when the count number of the counter 512 is 1 or more, that is, when the number of instructions stored in the instruction queue 502 is 1 word or more, the fetch bus cycle activation request signal 111 output from the NOR gate 515 is LO.
This means that the fetch bus cycle request is suppressed to W.

FIG. 3 shows the CP of FIG. 1 explained above.
FIG. 7 is a timing chart showing the operation of U101, which is a CPU 10
FIG. 9 is a timing diagram corresponding to the operation when executing the same instruction as in the timing diagram shown in FIG. 8 by 1. Since the signal 104 is at the HIGH level until the time T0, the condition for suppressing the futuristic bus cycle is that the count value of the counter 512 becomes 8. Since the value in the counter 512 at this time has not yet reached 8, the fetch bus cycle is activated at the next time T1. Now, at time T1, the output of the counter 102 changes, the signal 107 is HIGH, and the signal 104 is LO.
Suppose it has become W. The condition for suppressing the fetch bus cycle at this time is that the count value of the counter 512 is 1
That is all. Counter 5 at time T1
Since the count value of 12 exceeds 1, the fetch bus cycle from time T2 is suppressed. The branch instruction fetched at time T1 is executed at time T10, and a new fetch bus cycle is started at time T11. In FIG. 3, an invalid fetch bus cycle has not occurred.

Next, another embodiment of the present invention will be described. The present embodiment has the same overall configuration as that of FIG. 1, but is different from the above-described embodiments in the internal configuration of the counter 102 that counts the number of branch execution instructions. Figure 4
FIG. 8 is a block diagram showing an internal configuration of a second embodiment of a counter 102 that counts the number of branch execution instructions. As shown in FIG. 4, the counter 102 is the counter 20.
1 and 206, an AND gate 202, a NAND gate 203, a delay circuit 204, a latch 205, and a changeover switch 304, and a changeover switch 304 is newly added. By the changeover switch 304, as the carry signal 207, three carry signals including a carry signal from the fifth bit of the counter 206, a carry signal from the sixth bit, and a carry signal from the seventh bit are carried. It is possible to select one carry signal from the signals.

In the timing diagram shown in FIG.
While the time interval for counting the number of branch execution instructions is a fixed value of 256 clock times, according to the counter 102 of the present embodiment, this time interval is not only 256 clock times but 128 clock times and The changeover switch 30 is selected from among the three times including the 64 clock time.
It can be arbitrarily selected by 4. This gives C
An instruction executed by the PU 101, that is, a combination having the highest execution efficiency according to software can be set by the changeover switch 304.

[0031]

As described above, according to the present invention, the counter for storing the number of branch instructions executed by the instruction decoding execution unit within a predetermined time, the count value of the counter and the instruction queue are stored. By providing a means for stopping the fetch by a combination with a count value that counts the number of instructions being executed, it is possible to reduce invalid fetch bus cycles regardless of the type of branch instruction, and to reduce the CPU bus occupation rate. There is an effect that the processing efficiency of the entire system can be improved by lowering it to the required limit.

Further, the present invention can be realized by a small-scale circuit configuration of two counters, one latch, and one selector and about 10 logic gates.
The branch instruction detecting predecoder, which has a large circuit scale and is required in the related art, is not required, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a first embodiment of a counter for counting the number of branch instructions in the above embodiment.

FIG. 3 is a timing chart showing an operation of the one embodiment.

FIG. 4 is a block diagram showing a second embodiment of a counter for counting the number of branch instructions in the above embodiment.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a timing chart showing an operation of a conventional example.

FIG. 7 is a block diagram showing another conventional example.

FIG. 8 is a timing chart showing an operation of the other conventional example.

[Explanation of symbols]

 101, 501, 701 CPU 102, 201, 206, 512 counter 103 selector 112-114, 202 AND gate 115-117 OR gate 203 NAND gate 204 delay circuit 205 latch 304 changeover switch 502 instruction queue 503, 504 transfer gate 505 internal Data bus 514 Bus cycle control circuit 515 NOR gate 516 OR gate 518 Data bus 519 Instruction decoding execution unit 520 Queue read / write control circuit 702 Branch instruction detection predecoder 704 Flip-flop

Claims (2)

[Claims] 1. A read-ahead first-out type storage means (instruction queue) for temporarily storing an instruction code read from a predetermined storage device, and an instruction code once stored in the storage means to read the instruction code Instruction decoding execution means for performing decoding and execution, and already read in the storage means,
In a central processing unit including at least a first counting means for counting and storing the number of instruction codes not read by the instruction decoding execution means, the instruction decoding execution means executes within a predetermined time. A fetch bus cycle request is suppressed by a combination of a second counting unit that counts the number of branch instructions that have been executed, a count value of the first counting unit, and a count value of the second counting unit. A central processing unit, comprising: 2. The central processing unit according to claim 1, wherein the second counting means includes a switch circuit having a function of switching the predetermined time.