JPH0718172Y2 - Variable frequency signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a device for generating a signal whose frequency can be varied, and more particularly to a variable frequency signal generator suitable for use in a signal generator of an FFT analyzer.

<Prior Art> A signal generator for an FFT analyzer needs to generate various signals necessary for characteristic analysis, such as a fixed sine wave, a chirp sine wave, and a multisine wave. For that purpose, it is necessary to generate the basic sine wave and to change its frequency freely.

The sine wave can be generated by storing the waveform data of the sine wave in the ROM, sequentially reading out the data, and performing analog conversion. To change the frequency, the read cycle may be changed, but the upper limit frequency is limited by the ROM access time limitation. Therefore, the reading cycle is made constant and the waveform data is appropriately thinned and read. For example, if data is read every other piece, a waveform having a doubled frequency can be obtained. However, in such a configuration, since the required waveform data and the waveform data stored in the ROM do not always match at the timing of reading when obtaining a waveform of an arbitrary frequency, interpolation must be performed.

FIG. 5 shows the configuration of such a signal generator. In FIG. 5, initial data such as an initial frequency, an initial phase, and a frequency change amount are input to the phase data generator 1. Phase data generator 1 synchronizes with ROM 2 in synchronization with a separately input clock.
The address and the data generation interval Δx ₀ are output. ROM2
Stores the waveform data and the amount of change Δy of the data, and outputs the waveform data stored at the address output from the phase data generator 1 to the adder 3 and the amount of change Δy to the calculator 4. The calculation unit 4 calculates the interpolation data of the waveform and outputs it to the addition unit 3. The adder 3 adds these data and outputs it to the register 5. The register 5 latches the output of the adder 3 in synchronization with the clock input to the phase data generator 1. The output of the register 5 is converted into an analog signal by the DA conversion unit 6, smoothed by a filter (not shown), and output.

The interpolation calculation method of such a signal generator will be described with reference to FIG. The horizontal axis of FIG. 6 represents time, the vertical axis represents the size of data, A and B (● marks) supply data and timing read from ROM 2, and C (∘ marks) supply DA conversion unit 6. Data and timing. Assuming that the data sizes at points C and A are y _c and y _A , respectively, and the interval from point A to point C is Δx, y _C = y _A + Δy (Δx / Δx ₀ ) However, Δx ₀ is the generation interval of the data generated from the phase data generator 1, and Δy is the change amount data generated from the ROM 2. By performing this calculation in the calculation unit 4 and the addition unit 3, it is possible to supply appropriate waveform data to the DA conversion unit 6 at appropriate timing.

<Problems to be Solved by the Invention> However, in such a waveform generator, there is a problem that the circuit configuration becomes complicated because the waveform data must be interpolated.

Further, there is a problem that the upper limit of the generated frequency is limited because a certain time is required to perform the calculation.

<Purpose of Invention> An object of this invention is to provide a waveform generator capable of varying the frequency with a simple configuration.

<Means for Solving the Problems> In order to solve the above problems, according to the present invention, an address and timing data are generated by a phase data generator according to a clock signal, and waveform data in a memory is read by this address. Then, the clock is delayed based on the timing data generated by the phase data generator,
The waveform data read by this delayed clock is stored in a register and supplied to the DA converter.

<Embodiment> FIG. 1 shows an embodiment of a variable frequency waveform generator according to the present invention. The same elements as those in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, reference numeral 10 denotes a phase data generator, to which an initial frequency, an initial phase, initial data of a frequency change amount, and a clock are input. The phase data generator 10 generates address and timing data in synchronization with the clock based on these initial data. Reference numeral 11 is a ROM as a storage unit, which stores sine wave waveform data. This waveform data is read by the address generated by the phase data generator 10. That is, the waveform data of the ROM 11 is appropriately thinned out and read according to the frequency of the waveform to be generated. This waveform data is output to the register 5. A timing controller 12 receives the timing data and the clock output from the phase data generator 10, delays the clock by a time based on the timing data, and outputs the delayed clock to the register 5. Register 5 latches the output of ROM11 at the timing of this delayed clock and D
Output to the A conversion unit 6. The DA converter 6 converts the analog signal and outputs the analog signal through a filter (not shown).

Next, the operation of this embodiment will be described with reference to FIG.
The horizontal axis of FIG. 2 is time, and the vertical axis is the size of the waveform data. D (● mark) represents the waveform data read from the ROM 11. In the conventional example of FIG. 5 in which the clock is supplied to the register 5, the clock rises at the time t ₁ , so the waveform data is latched in the register 5 at this timing. Therefore, the waveform is deviated from the accurate waveform 13 and is supplied to the DA converter 6 to cause distortion. Therefore, interpolation calculation must be performed. In this embodiment, the timing controller 12 delays the rising edge of the clock by Δt and shifts it until time t ₂ so that it is latched in the register 5 at an accurate timing. The timing data is represented by an 8-bit binary number, and assuming that value is n, the delay amount Δt is represented by Δt = (256−n) / (256f) (1) f: clock frequency Can be done. The timing control unit 12 performs this calculation to obtain the delay amount Δt, delays the clock by this value, and outputs the delayed clock. FIG. 3 shows the relationship between the timing data n, the clock and the output of the timing control unit 12. (A)
From the equation (1), Δt shown in (B) is calculated by the timing data n of (1), and as a result, it is delayed as shown in (D) as compared with the clock shown in (C). As a result, since it is latched in the register 5 at an appropriate timing, it is not necessary to perform interpolation as in the conventional example. When changing the frequency of the output waveform, the waveform data stored in the ROM 11 is appropriately thinned out, so that the number of pulses in (C) and the number of pulses in (D) may not match during one cycle of the output waveform. Occur. In this case, the timing control unit 12 appropriately thins out the pulse of (D).

FIG. 4 shows an example of the output waveform. The mark ◯ indicates the timing of latching the waveform data in the register 5. (A) is a basic waveform, and since the waveform data of the ROM 11 is read out in order, no correction is made by the timing control unit 12.
Therefore, the latch timings (marked with ◯) occur at equal intervals. (B) is a case where a waveform having a higher frequency than that of (A) is output, and the timing control unit 12 has performed correction. Therefore, the latch timing occurs at unequal intervals.

In this embodiment, the case of a sine wave is explained, but other waveforms can be similarly constructed.

<Advantages of Device> As described above in detail with reference to the embodiments, in this device, the waveform data is supplied to the DA converter at an appropriate timing by shifting the timing of storing in the register. Therefore, an arithmetic circuit for interpolation is not required, and there is an effect that a frequency variable waveform generator can be realized with a simple configuration.

Further, since the time required for the calculation is unnecessary, there is an effect that a high frequency waveform can be easily generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a variable frequency waveform generator according to the present invention, FIGS. 2 to 4 are diagrams for explaining the operation thereof, and FIG. 5 is a block diagram of a conventional waveform generator. , FIG. 6 is a diagram for explaining the operation. 5 ... Register, 6 ... DA converter, 10 ... Phase data generator, 11 ... ROM, 12 ... Timing controller.

Claims (1)

[Scope of utility model registration request] 1. A phase data generator that generates an address and timing data according to a clock signal, a storage unit that receives an address from the phase data generator and outputs stored waveform data, and a storage unit of the storage unit. A register that holds an output; a timing control unit that receives the timing data and the clock signal of the phase data generation unit, delays the clock signal based on the timing data, and outputs the delayed signal to the register as a latch signal; A variable frequency signal generator having a DA converter that converts an output of a register into an analog signal.