JPH07176765A - Semiconductor strain transducer - Google Patents

Semiconductor strain transducer

Info

Publication number
JPH07176765A
JPH07176765A JP31991293A JP31991293A JPH07176765A JP H07176765 A JPH07176765 A JP H07176765A JP 31991293 A JP31991293 A JP 31991293A JP 31991293 A JP31991293 A JP 31991293A JP H07176765 A JPH07176765 A JP H07176765A
Authority
JP
Japan
Prior art keywords
amorphous
thin film
semiconductor thin
semiconductor
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP31991293A
Other languages
Japanese (ja)
Inventor
Shoji Nitta
昌二 仁田
Hisakuni Ito
寿国 伊藤
Shinichi Ito
真一 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ishizuka Glass Co Ltd
Original Assignee
Ishizuka Glass Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ishizuka Glass Co Ltd filed Critical Ishizuka Glass Co Ltd
Priority to JP31991293A priority Critical patent/JPH07176765A/en
Publication of JPH07176765A publication Critical patent/JPH07176765A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To provide a semiconductor strain transducer where a gauge rate can be adjusted easily, the element with a large area can be manufactured simply and inexpensively, and measurement in a three-dimensional curved surface can be made. CONSTITUTION:Either p-type, i-type or n-type amorphous Si semiconductor thin film 2 is formed in insulated state from a thin-piece substrate 1 on either one of the thin-piece substrate 1 which is deformed according to external stress, a pair of input electrodes 5 and a pair of output electrodes 6 are provided on amorphous Si semiconductor thin film for forming a strain gauge 10, and at the same time a protection film 4 for insulation is formed on the surface of the amorphous Si semiconductor thin film 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、圧力センサや歪センサ
等として用いられるピエゾ抵抗効果を応用した半導体歪
変換素子に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor strain conversion element which is used as a pressure sensor, a strain sensor or the like and which utilizes a piezoresistive effect.

【0002】[0002]

【従来技術】従来、半導体歪変換素子は、Siウエハー
から切り出して所定の大きさに切断した単結晶Siチッ
プの一部分を研摩加工やエッチング等により薄くしてダ
イヤフラムを形成し、ダイヤフラムに拡散技術を用いて
歪感応素子を形成し、これをブリッジ配線して歪ゲージ
を構成していた。ところが、研摩加工やエッチングによ
りダイヤフラムを形成するため、研摩ミスによる歩留り
の低下や製造に時間を要し、コストアップの原因となる
という問題があった。
2. Description of the Related Art Conventionally, a semiconductor strain conversion element has a diaphragm formed by thinning a part of a single crystal Si chip cut out from a Si wafer and cut into a predetermined size by polishing or etching to form a diffusion technique on the diaphragm. A strain sensitive element was formed by using the strain sensitive element, and this was bridge-wired to form a strain gauge. However, since the diaphragm is formed by polishing and etching, there is a problem in that a yield is reduced due to a polishing mistake and it takes time to manufacture, which causes a cost increase.

【0003】また、単結晶Siチップの大きさはSiウ
エハーの面積によって制限されるので、ウエハー以上の
面積を有する素子を製造することはできなかった。しか
も、単結晶Siからなるダイヤフラム上に歪ゲージを形
成する際、ダイヤフラムの厚みを均一にすることが難し
いうえに、ドーピングによる不純物の注入量のばらつき
等により、ゲージ率を高精度に制御することは困難であ
った。そのうえ、単一平面で歪を感知することになるの
で、3次元的な曲面における歪分布の測定は実質的に測
定できず、利用範囲が限られるという問題があった。
Further, since the size of the single crystal Si chip is limited by the area of the Si wafer, it has been impossible to manufacture an element having an area larger than that of the wafer. Moreover, when forming a strain gauge on a diaphragm made of single-crystal Si, it is difficult to make the diaphragm uniform in thickness, and the gauge ratio is controlled with high accuracy due to variations in the amount of impurities injected due to doping. Was difficult. In addition, since the strain is sensed on a single plane, there is a problem that the strain distribution on a three-dimensional curved surface cannot be practically measured and the usable range is limited.

【0004】[0004]

【発明が解決しようとする課題】本発明の目的は、上記
した問題点を解消し、ゲージ率の調整が容易なうえ、簡
単且つ、安価に大面積のものを製造することができ、し
かも、3次元的な曲面における測定が可能な半導体歪変
換素子を提供することにある。
SUMMARY OF THE INVENTION The object of the present invention is to solve the above-mentioned problems, to easily adjust the gauge ratio, and to easily and inexpensively manufacture a large area product. An object of the present invention is to provide a semiconductor strain conversion element capable of measuring a three-dimensional curved surface.

【0005】[0005]

【課題を解決するための手段】本発明は、外部からの応
力に応じて変形する薄片状基板の少なくとも一方の面
に、該薄片状基板とは絶縁状態でp型、i 型、n 型のい
ずれかのアモルファスSi半導体薄膜を形成し、該アモ
ルファスSi半導体薄膜上に、一対の入力電極と出力電
極とを設けて歪ゲージを形成するとともに、該アモルフ
ァスSi半導体薄膜の表面に絶縁用の保護膜を形成した
ことを特徴とするものである。
According to the present invention, a p-type, an i-type, and an n-type are provided on at least one surface of a flaky substrate which is deformed in response to an external stress while being insulated from the flaky substrate. An amorphous Si semiconductor thin film is formed, a pair of input electrodes and output electrodes are provided on the amorphous Si semiconductor thin film to form a strain gauge, and an insulating protective film is formed on the surface of the amorphous Si semiconductor thin film. Is formed.

【0006】[0006]

【作用】本発明の半導体歪変換素子は、薄片状基板の表
面に形成したアモルファスSi半導体薄膜がピエゾ抵抗
層となり、薄片状基板が外部からの応力を受けると、該
薄片状基板とともにアモルファスSi半導体薄膜が変形
し、該アモルファスSi半導体薄膜上に一対の入力電極
と出力電極とよりなる歪ゲージは、アモルファスSi半
導体薄膜面に対して垂直方向の応力を感知して、ピエゾ
抵抗効果によって電気信号の変位を出力する。
In the semiconductor strain conversion element of the present invention, the amorphous Si semiconductor thin film formed on the surface of the flaky substrate serves as a piezoresistive layer, and when the flaky substrate receives an external stress, the flaky substrate and the amorphous Si semiconductor The thin film is deformed, and a strain gauge consisting of a pair of input electrodes and output electrodes on the amorphous Si semiconductor thin film senses a stress in a direction perpendicular to the surface of the amorphous Si semiconductor thin film, and a piezoresistive effect causes an electrical signal of Output the displacement.

【0007】ピエゾ抵抗効果は一般的にはSi単結晶体
ように限られた晶属に属する結晶において認められる現
象であるが、アモルファスSi半導体でも外部からの応
力に応じて、荷電子帯と電導帯間のエネルギー差の変
化、及びバンド間の局在準位の変化によって抵抗値が変
化するので、ピエゾ抵抗層として有効に利用できるもの
である。
The piezoresistive effect is a phenomenon generally observed in crystals belonging to a limited crystal group such as a Si single crystal body. However, even in an amorphous Si semiconductor, depending on external stress, the valence band and the conductivity can be increased. Since the resistance value changes due to the change in energy difference between bands and the change in localized level between bands, it can be effectively used as a piezoresistive layer.

【0008】[0008]

【実施例】以下、本発明を歪ゲージを片面に形成した第
1の実施例を図1〜図6に基づいて詳細に説明する。1
は外部からの応力に応じて変形する薄片状基板であり、
該薄片状基板1には容量結合型、又は誘導結合型等のプ
ラズマCVDによってi型、p型、n型等ののアモルフ
ァスSi半導体薄膜2が被着形成されている。該アモル
ファスSi半導体薄膜2の原料ガスとしてはSiH4、Si2H
6 、SiF4、SiCl4 、SiCl4-xHx 等を使用してi型のアモ
ルファスSi半導体薄膜2を得る。一方、p型半導体を
得るには通常ジボランガスB2H6、又n型半導体を得るに
は通常フォスフィンガスPH3 あるいはアルシンガスAsH3
をそれぞれ原料ガスにドーピングすればよく、これらの
ドーピングガスの混合比を調整することによって、アモ
ルファスSi半導体薄膜2の導電率を任意に調整するこ
とができる。また、この他にもGeH4、CH4 等を原料ガス
に混合して合金形のアモルファスSi半導体薄膜2とす
ることによって、導電率を調整することもできる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which a strain gauge is formed on one surface of the present invention will be described in detail below with reference to FIGS. 1
Is a flaky substrate that deforms in response to external stress,
An amorphous Si semiconductor thin film 2 of i-type, p-type, n-type or the like is deposited on the thin substrate 1 by plasma CVD of capacitive coupling type or inductive coupling type. The raw material gas for the amorphous Si semiconductor thin film 2 is SiH 4 , Si 2 H
An i-type amorphous Si semiconductor thin film 2 is obtained by using 6 , SiF 4 , SiCl 4 , SiCl 4 -xHx and the like. On the other hand, diborane gas B 2 H 6 is usually used to obtain a p-type semiconductor, and phosphine gas PH 3 or arsine gas AsH 3 is usually used to obtain an n-type semiconductor.
It suffices to dope the respective source gases, and the conductivity of the amorphous Si semiconductor thin film 2 can be arbitrarily adjusted by adjusting the mixing ratio of these doping gases. In addition to this, the conductivity can also be adjusted by mixing GeH 4 , CH 4 and the like with the raw material gas to form the alloy-type amorphous Si semiconductor thin film 2.

【0009】プラズマCVDは比較的低温でアモルファ
スSi半導体薄膜2を被着形成することができるので、
使用できる薄片状基板1としてはガラスやセラミックス
基板は勿論のこと、ステンレス等の金属片や樹脂等の薄
板やフィルムも使用できる。また、薄片状基板1を導電
材とした場合はアモルファスSi半導体薄膜2との絶縁
を図るために、図3に示されるようにSi3N4 、又はSiO2
等の絶縁膜3をアモルファスSi半導体薄膜2の被着形
成に先立って薄片状基板1にプラズマCVDによって被
着形成する。その後、絶縁膜3の表面にアモルファスS
i半導体薄膜2を被着形成し、該アモルファスSi半導
体薄膜2の表面にSi3N4 、又はSiO2等の絶縁用の保護膜
4を被着形成する。この保護膜4によりアモルファスS
i半導体薄膜2を外部環境から保護し、劣化を防止して
いる。なお、絶縁膜3、アモルファスSi半導体薄膜
2、保護膜4はCVD装置に供給される原料ガスの種類
を変更することによって、薄片状基板1に連続的に被着
成形することができる。
Since the plasma CVD can deposit and form the amorphous Si semiconductor thin film 2 at a relatively low temperature,
As the flaky substrate 1 that can be used, not only a glass or ceramic substrate but also a metal plate such as stainless steel or a thin plate or film such as resin can be used. When the flaky substrate 1 is used as a conductive material, in order to insulate it from the amorphous Si semiconductor thin film 2, as shown in FIG. 3, Si 3 N 4 or SiO 2 is used.
Prior to the formation of the amorphous Si semiconductor thin film 2, the insulating film 3 is formed on the thin substrate 1 by plasma CVD. After that, amorphous S is formed on the surface of the insulating film 3.
The i semiconductor thin film 2 is deposited, and the insulating protective film 4 such as Si 3 N 4 or SiO 2 is deposited on the surface of the amorphous Si semiconductor thin film 2. Amorphous S is formed by this protective film 4.
The i semiconductor thin film 2 is protected from the external environment to prevent deterioration. The insulating film 3, the amorphous Si semiconductor thin film 2, and the protective film 4 can be continuously formed on the flaky substrate 1 by changing the type of the raw material gas supplied to the CVD apparatus.

【0010】続いて、保護膜4の所定表面をマスクキン
グしたうえエッチングを施し、入力電極、出力電極部位
の保護膜4を除去する。次に、除去した部分にNiCr
系合金や、Mgを下地としAlを上地とする多層膜等の
電極用金属を真空蒸着する。この時、電極の配置パター
ンは一対の入力電極5と一対の出力電極6とを設けて歪
ゲージ10を形成している。なお、図1においては一対
の入力電極5と一対の出力電極6とを各々交差して設け
てあるが、単結晶Siの結晶方位によって感度特性が制
限されることが無いので、自由に電極を配置して歪ゲー
ジ10を形成することができる。さらに、電極形状は、
電極の電流面積を増すために、クシ型電極としてもよ
く、また、電極の形成に先立って、電極位置に相当する
アモルファスSi半導体薄膜部分のみを、ドーピングガ
ス濃度を高めるなどの制御操作を行うことによって、ベ
ース部分の導電率より幾らか高めにして電極材料との接
触抵抗を小さくすることもできる。
Then, a predetermined surface of the protective film 4 is masked and then etched to remove the protective film 4 at the input electrode and output electrode portions. Next, NiCr is applied to the removed portion.
A system alloy or a metal for electrodes such as a multilayer film having Mg as a base and Al as a base is vacuum-deposited. At this time, the arrangement pattern of the electrodes is such that the pair of input electrodes 5 and the pair of output electrodes 6 are provided to form the strain gauge 10. Although a pair of input electrodes 5 and a pair of output electrodes 6 are provided so as to intersect with each other in FIG. 1, the sensitivity characteristics are not limited by the crystal orientation of the single crystal Si, so that the electrodes can be freely set. The strain gauge 10 may be arranged to form the strain gauge 10. Furthermore, the electrode shape is
In order to increase the current area of the electrode, a comb type electrode may be used, and prior to the formation of the electrode, a control operation such as increasing the doping gas concentration is performed only on the amorphous Si semiconductor thin film portion corresponding to the electrode position. Therefore, the contact resistance with the electrode material can be reduced by increasing the conductivity somewhat higher than that of the base portion.

【0011】このように構成されたものは、図4に示さ
れるようにアモルファスSi半導体薄膜2に歪ゲージ1
0を形成した薄片状基板1の一端をベース20に固定し
たカンチレバー型にすることによって加速度センサーと
して利用したり、図5に示されるように圧力導入管21
の端部にアモルファスSi半導体薄膜2に歪ゲージ10
を形成した薄片片状基板1の周縁を固定して、絶対圧な
らびに差圧型の圧力センサーとして利用でき、薄片状基
板1が外部からの応力を受けると、該薄片状基板1とと
もにアモルファスSi半導体薄膜2が変形し、該アモル
ファスSi半導体薄膜上に対向する一対の入力電極5と
出力電極6とよりなる歪ゲージ10は、アモルファスS
i半導体薄膜面に対して垂直方向の応力を感知して、ピ
エゾ抵抗効果によって電気信号の変位を出力するもので
ある。 また、薄片状基板1として、金属薄板や樹脂フ
ィルム等を用いれば、完成後のセンサーデバイスを、図
6に示されるように3次元形状の曲面を有する被測定面
に沿って設けることができ、3次元形状の応力測定が可
能となる。
As shown in FIG. 4, the strain gauge 1 thus constructed has a strain gauge 1 on an amorphous Si semiconductor thin film 2.
By using a cantilever type in which one end of the flaky substrate 1 on which 0 is formed is fixed to the base 20, it can be used as an acceleration sensor, or as shown in FIG.
Strain gauge 10 on the amorphous Si semiconductor thin film 2 at the end of
When the flaky substrate 1 is subjected to external stress, it can be used as an absolute pressure or differential pressure type pressure sensor by fixing the peripheral edge of the flaky substrate 1 on which the thin flaky substrate 1 is formed. 2 is deformed, and the strain gauge 10 composed of a pair of input electrode 5 and output electrode 6 facing each other on the amorphous Si semiconductor thin film is amorphous S
i The stress in the direction perpendicular to the semiconductor thin film surface is sensed, and the displacement of the electric signal is output by the piezoresistance effect. If a thin metal plate, a resin film or the like is used as the flaky substrate 1, the completed sensor device can be provided along the surface to be measured having a three-dimensional curved surface as shown in FIG. It is possible to measure stress in a three-dimensional shape.

【0012】図7は、外部からの応力を圧縮力として受
ける場合と、引張り力として受ける場合では、出力特性
が異なるので、用途に応じて歪の受ける方向性を考慮し
て薄片状基板1の両面にアモルファスSi半導体薄膜
2、2aを被着形成して両面に歪ゲージ10、10aを
設けた第2の実施例を示すもので、外部からの応力に対
して、一方のアモルファスSi半導体薄膜2には圧縮
力、他方のアモルファスSi半導体薄膜2aには引張り
力が作用し、各面の歪ゲージ10、10aはこれらの応
力に対応してそれぞれの出力信号を同時に出力するが、
これら2つの出力信号を補正回路によって、アモルファ
スSi半導体薄膜2、2aに加えられる応力の方向性に
よって生じる出力信号の差異を補正してより精度の高い
測定を行うことができる。
In FIG. 7, the output characteristics are different between the case where an external stress is applied as a compressive force and the case where it is applied as a tensile force. A second embodiment is shown in which the amorphous Si semiconductor thin films 2 and 2a are formed on both surfaces and the strain gauges 10 and 10a are provided on both surfaces. One of the amorphous Si semiconductor thin films 2 is resistant to external stress. Is applied to the amorphous Si semiconductor thin film 2a, and the strain gauges 10 and 10a on the respective surfaces simultaneously output respective output signals corresponding to these stresses.
A correction circuit for these two output signals can correct the difference in the output signals caused by the directionality of the stress applied to the amorphous Si semiconductor thin films 2 and 2a to perform more accurate measurement.

【0013】[0013]

【発明の効果】本発明は前記説明によって明らかなよう
に、アモルファスSi半導体薄膜上に入力電極と出力電
極を形成することにより、単結晶Siウエハーから切り
出して所定サイズに切断した単結晶Siチップの一部分
にエッチングや研摩によりダイヤフラムを形成する必要
がないので、製造工程が簡素化されるうえに歩留りが高
く、薄片状基板を金属や樹脂等の安価な材料を使用する
こともできるのでコストの低減が図れる。また、ピエゾ
抵抗層となるアモルファスSi半導体薄膜は被着形成時
に、比抵抗と膜厚を正確かつ容易に調整でき、ブリッジ
回路を用いることなく歪ゲージを形成することができる
ので、出力感度を良好なものとすることができる。ま
た、結晶面を有しないアモルファスSiのため、薄片状
基板の任意の箇所に任意の形状でピエゾ抵抗層を複数形
成することができ、しかも、薄片状基板を金属や樹脂と
したセンサーデバイスは自在に変形することが可能であ
るので、3次元的な曲面における応力分布の測定も可能
であるうえに、Siウエハーサイズによる制約がないの
で大面積の応力測定ができるなど、極めて自由度の高い
半導体歪変換素子を設計することが可能となり、利用範
囲を拡大することができるものである。従って、本発明
は従来の問題点を解決した半導体歪変換素子として業界
にもたらす益極めて大なものである。
As is apparent from the above description, the present invention provides a single crystal Si chip cut out from a single crystal Si wafer and cut into a predetermined size by forming an input electrode and an output electrode on an amorphous Si semiconductor thin film. Since it is not necessary to form the diaphragm by etching or polishing on a part, the manufacturing process is simplified and the yield is high, and it is also possible to use inexpensive materials such as metal and resin for the flaky substrate, reducing cost. Can be achieved. In addition, the amorphous Si semiconductor thin film that becomes the piezoresistive layer can precisely and easily adjust the specific resistance and the film thickness when it is deposited, and the strain gauge can be formed without using a bridge circuit, so that the output sensitivity is good. It can be anything. In addition, because amorphous Si does not have a crystal plane, it is possible to form multiple piezoresistive layers in any shape on the flaky substrate. Moreover, sensor devices using the flaky substrate as metal or resin are flexible. Since it can be deformed into a large area, it is possible to measure the stress distribution on a three-dimensional curved surface, and since there is no restriction due to the size of the Si wafer, it is possible to measure stress in a large area. The strain conversion element can be designed and the range of use can be expanded. Therefore, the present invention is a great advantage brought to the industry as a semiconductor strain conversion element which solves the conventional problems.

【図面の簡単な説明】[Brief description of drawings]

【図1】歪ゲージを片面に形成した本発明の第1の実施
例を示す平面図である。
FIG. 1 is a plan view showing a first embodiment of the present invention in which a strain gauge is formed on one surface.

【図2】同じく断面図である。FIG. 2 is a sectional view of the same.

【図3】絶縁膜を形成した第1の実施例を示す示す断面
図である。
FIG. 3 is a cross-sectional view showing a first embodiment in which an insulating film is formed.

【図4】加速度センサとして用いた斜視図である。FIG. 4 is a perspective view used as an acceleration sensor.

【図5】圧力センサとして用いた一部切欠側面図であ
る。
FIG. 5 is a partially cutaway side view used as a pressure sensor.

【図6】3次元曲面の測定に用いた断面図である。FIG. 6 is a cross-sectional view used for measuring a three-dimensional curved surface.

【図7】歪ゲージを両面に形成した本発明の第2の実施
例を示す断面図である。
FIG. 7 is a sectional view showing a second embodiment of the present invention in which strain gauges are formed on both sides.

【符号の説明】[Explanation of symbols]

1 薄片状基板 2 アモルファスSi半導体薄膜 4 保護膜 5 入力電極 6 出力電極 10 歪ゲージ 1 Flake substrate 2 Amorphous Si semiconductor thin film 4 Protective film 5 Input electrode 6 Output electrode 10 Strain gauge

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成6年1月12日[Submission date] January 12, 1994

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】全図[Correction target item name] All drawings

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図2】 [Fig. 2]

【図3】 [Figure 3]

【図6】 [Figure 6]

【図7】 [Figure 7]

【図1】 [Figure 1]

【図4】 [Figure 4]

【図5】 [Figure 5]

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 外部からの応力に応じて変形する薄片状
基板(1) の少なくとも一方の面に、該薄片状基板(1) と
は絶縁状態でp型、i型、n型のいずれかのアモルファス
Si半導体薄膜(2) を形成し、該アモルファスSi半導
体薄膜上に、一対の入力電極(5) と出力電極(6) とを設
けて歪ゲージ(10)を形成するとともに、該アモルファス
Si半導体薄膜(2)の表面に絶縁用の保護膜(4) を形成
したことを特徴とする半導体歪変換素子。
1. A p-type substrate, an i-type substrate, or an n-type substrate which is insulated from the flaky substrate (1) on at least one surface of the flaky substrate (1) that deforms in response to external stress. Of the amorphous Si semiconductor thin film (2), a pair of input electrodes (5) and output electrodes (6) are provided on the amorphous Si semiconductor thin film to form a strain gauge (10), and the amorphous Si semiconductor thin film (2) is formed. A semiconductor strain conversion element characterized in that a protective film (4) for insulation is formed on the surface of a semiconductor thin film (2).
JP31991293A 1993-12-20 1993-12-20 Semiconductor strain transducer Withdrawn JPH07176765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31991293A JPH07176765A (en) 1993-12-20 1993-12-20 Semiconductor strain transducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31991293A JPH07176765A (en) 1993-12-20 1993-12-20 Semiconductor strain transducer

Publications (1)

Publication Number Publication Date
JPH07176765A true JPH07176765A (en) 1995-07-14

Family

ID=18115624

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31991293A Withdrawn JPH07176765A (en) 1993-12-20 1993-12-20 Semiconductor strain transducer

Country Status (1)

Country Link
JP (1) JPH07176765A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105004456A (en) * 2015-08-18 2015-10-28 北京中航兴盛测控技术有限公司 High-performance thin film pressure sensor based on non-crystalline material
CN107462192A (en) * 2017-09-11 2017-12-12 重庆大学 A kind of surface acoustic wave high-temp strain sensor chip based on SOI and piezoelectric membrane and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105004456A (en) * 2015-08-18 2015-10-28 北京中航兴盛测控技术有限公司 High-performance thin film pressure sensor based on non-crystalline material
CN107462192A (en) * 2017-09-11 2017-12-12 重庆大学 A kind of surface acoustic wave high-temp strain sensor chip based on SOI and piezoelectric membrane and preparation method thereof

Similar Documents

Publication Publication Date Title
US4849730A (en) Force detecting device
US3858150A (en) Polycrystalline silicon pressure sensor
US5485753A (en) Piezoresistive silicon pressure sensor implementing long diaphragms with large aspect ratios
US4739381A (en) Piezoresistive strain sensing device
CN105241369A (en) MEMS strain gauge chip and manufacturing process thereof
EP0672898B1 (en) Semiconductor pressure sensor with polysilicon diaphragm and single-crystal gage elements and fabrication method therefor
US7808365B2 (en) Pressure sensor
GB2128404A (en) Piezoresistive transducer
KR100959005B1 (en) A pressure measuring sensor and manufacturing process
KR100432465B1 (en) Thin film piezoresistive sensor and method of making the same
US6635910B1 (en) Silicon strain gage having a thin layer of highly conductive silicon
US6453748B1 (en) Boron nitride piezoresistive device
JPH07176765A (en) Semiconductor strain transducer
JP3546151B2 (en) Distortion detecting element and method for manufacturing distortion detecting element
JPH07176766A (en) Orthogonal semiconductor pressure transducer
JPH0337534A (en) Semiconductor strain detecting apparatus
JPH01239882A (en) Semiconductor pressure sensor
KR101318260B1 (en) Semiconductor device and physical sensor using the same
JPS62266875A (en) Semiconductor pressure sensor
JPH06244438A (en) Manufacture of silicon semiconductor pressure gage
JPS62291073A (en) Semiconductor distortion detector
JPH09213638A (en) Method for manufacturing semiconductor thin film
Hase et al. SOI type pressure sensor for high temperature pressure measurement
JPH0697697B2 (en) Semiconductor pressure converter
JPH07335911A (en) Pressure sensor integrated with pressure receiving pipe

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20010306