JPH07176667A - Surface mounting semiconductor device - Google Patents

Surface mounting semiconductor device

Info

Publication number
JPH07176667A
JPH07176667A JP31878893A JP31878893A JPH07176667A JP H07176667 A JPH07176667 A JP H07176667A JP 31878893 A JP31878893 A JP 31878893A JP 31878893 A JP31878893 A JP 31878893A JP H07176667 A JPH07176667 A JP H07176667A
Authority
JP
Japan
Prior art keywords
lead
lead frame
semiconductor device
package
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31878893A
Other languages
Japanese (ja)
Inventor
Kenji Motai
建志 甕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP31878893A priority Critical patent/JPH07176667A/en
Publication of JPH07176667A publication Critical patent/JPH07176667A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To realize cost reduction of surface mounting semiconductor device by reducing the manufacturing process and facility. CONSTITUTION:In a surface mounting semiconductor device where a semiconductor chip 2 is mounted on a die pad 1a of a lead frame 1, a wire 3 is bonded between the semiconductor chip 2 and the wire connecting part 1c of outer lead 1b, and then the peripheral part is sealed with a resin package 4, the outer lead 1b of the lead frame 1 is set in flush with the bottom face of the resin package 4 and led out sideways therefrom. At the time of machining the lead frame 1, the outer lead part 1b is previously formed to raise the end part thereof so that it can be contained in the package 4 thus forming the wire connecting part 1c. This structure allows surface mounting of semiconductor chip as it is without requiring the forming of outer lead after molding or cutting of lead.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、リードフレームを用い
て組立てた樹脂封止形の表面実装型半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed surface mount type semiconductor device assembled using a lead frame.

【０００２】[0002]

【従来の技術】まず、本発明の実施対象となる表面実装
型半導体装置の従来構造を図２（ａ),（ｂ）に示す。図
において、１はリードフレーム、２はリードフレーム１
のダイパッド１ａにマウントした半導体チップ、３は半
導体チップ２とリードフレーム１のアウタリード１ｂと
の間に接続したボンディングワイヤ、４はトランスファ
モールド法などにより成形した樹脂パッケージである。2. Description of the Related Art First, FIGS. 2A and 2B show a conventional structure of a surface mount type semiconductor device to which the present invention is applied. In the figure, 1 is a lead frame, 2 is a lead frame 1.
3 is a semiconductor chip mounted on the die pad 1a, 3 is a bonding wire connected between the semiconductor chip 2 and the outer lead 1b of the lead frame 1, and 4 is a resin package molded by a transfer molding method or the like.

【０００３】ここで、リードフレーム１のダイパッド１
ａは、アウタリード１ｂとの間の絶縁距離を確保するた
めに、リードフレーム１の製作時にアウタリード１ｂの
高さよりも一段低く沈み込むように形成されており、ア
ウタリード１ｂは樹脂パッケージ４の厚みのほぼ中央部
から側方に突出している。また、アウタリード１ｂにつ
いては、リードフレーム１に対し樹脂パッケージ４をモ
ールドし、さらにリードカットした後に、フォーミング
（リード曲げ加工）を施してリード先端が樹脂パッケー
ジ４の底面と同じ高さに並ぶように成形されている。Here, the die pad 1 of the lead frame 1
In order to secure an insulation distance between the outer lead 1b and the outer lead 1b, a is formed so as to be recessed one step lower than the height of the outer lead 1b when the lead frame 1 is manufactured. It projects laterally from the center. As for the outer leads 1b, the resin package 4 is molded on the lead frame 1, the leads are further cut, and then the forming (lead bending process) is performed so that the lead tips are aligned at the same height as the bottom surface of the resin package 4. It is molded.

【０００４】[0004]

【発明が解決しようとする課題】ところで、前記した従
来の構造では、半導体装置の製造工程でモールド，リー
ドカットを行った後に、さらに別工程でフォーミング用
金型を用いてアウタリードを曲げ加工する必要がある。
このために製造設備，並びに工程数が多くなって半導体
装置の製作費がコストアップとなる。By the way, in the above-mentioned conventional structure, it is necessary to bend the outer leads using a forming die in another step after performing the molding and the lead cutting in the manufacturing process of the semiconductor device. There is.
Therefore, the number of manufacturing facilities and the number of steps are increased, and the manufacturing cost of the semiconductor device is increased.

【０００５】本発明は上記の点にかんがみなされたもの
であり、その目的は前記課題を解決し、製造設備，工程
を削減してコストダウンが図れるようにした表面実装型
半導体装置を提供することにある。The present invention has been made in view of the above points, and an object thereof is to provide a surface mount type semiconductor device which solves the above-mentioned problems and can reduce the cost by reducing manufacturing equipment and steps. It is in.

【０００６】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明の構成によれば、リードフレームのアウタリ
ードを樹脂パッケージの底面と同じ高さに揃えてパッケ
ージから側方へ直線状に引出すとともに、パッケージの
領域内でアウタリード部の端部を上方に立ち上げてワイ
ヤ接続部を形成するものとする。In order to achieve the above object, according to the structure of the present invention, the outer leads of the lead frame are aligned at the same height as the bottom surface of the resin package and are drawn out linearly from the package laterally. At the same time, the end portion of the outer lead portion is raised upward in the region of the package to form the wire connecting portion.

【０００７】また、前記構成におけるアウタリードのワ
イヤ接続部は、リードフレームの加工時に同時にフォー
ミングすることができる。Further, the wire connecting portion of the outer lead in the above structure can be simultaneously formed during the processing of the lead frame.

【０００８】[0008]

【作用】上記の構成によれば、アウタリードが樹脂パッ
ケージの底面と同じ高さに並んでパッケージより側方に
引出されているので、リードカットした後に改めてフォ
ーミングを施す必要なしに表面実装型の半導体装置が得
られる。また、アウタリードのワイヤ接続部に対する曲
げ加工をリードフレームを製作する際に同時に行うこと
で製造工程が増加することもない。According to the above structure, the outer leads are arranged at the same height as the bottom surface of the resin package and are drawn out to the side of the package. Therefore, it is not necessary to perform forming again after cutting the leads. The device is obtained. In addition, the bending process for the wire connection portion of the outer lead is performed at the same time when the lead frame is manufactured, so that the number of manufacturing processes does not increase.

【０００９】[0009]

【実施例】以下、本発明の実施例を図１（ａ),（ｂ）に
より説明する。なお、図中で図２と対応する同一部材に
は同じ符号が付してある。図１（ａ）において、リード
フレーム１のアウタリード１ｂには、あらかじめ樹脂パ
ッケージ４に収まる部分をダイパッド１ａよりも一段高
くなるように上方に折り曲げてあり、この立ち上がり部
分にワイヤ接続部１ｃが形成されている。このワイヤ接
続部１ｃは、金属リボンからリードフレーム１をプレス
加工する際に、同じ工程で同時に成形することができ
る。なお、１ｄはリードフレームのタイバーを示す。Embodiments of the present invention will be described below with reference to FIGS. 1 (a) and 1 (b). In the figure, the same members corresponding to those in FIG. 2 are designated by the same reference numerals. In FIG. 1A, the outer lead 1b of the lead frame 1 is bent upward in advance so that the portion that fits in the resin package 4 is one step higher than the die pad 1a, and the wire connection portion 1c is formed at this rising portion. ing. The wire connecting portion 1c can be simultaneously formed in the same process when the lead frame 1 is pressed from the metal ribbon. Note that 1d indicates a tie bar of the lead frame.

【００１０】そして、前記のリードフレーム１に対して
ダイパッド１ａに半導体チップ２をマウントし、さらに
半導体チップ２とアウタリード１ｂのワイヤ接続部１ｃ
との間にワイヤ３をボンディングした後、続くモールド
工程で樹脂パッケージ４を成形して樹脂封止し、最終工
程でアウタリードフレーム１ｂ，およびタイバー１ｄを
図示の切断箇所Ｘ−Ｘに沿ってリードカットして製品を
完成する。Then, the semiconductor chip 2 is mounted on the die pad 1a with respect to the lead frame 1, and the wire connecting portion 1c between the semiconductor chip 2 and the outer lead 1b.
After the wire 3 is bonded between and, the resin package 4 is molded and resin-sealed in the subsequent molding step, and in the final step, the outer lead frame 1b and the tie bar 1d are lead along the cutting point XX shown in the drawing. Cut to complete the product.

【００１１】図１（ｂ）はリードカットした後の完成製
品の外観図を示しており、この図から明らかなようにア
ウタリード１ｂは樹脂パッケージ４の底面と同じ高さか
ら側方に突出している。したがって、改めて樹脂パッケ
ージ４から引出したアウタリード１ｂにフォーミング
（リード曲げ加工）を施す必要はなく、このままの形で
製品をプリント配線板に表面実装することができる。FIG. 1B shows an external view of the finished product after lead cutting. As is apparent from this figure, the outer leads 1b project laterally from the same height as the bottom surface of the resin package 4. . Therefore, it is not necessary to form (lead bending) the outer leads 1b drawn out from the resin package 4 again, and the product can be surface-mounted on the printed wiring board as it is.

【００１２】[0012]

【発明の効果】以上述べたように、本発明の構成によれ
ば、モールド，リードカットを行った後に改めてアウタ
リードをフォーミングする必要がなく、したがってフォ
ーミング用の金型も不要となり、従来構造と比べて製造
工程数を削減して表面実装型半導体装置を安価に製作し
て提供できる。As described above, according to the structure of the present invention, it is not necessary to form the outer lead again after performing the molding and the lead cutting, and therefore the forming die is not necessary, which is more than the conventional structure. Thus, the number of manufacturing steps can be reduced, and a surface mount semiconductor device can be manufactured and provided at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例による表面実装型半導体装置の
構成図であり、（ａ）は樹脂パッケージをモールドする
以前の段階での組立構造の斜視図、（ｂ）は完成製品の
外観斜視図1A and 1B are configuration diagrams of a surface mount semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a perspective view of an assembly structure before a resin package is molded, and FIG. 1B is an external perspective view of a finished product. Figure

【図２】従来における表面除霜型半導体装置の構成図で
あり、（ａ）は完成製品の外観斜視図、（ｂ）は断面図2A and 2B are configuration diagrams of a conventional surface defrosting type semiconductor device, in which FIG. 2A is an external perspective view of a finished product, and FIG.

【符号の説明】 １ リードフレーム １ａ ダイパッド １ｂ アウタリード １ｃ ワイヤ接続部 ２ 半導体チップ ３ ボンディングワイヤ ４ 樹脂パッケージ[Explanation of reference numerals] 1 lead frame 1a die pad 1b outer lead 1c wire connecting portion 2 semiconductor chip 3 bonding wire 4 resin package

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】リードフレームのダイパッドに半導体チッ
プをマウントし、かつ半導体チップとリードフレームの
アウタリードとの間にワイヤボンディングを施した上
で、その周域を樹脂パッケージで封止した表面実装型半
導体装置において、リードフレームのアウタリードを樹
脂パッケージの底面と同じ高さに揃えてパッケージから
側方へ直線状に引出すとともに、パッケージの領域内で
アウタリード部の端部を上方に立ち上げてワイヤ接続部
を形成したことを特徴とする表面実装型半導体装置。1. A surface mount semiconductor in which a semiconductor chip is mounted on a die pad of a lead frame, wire bonding is performed between the semiconductor chip and an outer lead of the lead frame, and the peripheral region is sealed with a resin package. In the equipment, align the outer leads of the lead frame at the same height as the bottom surface of the resin package and pull out linearly from the package to the side, and raise the end of the outer lead part in the area of the package to raise the wire connection part. A surface-mounted semiconductor device characterized by being formed. 【請求項２】請求項１記載の半導体装置において、アウ
タリードのワイヤ接続部をリードフレームの加工時に同
時にフォーミングしたことを特徴とする表面実装型半導
体装置。2. The surface-mounted semiconductor device according to claim 1, wherein the wire connecting portions of the outer leads are simultaneously formed during processing of the lead frame.
JP31878893A 1993-12-20 1993-12-20 Surface mounting semiconductor device Pending JPH07176667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31878893A JPH07176667A (en) 1993-12-20 1993-12-20 Surface mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31878893A JPH07176667A (en) 1993-12-20 1993-12-20 Surface mounting semiconductor device

Publications (1)

Publication Number Publication Date
JPH07176667A true JPH07176667A (en) 1995-07-14

Family

ID=18102954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31878893A Pending JPH07176667A (en) 1993-12-20 1993-12-20 Surface mounting semiconductor device

Country Status (1)

Country Link
JP (1) JPH07176667A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2755540A1 (en) * 1996-10-01 1998-05-07 Int Rectifier Corp CONDUCTOR FRAME WITH CONNECTING WIRES, HOUSING COMPRISING THE SAME, AND METHOD FOR MANUFACTURING THE SAME

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2755540A1 (en) * 1996-10-01 1998-05-07 Int Rectifier Corp CONDUCTOR FRAME WITH CONNECTING WIRES, HOUSING COMPRISING THE SAME, AND METHOD FOR MANUFACTURING THE SAME

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